LC749870W

Ordering number : ENA1957 CMOS IC LC749870W Overview Silicon gate NTSC/PAL/SECAM Digital Video Decoder The LC749870W is a digital video decoder that converts NTSC, PAL and SECAM video signals into digital component video signals. Digital video data can be output easily by inputting NTSC, PAL and SECAM video signals. The output data format is compatible with ITU-R BT.656. Features • Supports NTSC (M, 4.43), PAL (B, D, G, H, I, M, N, 60), and SECAM video signal inputs. • On-chip video switch that supports 4 video inputs • 10-bit ADC (sampling at 27MHz) • Automatic gain control (AGC) function • Digital clamp circuit • Digital automatic color control (ACC) circuit • Sync separation circuit • Signal-to-noise (S/N) detection capabilities • Non-standard signal detection function • No signal detection function • Adaptive two-dimensional Y/C separation circuit • NTSC/PAL/SECAM demodulator circuit • Clock rate conversion circuit • Picture quality improvement (sharpness, contrast, brightness, CTI, UV gain, HUE) • 8-bit ITU-R BT.656 output format ITU-R BT.656 (8bit YCbCr 4:2:2 with SAV/EAV) 8bit YCbCr 4:2:2 with Syncs • I2C control (100k/400kbps, 2 types of slave address selectable) Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment (home appliances, AV equipment, communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee thereof. If you should intend to use our products for applications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our customer shall be solely responsible for the use. Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer' s products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer' s products or equipment. 62911HKPC 20110419-S00002 No.A1957-1/45 LC749870W IC Specifications • Power supply voltage I/O: Analog 3.3V, Digital 1.8V or 3.3V Core: Analog 1.8V, Digital 1.1V • Maximum operating frequency: 30MHz • Package: SQFP64 Applications • Small-size monitors Specifications Absolute Maximum Ratings at Ta = 25°C, DVSS = 0V, AVSS = 0V Parameter Maximum supply voltage (I/O) Symbol DVDD33 XVDD33 AVDD33 Maximum supply voltage (Core) Digital input voltage Digital output voltage Operating temperature Storage temperature DVDD11 XVDD11 VI VO Topr Tstg -0.3 to +3.95 V Conditions Ratings unit -0.3 to +1.8 -0.3 to DVDD33+0.3 -0.3 to DVDD33+0.3 -40 to +85 -55 to +125 V V V °C °C Allowable Operation Ranges at Ta = 25°C, DVSS = 0V, AVSS = 0V Parameter Supply voltage (I/O) Symbol AVDD33 XVDD33 DVDD33 Supply voltage (Core) Input voltage range DVDD11 XVDD11 VIN Conditions min 3.0 1.7 1.0 0 typ 3.3 1.8 or 3.3 1.1 max 3.6 3.6 1.2 DVDD33 unit V V V V DC Characteristics at Ta = -30 to +70°C, DVDD33 = 1.7 to 3.63V, AVDD33 = 3.0 to 3.63V, DVDD11 = 1.0 to 1.2V Parameter Input high-level voltage Symbol VIH Conditions CMOS level inputs CMOS level Schmitt inputs Input low-level voltage VIL CMOS level inputs CMOS level Schmitt inputs Input high-level current IIH VI = VDD VI = VDD, with pull-down resistance Input low-level current Output high-level voltage Output low-level voltage Output leakage current Pull-down register IIL VOH VOL IOZ RDN VI = VSS CMOS (Pin E/G: IOH = -4mA, F: IOH = -6mA) CMOS When in high-impedance output mode DVDD11 = 1.1V, DVDD33 = 3.3V DVDD11 = 1.1V, DVDD33 = 1.8V Operating current drain IDDOP Output open, tck=27MHz, natural image. Ta = 25°C, DVDD33 = 3.3V, AVDD33 = 3.3V, DVDD11 = 1.1V Output open, tck=27MHz, natural image. Ta = 25°C, DVDD33 = 1.8V, Static current drain *1 IDDST AVDD33 = 3.3V, DVDD11 = 1.1V Output open, VI = VSS, Ta = 25°C 38 10 mA μA 42 mA -10 159 95 -10 VDD-0.4 0.4 10 min 0.7DVDD33 0.7DVDD33 0 0 0.3DVDD33 0.3DVDD33 10 100 typ max unit V V V V μA μA μA V V μA kΩ kΩ *1: There is an input pin which builds in pull down resistance. Note that there is no guarantee about static consumption current depending on circuit configuration. No.A1957-2/45 LC749870W Package Dimensions unit : mm (typ) 3190A 12.0 48 49 33 32 0.5 10.0 64 1 0.5 (1.25) (1.5) 17 16 0.18 0.15 1.7max 0.1 SANYO : SQFP64(10X10) Pin Assignment 10.0 12.0 CKO DVSS GPIO0 DATA6 DATA4 DATA7 DVSS DATA5 DATA3 DATA2 DATA1 2 I CSEL DATA0 DVSS DVDD11 DVDD33 64 1 DVDD33 DVDD11 GPIO3 DVSS GPIO1 VS CK13 HS DE GPIO2 DVDD11 FIELD DVSS XVSS XVDD11 XOUT 49 48 LC749870W 16 17 33 32 XIN XVDD33 XVSS AFEVRTC SVO AVSS33 AIN0 AVDD33 AIN1 AVSS33 AIN2 AVDD33 AIN3 AVSS33 VRB VRT INTREQ DVSS MD0 DVSS MD2 SCL MD1 SDA RESET PDWN DVDD11 TEST DVSS DVSS REFPKV REFNKV Top view No.A1957-3/45 LC749870W Pin Descriptions Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Symbol I/O CKO DVSS GPIO0 DATA6 DATA4 DATA7 DVSS DATA5 DATA3 DATA2 DATA1 I CSEL DATA0 DVSS DVDD11 DVDD33 INTREQ DVSS MD0 DVSS MD2 SCL MD1 SDA RESET PDWN DVDD11 TEST DVSS DVSS REFPKV REFNKV VRT VRB AVSS33 AIN3 AVDD33 AIN2 AVSS33 AIN1 AVDD33 AIN0 AVSS33 SVO AFEVRTC XVSS XVDD33 XIN XOUT XVDD11 2 I/O Type Type F CMOS GND G G G G CMOS CMOS CMOS CMOS GND G G G G C G CMOS CMOS CMOS CMOS CMOS CMOS GND Connected to Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Analog Analog Analog Analog GND A Analog Voltage A GND A Analog Voltage A GND A A GND I/O Voltage H H CMOS CMOS Core Voltage Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Digital Digital Digital Digital Digital X’tal input X’tal output AFE SVO output Interrupt (“H” active) Video signal output Video signal output Video signal output Video signal output For test Video signal output Video signal output Notes Data synchronous clock output O P I/O I/O I/O I/O P I/O I/O I/O I/O I I/O P P P O P I P I I I I/O I I P I P P I I I I P I P I P I P I P O I P P I O P Video signal output (MSB) I2C slave select L = 0x88, H = 0x8A Video signal output (LSB) Core voltage I/O voltage E CMOS GND D CMOS GND D D D G B B CMOS CMOS CMOS CMOS CMOS CMOS Core voltage C CMOS GND GND A A A A For test (Connect to GND) For test (Connect to GND) I2C clock For test (Connect to GND) I2C data input/output System reset (“L” active) Power down control For test (Connect to GND) ADC top reference buffer-amp input ADC bottom reference buffer-amp input ADC top reference voltage input ADC bottom reference voltage input Video signal input (CVBS) Video signal input (CVBS) Video signal input (CVBS) Video signal input (CVBS) ADC D-range control voltage external input Continued on next page. No.A1957-4/45 LC749870W Continued from preceding page. Pin No. 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Pin symbol I/O XVSS DVSS FIELD DVDD11 GPIO2 DE HS CK13 VS GPIO1 DVSS GPIO3 DVDD11 DVDD33 P P I/O P I/O I/O I/O O I/O I/O P I/O P P G G G G F G G G I/O Type Type GND GND CMOS Core voltage CMOS CMOS CMOS CMOS CMOS CMOS GND CMOS Core voltage I/O voltage Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital For test For test Data enable signal Horizontal sync signal Clock output (13.5MHz) Vertical sync signal For test Field signal Connected to Notes No.A1957-5/45 LC749870W Pin Circuits I/O type A Function Analog input/output Equivalent Circuit Applicable Pins AIN0, AIN1, AIN2, AIN3, VRT, VRB, REFPKV, REFNKV, SVO, AFEVRTC B Schmitt trigger CMOS input PDWN, RESET C CMOS input with built-in pull-down resistor I2CSEL, TEST D CMOS input SCL, MD0, MD1, MD2 E 2mA/4mA switching 3-STATE drive CMOS output INTREQ F 4mA/8mA switching 3-STATE drive CMOS output CKO, CK13 G 2mA/4mA switching 3-STATE drive CMOS input/output SDA, GPIO0, GPIO1, GPIO2, GPIO3, DATA0, DATA1, DATA2, DATA3, DATA4, DATA5, DATA6, DATA7, FIELD, DE, VS, HS H Oscillator XIN, XOUT No.A1957-6/45 LC749870W Pin Connection 1) ADC and its peripherals REFPKV VRT VRB REFNKV 0.1μF AIN* 0.1μF 10μF 10μF 0.1μF AFEVRTC Capacitors must be placed as close as possible to the IC. 2) Unused Pin Handling (Please be sure to perform except input open processing) AIN0 to AIN3: Open PDWN: Pull up TEST, MD0, MD1, MD2: Pull down RESET: Must always be configured for input. GPIO0 to GPIO3: Open DATA0 to DATA7: Open FIELD, DE, VS, HS: Open CKO, CK13: Open INTREQ: Open SVO: Open No.A1957-7/45 Block Diagram LC749870 CKO SRAM SRAM SRAM CK13 XIN RESET APC AIN0 Digital Clamp AGC MUX Clock Rate Conversion SECAM Demodulation 2D Y/C Separation Sync Separation Timing Gen NT/PAL Demodulation DATA[7:0] Sharpness Contrast Brightness Output Formatter CTI HUE UV Gain HS VS DE FIELD AIN1 LC749870W AIN2 AFE + ADC 1ch Data Interpolation LPF AIN3 TEST INTREQ PDWN IC 2 SCL SDA I CSEL 2 No.A1957-8/45 LC749870W Input/Output Timing 1) Input clock timing tHI XIN tLI tCK DVDD33/2 Pin Name XIN Parameter Symbol tCK min typ 37 50 max unit ns % Clock cycle Duty 2) Output data timing tHO CKO tAC tLO tCK DVDD33/2 Output data DVDD33/2 Pin Name CKO Parameter Symbol tCK min typ 37 50 max unit ns % 3 ns Clock cycle Duty Output data delay time (DVDD33 = 2.6 to 3.6V) Pins E,G: 4mA setting Pin F: 8mA setting Output data delay time (DVDD33 = 2.6 to 3.6V) Pins E,G: 2mA setting Pin F: 4mA setting Output data delay time (DVDD33 = 1.7 to 1.9V) Pins E,G: 4mA setting Pin F: 8mA setting Output data delay time (DVDD33 = 1.7 to 1.9V) Pins E,G: 2mA setting Pin F: 4mA setting tAC -3 tAC -3 6 ns DATA*, HS,VS,DE,FIELD, INTREQ tAC -5 4 ns tAC -6 9 ns No.A1957-9/45 LC749870W Register Specifications BANK0 (AFE + ADC) Register Specification Subaddress Bit 7 6 5 4 00H 3 2 I2C_ADCPWDB 1 0 7 6:5 01H 4 3:2 1:0 7 02H 6 5:0 7 03H 3:1 0 5:4 04H 3 2:0 7 6 5 05H 4 3 2 1 0 I2C_LPFPWDB I2C_AINSEL I2C_CLPLPFON I2C_SCARTON 1 1 1 2 1 2 2 1 1 6 1 3 1 2 1 3 1 1 1 1 1 1 1 1 For test Input switch control LPF enable control For test For test AGC mode control For test For test For test For test For test For test For test For test 1 1 Power down control Name I2C_BGRPWDB I2C_SVOPWDB I2C_ SELFCLPPWDB I2C_AFEPWDB BitSize 1 1 1 1 Function Name Functions Band gap reference power down control 0: Power down 1: Normal operation 1: SVO AMP circuit ON AFE SVO AMP power down control 0: SVO AMP circuit OFF 0: Self clamp OFF 0: AFE power down 0: Power down 0: Power down 0: Power down 0: Power down 0: Power down 00: AIN0 AFE self clamp circuit power down control 1: Self clamp ON 1: AFE normal operation AFE power down control ×2 AMP circuit and ×2 AMP bias circuit power down control 1: Normal operation 1: Normal operation 1: Normal operation 1: Normal operation 1: Normal operation 10: AIN2 11: AIN3 Reference voltage generation circuit 1 power down control Reference voltage generation circuit 2 power down control Clock generation circuit power down control LPF buffer circuit power down control AFE 4-input selector control signal (when in normal operation) 01: AIN1 LPF enable control of AFE self clamp circuit 0: LPF OFF For test Normally set to 0H For test Normally set to 0H AFE D-range control voltage external input select control 0: AGC mode For test Normally set to 0H For test Normally set to 00H For test Normally set to 0H For test Normally set to 0H For test Normally set to 0H For test Normally set to 0H For test Normally set to 1H For test Normally set to 4H For test Normally set to 0H For test Normally set to 0H For test Normally set to 0H Reserved Reserved Reserved Reserved For test Normally set to 0H 1: Non-AGC mode 1: LPF ON Initial value 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 00H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H Continued on next page. No.A1957-10/45 LC749870W Continued from preceding page. Subaddress Bit 7 6 5 4 06H 3 2 1 0 7 6 5 4 07H 3 2 1 0 1 08H 0 09H to 0FH 7 10H 0 7:6 11H 1:0 12H 0 6:4 13H 2:0 14H 15H 16H 7:0 7:0 7:0 3 8 8 8 For test I2C_CKINV 2 1 3 For test Clock output invert 1 2 For test For test I2C_SRST 1 Soft reset Software reset of digital video signal processing block 0: Reset ON For test Normally set to 0H For test Normally set to 0H For test Normally set to 0H Clock output (CKO) invert control 0: Normal For test Normally set to 0H For test Normally set to 0H For test Normally set to 0H For test Normally set to 0H For test Normally set to 0H 1: Invert 1: Reset OFF 0H 0H 0H 0H 0H 0H 0H 00H 00H 00H I2C_IOSEL1 1 I2C_IOSEL2 1 1 1 1 1 Clock output current drive capability Signal output current drive capability 1 1 1 1 1 1 1 1 For test Name BitSize 1 1 1 1 Function Name For test Normally set to 0H For test Normally set to 0H For test Normally set to 0H For test Normally set to 0H For test Normally set to 0H For test Normally set to 0H For test Normally set to 0H For test Normally set to 0H For test Normally set to 0H For test Normally set to 0H For test Normally set to 0H For test Normally set to 0H For test Normally set to 0H For test Normally set to 0H For test Normally set to 0H For test Normally set to 0H Clock output current drive capability switching 0: 4mA 0: 2mA 1: 8mA 1: 4mA Signal output current drive capability switching Functions Initial value 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H No.A1957-11/45 LC749870W BANK1 (Digital Video Signal Processing Block 1) Register Specifications Subaddress Bit 5:4 00H 0 7:6 01H 5:4 3:0 7:3 02H 2:0 I2A_TMCTRL 3 Auto mode switching I2A_ACCON I2A_ACCFRAME I2A_ACCSELAMP 1 2 2 4 5 For test ACC control Number of update frames For test ACC amplifier fixed mode Name BitSize 2 Function Name For test For test Normally set to 0H For test Normally set to 0H ACC ON/OFF switching 00: OFF 01: ON 1x: Amplifier fixed 10: 4 frames 11: 8 frames Number of update frame select 00: 1 frame For test Normally set to 0H ACC amplifier fixed mode Gain adjustment 000: Auto 100: PAL-M 03H 04H 05H 06H 07H 08H 09H 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:5 0AH 4 3:0 7:4 0BH 3:0 7 0CH 6:0 0DH 0EH 0FH 10H 7:0 7:0 7:0 7:4 11H 3:0 7:6 5:4 12H 3 2:0 1 3 For test 4 2 2 For test For test 7 8 8 8 4 For test For test For test For test For test 4 1 For test 8 8 8 For test 8 8 8 8 3 1 4 4 For test For test For test For test For test For test For test For test For test For test Normally set to 20H For test Normally set to 80H For test Normally set to 40H For test Normally set to 10H For test Normally set to 80H For test Normally set to 00H For test Normally set to 80H For test Normally set to 5H For test Normally set to 0H For test Normally set to 2H For test Normally set to 3H For test Normally set to 3H For test Normally set to 0H For test Normally set to 18H For test Normally set to A0H For test Normally set to 60H For test Normally set to 80H For test Normally set to CH For test Normally set to 8H For test Normally set to 3H For test Normally set to 3H For test Normally set to 1H For test Normally set to 0H -5 to +26dB 010: NTSC-4.43 110: PAL-60 011: PAL Auto/manual mode switching 001: NTSC-M 101: PAL-N 0H 111: SECAM 20H 80H 40H 10H 80H 00H 80H 5H 0H 2H 3H 3H 0H 18H A0H 60H 80H CH 8H 3H 3H 1H 0H 01: 2 frames Functions Initial value 0H 0H 1H 0H 0H 00H Continued on next page. No.A1957-12/45 LC749870W Continued from preceding page. Subaddress Bit 6:4 13H 1:0 14H 15H 16H 7:0 7:0 7:0 2 8 8 8 For test For test Name BitSize 3 Function Name For test For test Normally set to 0H For test Normally set to 2H For test Normally set to 96H For test Normally set to 64H For test Normally set to 64H Auto mode switching (It takes effect at I2A_TMCTRL=3’h0.) 0000: Manual mode 0001: Auto0 (NTSC/PAL) 0010: Auot1 (PAL/SECAM) 0011: Auto2 (NTSC/PAL-N/PAL-M) 7:4 I2A_ATMODE 4 Video system auto-detect switch 0100: Auto3 (NTSC/PAL/SECAM) 0101: Auto4 (NTSC/PAL/SECAM/PAL-N/PAL-M) 0110: Auto5 (Auto0+NTSC-443/PAL-60) 0111: Auto6 (Auto1+NTSC-443/PAL-60) 17H 1000: Auto7 (Auto2+NTSC-443/PAL-60) 1001: Auto8 (Auto3+NTSC-443/PAL-60) 1010: Auto9 (Auto4+NTSC-443/PAL-60) 1011 to 1111: Full Fsc select at manual mode 3:2 I2A_FSCSEL 2 Fsc select Scanning line number select NTSC/PAL select 00: 3.579545MHz 10: 3.57561149MHz 1 0 7:6 5:4 18H 1 0 19H 1AH 6:0 6:0 2 1BH 1 0 1CH 6:0 I2A_SECAMSEL I2A_DCON I2A_DCLINE I2A_STDLEVY 1 1 7 For test 7 1 1 1 7 Digital clamp ON/OFF setting Detection level update unit switching For test Pedestal level setting For test SECAM select I2A_SCANSEL I2A_NTPALSEL 1 1 2 For test 2 0: 525i 0: NTSC For test Normally set to 3H For test Normally set to 0H For test Normally set to 1H SECAM select at manual mode 0: not SECAM For test Normally set to 7FH For test Normally set to 00H Digital clamp ON/OFF setting 0: OFF 1: ON 1: Each line Pedestal level update unit switching 0: Each frame For test Normally set to 0H Target pedestal level setting Level setting range: 236 to 363LSB Digital clamp time constant setting 7:5 1DH 4:0 1EH 1FH 6:0 4:0 I2A_FRAMEDC 5 7 5 Update field number setting For test For test I2A_TCDC 3 Time constant setting 000: Time constant none 100: 1/16 101: 1/32 001: 1/2 010: 1/4 111: 1/128 10H 00H 17H 011: 1/8 0H 110: 1/64 1: SECAM 1: 625i 1: PAL 01: 4.43361875MHz 11: 3.58205625MHz 0H 0H 3H 0H 1H 0H 7FH 00H 1H 0H 0H 40H 1H FH Functions Initial value 0H 2H 96H 64H 64H Scanning line number select at manual mode NTSC/PAL select at manual mode Pedestal level update field number setting Setting range: 0 to 31 fields For test Normally set to 00H For test Normally set to 17H Continued on next page. No.A1957-13/45 LC749870W Continued from preceding page. Subaddress Bit Name BitSize Function Name Functions LPF characteristic switching for sync separation 7 I2A_FILSEL 1 LPF characteristic switch (It takes effect at I2A_AUTOFIL = 1’b0.) 0: Cutoff frequency 1: Cutoff frequency 6 20H 5 4 3:0 21H 7:0 7 6 5 22H 4 I2A_MANMODE 1 Input signal system 2:0 I2A_TVMODE 3 setting 1 1 4 For test 8 1 For test 1 1 I2A_AUTOFIL 1 LPF characteristic auto-switching setting For test For test separation 0: OFF For test Normally set to 1H For test Normally set to 0H For test Normally set to FH For test Normally set to 55H For test Normally set to 1H For test Normally set to 0H Input signal system auto/manual setting 0: Auto setting 0: Auto setting 1: Manual setting 1: Manual setting Input signal line number auto/manual setting Input signal system setting (It takes effect at I2A_MANMODE[1] = 1’b1) 000: NTSC-M 011: PAL-GBI 6 23H I2A_INSIG 1 001: PAL-M 100: SECAM 1H 010: PAL-N 0H 1: ON 1H 0H FH 55H 1H 0H 0H 0H 0.35MHz 1.4MHz 1H 1H Initial value LPF characteristics automatic switching setting for sync Input signal line number setting (It takes effect at I2A_MANMODE[0] = 1’b0) 0: 625 lines 5:4 3:0 7 5:4 24H 3:2 I2A_LEVAD 2 I2A_SLDET I2A_TCLEV 2 4 1 2 For test For test Slice level setting Slice level time constant setting For test Normally set to 1H For test Normally set to 1H Sync separation slice level auto-setting 0: Manual setting 00: 1/2 01: 1/4 1: Auto setting 10: 1/8 11: 1/16 10: 100LSB 11: 120LSB Slice level time constant setting Slice level initial value setting Initial slice level setting 00: 60LSB 01: 80LSB As for an initial value of the slice level, the above value is added to the detected sync tip level. Slice level Level setting 25H 7:0 I2A_SLST 8 range: 236 to 363LSB setting 7:4 26H 3:0 7:4 27H 3:2 1:0 7:4 28H 3:0 4 4 4 2 For test 2 4 For test For test 4 Slice level setting (It takes effect at I2A_SLDET = 1’b0) Settable in 4 LSB units Setting range: 0 to 1020LSB For test Normally set to 7H For test Normally set to 9H For test Normally set to 7H For test Normally set to 3H For test Normally set to 0H For test Normally set to 3H For test Normally set to 1H 7H 9H 7H 3H 0H 3H 1H 08H 3H 1: 525 lines 1H 1H 1H 1H Continued on next page. No.A1957-14/45 LC749870W Continued from preceding page. Subaddress Bit 7 29H 6:4 2:0 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 7:0 7:0 7:0 7:0 6:4 5:0 5:0 7:0 7 6 32H 5 4 3:0 33H 34H 35H 7:0 7:0 7:0 6 5 36H 4 2:0 7:5 37H 4:0 7:5 38H 4:0 I2A_HBEND 5 I2A_FIXLN I2A_VSTART I2A_VBSTART I2A_HBSTART I2A_VBWIDTH 1 3 3 5 3 Name I2A_HSPAD BitSize 1 3 For test 3 8 8 For test 8 8 3 6 6 8 1 1 For test 1 1 For test 4 8 8 8 1 1 For test For test For test For test For test Line number fixed mode ON/OFF setting V-sync positioning V-blank positioning H-blank rising positioning V-blank width adjustment H-blank falling positioning H-sync positioning For test For test Function Name For test For test Normally set to 1H For test Normally set to 1H For test Normally set to 7H For test Normally set to 04H For test Normally set to 14H For test Normally set to 00H For test Normally set to 03H For test Normally set to 4H For test Normally set to 02H For test Normally set to 01H H-sync position adjustment For test Normally set to 0H For test Normally set to 1H For test Normally set to 1H For test Normally set to 1H For test Normally set to 0H For test Normally set to CBH For test Normally set to CAH For test Normally set to CDH For test Normally set to 1H For test Normally set to 0H Line number fixed mode ON/OFF setting 0: OFF 1: ON Functions Initial value 1H 1H 7H 04H 14H 00H 03H 4H 02H 01H 05H 0H 1H 1H 1H 0H CBH CAH CDH 1H 0H 1H 3H 3H 0FH 3H 0FH V-sync position adjustment V-blank position adjustment H-blank rising position adjustment V-blank width adjustment H-blank falling position adjustment Continued on next page. No.A1957-15/45 LC749870W Continued from preceding page. Subaddress 39H 3AH 3BH 3CH 3DH 3EH 3FH 40H 41H 42H 43H Bit 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7 I2A_NSDON 6 44H 4 3:2 1:0 5 45H 3:2 1:0 46H 47H 4:0 5:0 5 3 48H 2 1 49H 4AH 4BH 7:0 7:0 7:0 6:4 4CH 3:0 I2A_FIXGAIN 4 I2A_EXAGCON I2A_SYNLEV I2A_FRMCNT 1 1 8 For test 8 8 3 Sync level setting Update field number setting Fixed gain setting For test External AGC ON/OFF setting I2A_NSDTHH I2A_NSDTHL 1 2 2 1 2 2 5 For test 6 1 1 For test For test For test No signal detection threshold setting For test For test For test 1 Name BitSize 8 8 8 8 8 8 8 8 8 8 8 1 No signal detection ON/OFF setting Function Name For test For test For test For test For test For test For test For test For test For test For test For test Normally set to 50H For test Normally set to 10H For test Normally set to 24H For test Normally set to F1H For test Normally set to 93H For test Normally set to 50H For test Normally set to 30H For test Normally set to 18H For test Normally set to 25H For test Normally set to 23H For test Normally set to C8H No signal detection ON/OFF setting 0: OFF 1: ON Forced no signal mode ON/OFF setting (It takes effect at I2A_NSDON[1] = 1’b0) 0: OFF For test Normally set to 0H Threshold setting where signals can be measured Threshold setting where no signal can be measured For test Normally set to 0H For test Normally set to 1H For test Normally set to 1H For test Normally set to 10H For test Normally set to 3FH For test Normally set to 0H For test Normally set to 0H For test Normally set to 0H External AGC ON/OFF setting 0: OFF For test Normally set to 00H For test Normally set to 00H AGC target sync level setting Setting range: 158 to 413LSB AGC update field number setting Fixed gain setting Setting range: -6 to +9dB 1: ON 1: ON 0H 0H 1H 0H 1H 1H 10H 3FH 0H 0H 0H 0H 00H 00H 80H 0H 6H 1H Functions Initial value 50H 10H 24H F1H 93H 50H 30H 18H 25H 23H C8H 1H Continued on next page. No.A1957-16/45 LC749870W Continued from preceding page. Subaddress Bit 7:6 4DH 4:0 7:6 4EH 4:0 5 I2A_EXAGCINIT I2A_AMPLIMIT 5 2 Name I2A_TCAGC BitSize 2 Function Name Time constant setting External AGC gain value setting Amplifier limit switching For test Functions AGC time constant setting 00: No time constant 01: 1/2 10: 1/4 11: 1/8 Initial value 0H 0FH 0H 00H External AGC initial gain value setting AGC amplifier limit switching 00: ±3dB For test Normally set to 00H Noise detection results update field number setting 000: 1 field 010: 4 fields 100: 16 fields 110: 64 fields For test Normally set to 0FH For test Normally set to 2H For test Normally set to 0H Threshold value setting of noise detection System detection select 001: 2 fields 011: 8 fields 101: 32 fields 111: 128 fields 01: ±6dB 10: ±9dB 11: ±12dB 7:5 4FH I2A_NLFIELD 3 Update field number setting 0H 4:0 5:4 50H 3:0 51H 52H 6:0 7:0 - 5 2 4 For test For test For test Noise detection threshold setting 0FH 2H 0H 0C80H I2A_NLTH 15 5:4 I2A_SELNTPAL 2 System detection select 00: Both NTSC/PAL (Line number is distinguished.) 01: Only NTSC 10: Only PAL 11: Both NTSC/PAL 0H 53H 2 I2A_AUTODET 1 System auto-detection ON/OFF setting Non-standard 0 I2A_NOSTDDET 1 detection ON/OFF setting System auto-detection ON/OFF setting 0: OFF 1: ON 0H Non-standard detection ON/OFF setting 0: OFF 1: ON 0H Input signal system designation 54H 1:0 I2A_HSELFORMAT 2 System designation (It takes effect at I2A_AUTODET = 1’b0) 00: 576i For test Normally set to 0H For test Normally set to 0H For test Normally set to 0H For test Normally set to 3H For test Normally set to 0H For test Normally set to 0H For test Normally set to 5H For test Normally set to 1H For test For test 1:0 2 Normally set to 0H For test Normally set to 2H 01: 480i 11: 480i (Non-standard) 0H 0H 0H 3H 0H 0H 5H 1H 0H 2H 10: 576i (Non-standard) 5 4 55H 3:2 1:0 6:4 56H 2:0 6:4 3 57H 2 1 3 3 1 For test For test For test 2 2 3 For test For test For test 1 1 For test For test 1H Continued on next page. No.A1957-17/45 LC749870W Continued from preceding page. Subaddress 58H 59H 5AH 5BH 5C Bit 7:0 5:0 7:0 5:0 7:0 6:4 5DH 2:0 5EH 7:0 7:6 5:4 5FH 3:2 1:0 7:6 5:4 60H 3:2 1:0 7:4 61H 3:0 62H to 6FH 70H 71H 72H 73H to 74H 75H 76H 77H 7 6:0 7:0 0 5:4 78H 1 0 HSYSFORMAT 1 2 1 1 For test System detection For test For test NLDOUT 1 S/N detection NLDET 15 S/N detection result Read only Noise level Read only Read only System detection result Read only Read only Read only 1:0 7:0 0 NOSIG 1 No signal detection No signal detection result Read only 4 2 2 4 For test 2 2 For test 2 2 3 8 2 2 Name BitSize 8 6 8 6 For test 8 3 Function Name For test Normally set to 0CH For test Normally set to 32H For test Normally set to F0H For test Normally set to 05H For test Normally set to 28H For test Normally set to 4H For test Normally set to 3H For test Normally set to 0AH For test Normally set to 3H For test Normally set to 3H For test Normally set to 3H For test Normally set to 3H For test Normally set to 3H For test Normally set to 3H For test Normally set to 3H For test Normally set to 3H For test Normally set to 0H For test Normally set to 0H Functions Initial value 0CH 32H F0H 05H 28H 4H 3H 0AH 3H 3H 3H 3H 3H 3H 3H 3H 0H 0H - 10 For test Read only - - Continued on next page. No.A1957-18/45 LC749870W Continued from preceding page. Subaddress Bit Name BitSize Function Name Functions Non-standard detection result (H) 3 DOUTH 1 When non-standard is detected in field-blanking period 0: Normal Read only Non-standard detection result (H) 2 79H 1 DOUTV 1 DOUTH2 1 Non-standard detection 0: Standard Read only Non-standard detection result (V) 0: Standard Read only Stability judgment result 0 7AH 7BH to 8AH 8BH 8CH 8DH 8EH 0 0 0 1 1 1 For test For test For test For test Normally set to 0H For test Normally set to 0H For test Normally set to 0H 0H 0H 0H 4:0 DOUTSTA 1 5 For test 0: Stable Read only Read only 1: Unstable 1: Non-standard 1: Non-standard 1: Special reproduction Initial value No.A1957-19/45 LC749870W BANK2 (Digital Video Signal Processing Block 2) Register Specification Subaddress Bit 7 Name I2BYC_ SOFTRESET I2BYC_ SEL_FORMAT BitSize 1 Function Name For test For test Normally set to 0H Soft reset 1 Soft reset Y/C separation is initialized on the rising edge of the register clock 3 Input switching setting For test For test Input switching setting For test For test Input switching (It takes effect at I2BYC_INSEL[0] = 0) 000: NTSC 110: PAL-N For test Normally set to 1H For test Normally set to 1H Input switching setting 0: I2BYC_SEL_PAL[7:6] For test Normally set to 16H For test Normally set to 16H For test Normally set to 3H For test For test 1 4 4 1 1 1 For test Normally set to 0H For test Normally set to 1H For test Normally set to 4H For test Normally set to 4H For test Normally set to 0H For test Normally set to 0H For test Normally set to 0H For test Normally set to 0H 1 2 1 I2BYC_2DCOMB2 3 2 1:0 7:5 3 06H 1 0 1 1 1 1 For test 2 3 1 For test For test Vertical high region line comb setting For test Dot interference reduction setting For test Normally set to 0H Line comb vertical high region element BSF coefficient select 00: BSF1 For test Normally set to 0H Dot interference reduction BSF 0: OFF For test Normally set to 1H For test Normally set to 2H For test Normally set to 2H For test Normally set to 0H For test Normally set to 0H For test Normally set to 0H 1: ON 01: BSF2 10: BSF3 11: BSF4 1: INSEL(input port) 010: PAL-M xx1: SECAM 1H 1H 1H 16H 16H 3H 0H 1H 4H 4H 0H 0H 0H 0H 0H 3H 0H 1H 1H 2H 2H 0H 0H 0H 100: PAL 0H 0H Functions Initial value 0H 6 00H 5:3 2 1 0 01H 02H 7:0 7:0 7:6 5 03H 4 3:0 7:4 3 04H 2 1 0 7 6:5 4 05H I2BYC_INSEL 1 1 1 8 2 2 1 Continued on next page. No.A1957-20/45 LC749870W Continued from preceding page. Subaddress Bit 7 6 5 4 07H 3 2 1 0 7 6 5 08H 4 3:2 1 0 7 09H 6 5 7 6 5 0AH 4 3:2 1 0 7:4 0BH 3:0 7:4 0CH 3:0 0DH 0EH 7:0 7:0 4 8 8 For test For test 4 4 For test I2BYC_2DCOMB8 I2BYC_2DCOMB4 1 For test 1 1 1 1 1 1 1 2 1 1 1 1 For test 1 1 1 1 1 For test 2 1 1 4 For test One dimensional filter setting For test For test For test For test For test For test Name BitSize 1 1 1 1 Cross color reduction ON/OFF For test Function Name For test Normally set to 1H For test Normally set to 1H For test Normally set to 1H Cross color reduction 0: OFF For test Normally set to 1H For test Normally set to 1H For test Normally set to 1H For test Normally set to 0H For test Normally set to 0H For test Normally set to 1H For test Normally set to 1H For test Normally set to 1H For test Normally set to 1H For test Normally set to 1H For test Normally set to 1H For test Normally set to 1H For test Normally set to 1H For test Normally set to 1H Adaptive two dimensional filter 0: Two dimensional For test Normally set to 1H For test Normally set to 1H For test Normally set to 1H For test Normally set to 3H For test Normally set to 1H For test Normally set to 1H For test Normally set to 4H For test Normally set to 4H For test Normally set to 7H For test Normally set to 8H For test Normally set to 0CH For test Normally set to 14H enable/disable setting 1: Adaptive two dimensional 1: ON Functions Initial value 1H 1H 1H 0H 1H 1H 1H 0H 0H 1H 1H 1H 1H 1H 1H 1H 1H 1H 1H 1H 1H 1H 3H 1H 1H 4H 4H 7H 8H 0CH 14H Continued on next page. No.A1957-21/45 LC749870W Continued from preceding page. Subaddress Bit Name BitSize 4 4 8 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 For test For test For test For test For test Function Name Functions Vertical enhancer gain setting 0FH 7:4 3:0 10H 7:0 7 6 5 11H 4 2 1 0 7 6 5 12H 4 2 1 0 7 5 4 13H 3 2 1 0 14H 0 I2BYC_2DVENH Vertical enhancer setting 000: OFF 001: 2/8 times to 0111: 8/8 times to 1111: 16/8 times Vertical enhancer coring setting For test Normally set to 4BH For test Normally set to 0H For test Normally set to 0H For test Normally set to 0H For test Normally set to 0H For test Normally set to 0H For test Normally set to 0H For test Normally set to 0H For test Normally set to 0H For test Normally set to 0H For test Normally set to 0H For test Normally set to 0H For test Normally set to 0H For test Normally set to 0H For test Normally set to 0H For test Normally set to 0H For test Normally set to 0H For test Normally set to 0H For test Normally set to 0H For test Normally set to 0H For test Normally set to 1H For test Normally set to 1H For test Normally set to 0H 0H 4BH 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 1H 1H 0H 0H Initial value Continued on next page. No.A1957-22/45 LC749870W Continued from preceding page. Subaddress Bit 7 6 5:4 15H 3 2 1 7:4 16H 3:1 0 17H to 1FH 20H 7:0 5 4 21H 3 2:0 22H to 25H 26H 27H 28H 7:0 7:0 4:3 29H 2:0 2AH 2BH 2CH 2DH to 2FH 3 30H 2 1:0 31H 32H 33H 7:0 3:0 1:0 I2BAC_ SW_ACC_NTPAL I2BAC_ACC_ON I2BAC_ ACC_BSTLV I2BAC_ ACC_TIMCON 1 1 2 8 ACC setting 4 2 For test For test ACC NTSC/PAL setting ACC ON For test Normally set to 0H 0: NTSC = 286LSB 1: PAL = 300LSB (when ACC_BSTLV is center value) ACC ON/OFF setting 00: OFF 01: ON 1x: Gain fix ACC target value setting 158 to 413LSB Maximum value of time constant, characteristics select Setting range: 1 time to 16 times For test Normally set to 0H 0H 0H 1H 80H 3H 0H 7:0 7:0 3 For test 8 8 For test I2BCD_UGAIN I2BCD_VGAIN 8 8 2 Cb gain setting Cr gain setting For test Gain control of Cb signal Gain control of Cr signal For test Normally set to 0H For test Normally set to 0H For test Normally set to 80H For test Normally set to 80H 80H 80H 0H 0H 80H 80H 1 3 For test For test 8 1 1 For test For test For test For test Normally set to 2CH For test Normally set to 0H For test Normally set to 1H For test Normally set to 1H For test Normally set to 0H 2CH 0H 1H 1H 0H I2BYC_1DFIL 1 For test 1 1 4 3 1 One dimensional BPF select BPF for SECAM select One dimensional filter ON Name BitSize 1 1 2 Function Name For test For test For test Normally set to 0H For test Normally set to 0H For test Normally set to 0H For test Normally set to 0H For test Normally set to 0H For test Normally set to 0H One dimensional BPF select 000: BPF0 to 1011: BPF11 One dimensional BPF select for SECAM 000: BPF0 to 111: BPF7 One dimensional filter ON/OFF setting 0: Line comb filter 1: One dimension filter Functions Initial value 0H 0H 0H 0H 0H 0H 4H 2H 0H Continued on next page. No.A1957-23/45 LC749870W Continued from preceding page. Subaddress Bit Name BitSize Function Name Functions Color killer ON/OFF setting 0000: OFF 0001: ON by APC 0010: ON by ACC 0011: ON by APC + ACC 34H 3:0 I2BAC_CKILL_ON 4 Color killer setting 0100: ON at the time of noncompliant signal input 0101: ON by APC and at the time of noncompliant signal input 0110: ON by ACC and at the time of noncompliant signal input 0111: ON by APC + ACC and at the time of noncompliant signal input 1xxx: Forced ON 35H 36H 37H 38H to 3AH 3BH 3CH 3DH 3EH 3FH 4:0 2:0 1:0 4:0 5 40H 4 3:0 7:4 41H 3:2 2 42H 1:0 43H 44H 5:0 7:0 3:2 45H 1:0 2 I2BSE_CLPFSEL 2 6 8 For test 2 I2BAC_ ACC_SELAMP I2BSE_BELLF0 I2BSE_BELLQ I2BSE_BELLAMP 5 For test 3 2 5 1 1 4 4 2 1 For test LPF setting after FM demodulation Bell filter setting For test ACC setting For test For test For test Normally set to 0H For test Normally set to 0H For test Normally set to 0H Gain setting at ACC_ON = 2’b1x Setting range: -6 to 32dB For test Normally set to 1H For test Normally set to 0H Bell filter f0 select Bell filter Q select Bell filter amplifier select 0: 1 time For test Normally set to 1H LPF select after FM demodulation For test Normally set to 28H For test Normally set to 40H For test Normally set to 3H For test Normally set to 3H 1: 2 times 0H 0H 0H 0H 1H 0H 8H 8H 1H 1H 2H 28H 40H 3H 3H 4:0 4:0 1:0 I2BAC_CKILL_LV I2BAC_ CKILL_HYST 5 5 2 For test Threshold value killer is turned on by burst-amplitude Threshold value killer is turned off by burst-amplitude For test Normally set to 1H 3H 0H 1H 7H Initial value Continued on next page. No.A1957-24/45 LC749870W Continued from preceding page. Subaddress Bit 6:4 3 46H 2:1 0 47H 48H 49H 4AH 4BH 4CH 4DH to 4FH 2 50H 1 0 51H 7:0 I2BSE_UGAIN 1 1 1 8 For test For test Normally set to 1H For test Normally set to 0H For test Normally set to 0H Cb/Cr gain control 0 to 3.984375 0=0 52H 7:0 I2BSE_VGAIN 8 SECAM chroma adjustment 53H 7:0 I2BSE_UOFFSET 8 64 = 1 128 = 2 255 = 3.984375 Cb/Cr offset adjustment -128 to 127 0 = -128 54H 7:0 I2BSE_VOFFSET 8 128 = 0 255 = 127 5 55H 4:3 2:0 56H to 5FH 60H 61H 7:0 7:0 8 8 For test For test For test Normally set to FH For test Normally set to 64H FH 64H I2BSE_DEIIR 1 2 3 For test De-emphasis filter setting For test For test Normally set to 0H De-emphasis filter select For test Normally set to 0H 0H 0H 0H 80H 80H 80H 1H 0H 0H 80H 5:0 3:0 6:0 6:0 5:0 5:0 2 1 6 4 7 7 6 6 For test For test For test Name BitSize 3 1 Function Name For test For test Normally set to 1H For test Normally set to 1H For test Normally set to 3H For test Normally set to 0H For test Normally set to 1H For test Normally set to 1H For test Normally set to 40H For test Normally set to 40H For test Normally set to 3H For test Normally set to AH Functions Initial value 1H 1H 3H 0H 1H 1H 40H 40H 3H AH Continued on next page. No.A1957-25/45 LC749870W Continued from preceding page. Subaddress Bit 7 6 62H 5 4 3 63H 7 6 64H 3 2 1:0 7:6 65H 2:0 66H 7:6 5 67H 4 3:1 0 68H to 69H 6AH 6BH to 70H 71H 72H 73H to 7BH 7CH 7DH to 7FH 80H 81H 82H to 9FH 0 0 1 For test 1 For test Normally set to 1H For test Normally set to 0H 1H 0H 1 0 I2BSR_SETUP 1 1 For test Setup For test Normally set to 0H Setup processing 0H 1H 5:0 5:0 I2BSR_GAIN I2BSR_OFST 6 6 Contrast adjustment Brightness adjustment 20H 20H 7:0 8 For test For test Normally set to 10H 10H 3 2 1 1 3 1 For test For test For test For test For test For test I2BCV_TVMODE 1 1 2 2 TV mode select Frequency select System setting For test Name BitSize 1 1 1 1 1 1 1 Function Name For test For test For test For test For test For test For test For test Normally set to 0H For test Normally set to 1H For test Normally set to 0H For test Normally set to 0H For test Normally set to 0H For test Normally set to 0H For test Normally set to 0H 0: Auto setting 1: Manual setting with TVMODE[2: 0] 0: 50Hz (625 lines) 0: NTSC For test Normally set to 0H For test Normally set to 1H For test Normally set to 0H For test Normally set to 0H For test Normally set to 0H For test Normally set to 0H For test Normally set to 0H 1: PAL-M 1: 60Hz (525 lines) 2: PAL 3: PAL-N Functions Initial value 0H 1H 0H 0H 0H 0H 0H 0H 0H 0H 0H 1H 0H 0H 0H 0H 0H Sub contrast/ brightness setting Continued on next page. No.A1957-26/45 LC749870W Continued from preceding page. Subaddress A0H A1H Bit 2:0 2:0 Name BitSize 3 For test 3 Function Name For test Normally set to 0H For test Normally set to 0H Functions Initial value 0H 0H No.A1957-27/45 LC749870W BANK3 (Digital Video Signal Processing Block 3) Register Specification Subaddress Bit 2 00H 1 0 01H 02H 03H 5:0 2:0 3:0 2 04H 1 0 05H 06H 07H 08H 09H 0AH 0BH to 0EH 0FH 1:0 3:1 10H 0 7:4 11H 3:0 7:4 12H 3:0 I2D65_ AUTOBBACK I2D65_SEPIA I2D65_601LIM I2D65_AVOFF 1 I2DCT_SMP I2DCT_CTIEN I2DCT_CORR I2DCT_GAIN 2 3 1 4 4 4 For test CTI setting For test For test Normally set to 1H CTI correction tap coefficient CTI ON/OFF setting 0: OFF 1: ON CTI Coring threshold CTI gain GAIN=C_GAIN/8 (0 ≤ C_GAIN ≤ 15) For test Normally set to 0H For test Normally set to 0H No signal output mode 2 1 1 1 1 For test 656 conversion setting 00: Black background 01: Blue background 10: OFF 0: Normal output 11: BL 1: Sepia output 0H 0H 1H 0H 0H 1H 0H 0H 0H 6H 0H 0H 0 7:0 7:0 6:0 7:0 7:0 Name I2DSH_LPFOFF I2DSH_ON I2DSH_ATT I2DSH_CORR I2DSH_FILTER I2DCB_CONT I2DCB_BRIGHT I2DHU_HUE I2DUV_UGAIN I2DUV_VGAIN BitSize 1 1 1 6 3 4 1 1 1 1 8 8 7 8 8 For test Contrast/ Brightness setting HUE setting U/V gain setting For test Function Name Sharpness setting For test Functions Sharpness LPF ON/OFF setting 0: ON For test Normally set to 0H Sharpness ON/OFF setting 0: OFF Sharpness setting 1: ON Sharpness ATT value setting Setting range: -47.5 to 12dB Sharpness coring threshold Sharpness characteristic select For test Normally set to 0H For test Normally set to 0H For test Normally set to 1H For test Normally set to 0H Contrast adjustment Brightness adjustment HUE adjustment Cb gain control Cr gain control 1: OFF Initial value 0H 0H 0H 10H 0H 1H 0H 0H 1H 0H 80H 80H 40H B4H B4H 5:4 3 13H 2 1 0 14H to 1FH 20H 21H 1:0 1:0 - 0: Signal level 1 to 254 1: Y level 16 to 235, C level 16 to 240 0: 656 with SAV,EAV 1: No SAV, EAV For test Normally set to 0H For test - - - - - 2 For test 2 Normally set to 0H For test Normally set to 0H 0H 0H No.A1957-28/45 LC749870W Function Descriptions 1. CPU I/F The LC749870W registers are controlled by I2C. 1) I2C The LC749870W supports high-speed mode slave operation (400 kHz) and the slave address is as follows. bit[7] (MSB) 1 0 0 0 1 0 I2CSEL bit[6] bit[5] bit[4] bit[3] bit[2] bit[1] bit[0] (LSB) R/W *Note: The bit 1 is decided according to the I2CSEL pin condition. bit 0 R/W: 0 = write, 1 = read ■Write Mode • Auto address increment. • As shown below, after the start condition, the settings must be made in the following order: slave address (W), ACK waiting, write start sub address, ACK waiting, write data. The stop condition must be set last. Data can be transmitted continuously from the write start sub address using the auto address increment function. [ST] [Slave Address(W)] [A] [Sub address] [A] [Data] [A] [Data] • • • [SP] ■Read Mode • Auto address increment. • The read start sub address must be assigned in write mode. • As shown below, after the start condition, first set the slave address (W), ACK waiting and read start sub address. Next, set the start condition again or set the start condition after setting the stop condition. Next set the slave address (R) and ACK waiting in read mode. The data for each sub address is output continuously from the read start sub address data using the auto address increment function. After receiving the data for each sub address, return the ACK. Finally, set the stop condition. [ST] [Slave Address (W)] [A] [Sub address] [ST] [Slave Address(R)] [A] [Data] [A] [Data] [A] [Data] • • • [SP] or [ST] [Slave Address (W)] [A] [Sub address] [SP] [ST] [Slave Address(R)] [A] [Data] [A] [Data] [A] [Data] • • • [SP] [ST]: Start condition [SP]: Stop condition [A]: ACK [A]: ACK waiting [Data]: Data transmission [Data]: Data reception No.A1957-29/45 LC749870W 2) BANK Each register is allocated to the BANK depending on its function (Refer to Table 1). After the BANK is specified, the register can be controlled. The BANK is specified by setting the BANK code to sub address FFH. Note that the register cannot be transmitted or received if codes other than the BANK codes in Table1 are specified. Table 1 Allocation of BANK BANK 0 1 BANK Code 01H 02H AFE + ADC Digital video signal processing block 1 (Data interpolator, APC, AGC, digital clamp, sync separator, timing generator, video system detection, S/N detection, non-standard signal detection, No-signal detection) 2 3 04H 08H Digital video signal processing block 2 (Y/C separator, color demodulator, clock rate converter) Digital video signal processing block 3 (Sharpness, contrast/brightness, CTI, HUE, UV gain) Controlled Function • Auto address increment. [ST] [Slave address (W)] [A] [FFH] [A] [BANK Code] [SP] [ST]: Start condition [SP]: Stop condition [A]: ACK [Data]: Data transmission No.A1957-30/45 LC749870W 2. AFE and ADC This IC (LC749870W) incorporates 1-channel of video AFE and 10-bit 30MHz ADC. • Analog clamp (Self-clamp circuit) The self clamp circuit clamps the sync-tip without supplying clamp pulses to AFE module. When the self-clamp function is not used, it can be placed in power down mode using I2C_SELFCLPPWDB. • Sync-tip clamp specifications Analog input 1.55V 1.35V 1.0Vp 0.85V (ADC-input reference) 0.65V 0.35V 0.15V 1.4Vp-p range * The figures represent the values under ideal conditions. Clamp Setting Self Clamp Setting SELFCLPPWDB Main Clamp Level Setting MAINCLPLVCNT [1:0] Digital output ADC output code 1023 878 512 356 147 1 1: Self Clamp enable 00: Main Clamp Level 0.35V • Low pass filter before self-clamp A primary LPF with a 1MHz cutoff frequency has been inserted in the stage before the self-clamp circuit as a measure to deal with the high-frequency noise that is present in weak electric fields. The LPF function is for minimizing shifts in the clamp levels of the self-clamp when high-frequency noise components are present in the video signals. The LPF can be set to ON or OFF using I2C_CLPLPFON. Input video signal (SD) High frequency noise of 1MHz or more Sync tip clamp when LPF is OFF Sync tip clamp when LPF is ON 0.35V 0V Clamping is performed at the lower limit level of the noise components. Due to the effect of the noise, the clamp level shifts. Clamping is performed at the level at which the noise components are removed. It is clamped at its original position. Fig.1 Self Clamp in Weak Electric Fields No.A1957-31/45 LC749870W • AGC Mode and Non-AGC Mode Switch between non-AGC mode and AGC mode using I2C_SCARTON. Non-AGC mode is used when the amplitude of the video signal is steady in the environment of a strong electric field. The maximum of the sync tip clamped analog video input amplitude assumes 1.0Vp-p in non-AGC mode. The ADC full-scale input range is fixed at 1.4Vp-p. AGC mode is used when the amplitude of the video signal is unsteady in the environment of a weak electric field. The maximum of the sync tip clamped analog video input amplitude assumes a value no greater than from 0.7Vp-p (-3dB) to 1.4Vp-p (+3dB) in AGC mode. Because the AFEVRTC is controlled according to the amplitude of SYNC detected by the decoder, AGC mode is enabled by varying the ADC full-scale input range. 3. Data Interpolator Data interpolator converts the input video signal sampled at 27MHz into 4fsc data. Supported video systems are shown in the following table. Table 2: Supported Video System Video System NTSC PAL-B, G, D, K, I PAL-M PAL-N NTSC4.43 PAL-60 SECAM Input Sampling clock 27MHz 27MHz 27MHz 27MHz 27MHz 27MHz 27MHz Data transfer rate 14.318180MHz 17.734476MHz 14.302444MHz 14.328224MHz 17.734476MHz 17.734476MHz 13.5MHz Output Clock lock method Burst Lock Burst Lock Burst Lock Burst Lock Burst Lock Burst Lock H Lock 4. APC (Auto Phase Control) In order to burst lock input video signals, the APC circuit detects the color burst phase error. The data interpolation coefficient is calculated using the detected phase error, and is then output to the data interpolator circuit. It is equipped with a function to turn on the color killer when not burst-locked, and also has an ACC circuit to maintain the amplitude of the carrier chrominance signal at a constant level. 5. AGC (Auto Gain Control) The AGC keeps the sync level constant by automatically calculating an appropriate gain value from the input video signal sync level and amplifying the input video signal. Because the AGC circuit includes a time constant circuit, following rapid changes in the input video signal can be suppressed. Pedestal Level Sync Level Before AGC After AGC Sync tip Level Fig.2 Waveform Change Before and After AGC No.A1957-32/45 LC749870W 6. Digital Clamp The digital clamp circuit detects the pedestal level of the input video signal, and keeps the level constant. Because the digital clamp includes a time constant circuit, following rapid changes in the input video signal can be suppressed. Input signal Target pedestal level 0LSB Before clamp After clamp Fig.3 Waveform Change Before and After Digital Clamp 7. Sync Separator The sync separator circuit separates horizontal and vertical sync signals out of the input video signals. Because an LPF is built in, the sync signal can be separated even in a weak electric field. The weak electric field is detected using the S/N detection result. Moreover, the stability of the sync signal in the weak electric field is improved by the internal AFC circuit. Fig. 4 shows the LPF characteristics for the sync separator. “FILSEL = 1’b0” is the characteristic of an LPF for a weak electric field, and “FILSEL = 1’b1” is the characteristic of an LPF for a strong electric field. Fig.4 LPF Characteristic for Sync Separator 8. Timing Generator Using the sync signal separated by the sync separator circuit, the timing generator generates various timing signals to be used for each module as well as for horizontal and vertical blanking signals. The adjustments of timing signals are possible by setting the corresponding register (s) as follows: Positioning of horizontal sync signal: I2A_HSPAD Positioning of vertical sync signal: I2A_VSTART Positioning of horizontal blanking signal: I2A_HBSTART, I2A_HBEND Positioning and width adjustment of vertical blanking signal: I2A_VBSTART, I2A_VBWIDTH No.A1957-33/45 LC749870W 9. Two-dimensional Y/C Separation The Y/C separator switches adaptive two-dimensional Y/C separation and one-dimensional Y/C separation according to the input video system. The table below shows the relationship between input video system and Y/C separation method. Table 3 Relationship Between Input Video System and Y/C Separation Method Video System NTSC NTSC-4.43 PAL-B, G, D, K, I, M, N PAL-60 SECAM Y/C Separation Filter Adaptive two-dimensional Y/C separation One-dimensional Y/C separation Adaptive two-dimensional Y/C separation One-dimensional Y/C separation One-dimensional Y/C separation 1) Adaptive Two-dimensional Y/C Separation The correlation between lines is detected in the vertical LPF and BPF, and the system switches between upper two line processing and lower two or three line processing, based on the results. The adaptive two-dimensional Y/C separation and two-dimensional Y/C separation can be switched using I2BYC_2DCOMB8 [7]. Note that the Y/C separation filter is switched to one-dimensional Y/C separation when I2BYC_1DFIL [0] is set to 1’b1 ( I2BYC_1DFIL [0] = 1’b1). • Y signal = (Vertical low frequency component) + (Horizontal low frequency component of vertical high frequency component) • C signal = Horizontal high frequency component of vertical high frequency component Vertical frequency Vertical frequency 525/4cph 525/4cph Pass range 3.58MHz Vertical LPF horizontalLPF Vertical BPF horizontalBPF Separation C Output horizontal frequency Pass range horizontal 3.58MHz frequency Composite signal Input Separation Y Output Vertical frequency 525/4cph Pass range Vertical frequency 525/4cph Pass range Vertical frequency 525/4cph Pass range horizontal 3.58MHz frequency horizontal 3.58MHz frequency 3.58MHz horizontal frequency Fig.5 Basic Block Diagram of Two-dimensional Y/C Separation (Line Comb Filter) • 1 Line Chroma Detector When 1 line chroma is separated with the two-dimensional Y/C separation, the dot interference is generated because there is no correlation between lines. Therefore, 1 line chroma is detected and dot interference reduction is attempted by subtracting chroma components. When the following conditions exist, it is judged to be 1 line chroma. (1) No chroma changes in the line (horizontal direction). (2) Chroma changes between lines (vertical direction). (3) Luminance changes between lines (vertical direction). No.A1957-34/45 LC749870W • 3 Line Median Processing When the vertical color in the DVD color bar changes and blurs, dot interference may be generated. Dot interference reduction is attempted by detecting this location and removing the chroma components. W Y Cy Gr Ma R B DVD SG Fig.6 Dot interference When the following conditions exist as a result of comparing the BPF values for each line, the chroma components must be removed. (1) When there is a match between the median value of each line and the pixel of the line at the center. (2) When there is a change between lines. • Y Signal Bypass Processing If the chroma band component of the separated Y signal is compared with the chroma band component of the signal before separation, and if the chroma band of the signal before separation is smaller, the signal is output as a Y signal. • C Signal Bypass Processing If a C signal processed by the comb filter is compared with the result processed by the BPF, and if the result of the BPF is smaller, the BPF processing result is output as a C signal. • Dot Interference Reduction The line comb filter need not add HLVH*1 to the Y signal if there is a complete line correlation, such as with the Color Bar. Such an addition will only increase the dot interference shown in Fig. 6 above. Therefore, when a location with strong line correlation is detected, the horizontal BSF pass band of HLVH to be added to the Y signal is narrowed, and the dot interference is reduced. The dot interference reduction BSF can be set to ON or OFF using I2BYC_2DCOMB2[3]. *1: Horizontal low frequency component of vertical high frequency component • Cross Color Reduction When a location with weak line correlation is detected, the BPF pass band in the subsequent stage of the C signal is narrowed, and the cross color is reduced. cross color reduction can be set to ON or OFF using I2BYC_2DCOMB4 [4]. No.A1957-35/45 LC749870W 2) One-dimensional Y/C separation (BPF) Y/C separation is performed by using BPF. The BPF characteristics for NTSC/PAL and for SECAM are selected by I2BYC_1DFIL [7:1]. It is forced to one-dimensional Y/C separation when I2BYC_1DFIL [0] is set to 1’b1 (I2BYC_1DFIL [0] = 1’b1). When performing adaptive two-dimensional Y/C separation, I2BYC_1DFIL [0] must be set to 1’b0 (I2BYC_1DFIL [0] = 1’b0) . Fig.7 and 8 show the characteristics of BPF. 10 0 -10 -20 -30 BPF0 BPF1 BPF2 BPF3 BPF4 BPF5 BPF6 BPF7 BPF8 BPF9 BPF10 BPF11 [dB] -40 -50 -60 0 1 2 3 4 Frequency[MHz] 5 6 7 Fig.7 BPF Characteristic for NTSC/PAL 10 0 -10 -20 [dB] BPF0 BPF1 BPF2 BPF3 BPF4 BPF5 BPF6 BPF7 -30 -40 -50 -60 0 1 2 3 Frequency[MHz] 4 5 6 Fig.8 BPF characteristic for SECAM No.A1957-36/45 LC749870W 10. Chrominance Signal Processing In chrominance signal processing, U/V axial demodulation is performed on the carrier chrominance signal after Y/C separation, and the UV signal is output. 1) ACC (Auto Color Control) ACC maintains a constant carrier chrominance signal amplitude for NTSC and PAL. The amplitude is kept constant by observing the color burst amplitude of the input carrier chrominance signal, and controlling the amplifier according to the amplitude level. It can also turn on the color killer when the color burst amplitude is small. I2BAC_ACC_ON switches between ACC ON and OFF. 2) Color Killer The color killer masks the carrier chrominance signal so that a monochrome image is output. When entering the detection results from APC or ACC circuits or an incompatible signal, the color killer is turned on and off. The color killer can be set using I2BAC_CKILL_ON. 3) NTSC/PAL Color Decoder The NTSC/PAL color decoder demodulates the carrier chrominance signal into color component signals (U/V). • Color Demodulator and Low Pass Filter The Cb/Cr signal is demodulated by multiplying the chrominance signal and phase-controlled color sub-carrier (4Fsc). Fig. 9 shows the block diagram. Chrominance signal 10 × LPF 10 Cb/Cr signal Color sub-carrier Fig.9 Color Demodulator The LPF characteristic after demodulation is shown in Fig.10. 10 0 0 1 2 3 4 5 6 7 -10 Magnitude[dB] -20 -30 -40 -50 -60 Frequency[MHz] Fig.10 LPF Characteristic after Demodulation No.A1957-37/45 LC749870W • UVGAIN (Cb/Cr Gain Control) The UVGAIN adjustment changes the Cb/Cr signal gain based on a center value. Fig.11 shows the block diagram. The gain can be controlled using I2BCD_UGAIN and I2BCD_VGAIN. U(V)GAIN 8bits CBIN (CRIN) 10 − × /128 + CBOUT (CROUT) center(512LSB) Fig.11 UVGAIN Block Diagram 4) SECAM Color Decoder The SECAM color decoder demodulates the carrier chrominance signal into color difference signals (U/V). • Bell Filter The bell filter is used to maintain the color sub-carrier amplitude of the Y/C-separated chrominance signal constant. The f0 parameter can be selected using I2BSE_BELLF0, and the Q parameter using I2BSE_BELLQ. bell filter characteristic 0 -2 I2_BELLQ=0 standard condition I2_BELLQ=15 -4 Gain[dB] -6 -8 -10 -12 -14 3.75 3.95 4.15 4.35 frequency[MHz] 4.55 4.75 Fig.12 Bell Filter characteristics No.A1957-38/45 LC749870W • Low Pass Filter The LPF is used to reduce noise in FM demodulated DB/DR signals. The characteristics of the LPF can be selected using I2BSE_CLPFSEL. LPF characteristic 10 0 -10 Gain[dB] -20 -30 LPF0 LPF1 LPF2 LPF3 -40 -50 -60 0 1 2 3 4 Frequency[MHz] 5 6 Fig.13 LPF Characteristics • UV Gain and Offset Adjustment The UV gain adjustment is performed to convert DB/DR to CB/CR, and the UV offset fine adjustment is also performed. The UV gain can be adjusted by changing I2BSE_UGAIN and I2BSE_VGAIN, and the UV offset can be adjusted by I2BSE_UOFFSET and I2BSE_VOFFSET. DB Gain DR Offset CB CR Fig.14 UV Gain and Offset Adjustment No.A1957-39/45 LC749870W • De-emphasis Filter The de-emphasis filter characteristics can be selected using I2BSE_DEIIR. de-emphasis filter characteristic 0 -5 def0 def1 def2 def3 -10 Gain[dB] -15 -20 -25 0.01 0.1 Frequency[MHz] 1 10 Fig.15 De-emphasis Filter Characteristics 11. Automatic Video Standard Recognition The video input standard is recognized automatically. Automatic video standard recognition can be set to ON or OFF using I2A_AUTODET. 12. S/N Detection S/N detection determines the video input noise level. During a vertical blanking period, the detection of noise is processed while the detection enable signal is high. The level of S/N detection can be controlled using I2A_NLTH. ODD line EVEN line Detection enable Signal 128CLK Fig.16 S/N Detection 13. Non-standard Detectionn This function determines whether the video input is non-standard. The video input is judged standard/non-standard by observing any variation from the standard VSYNC cycle. No.A1957-40/45 LC749870W 14. No Signal Detection This function detects no signal state. The result of no signal detection is output to the INTREQ pin. No signal detection function can be turned ON or OFF using I2A_NSDON [1]. Note that I2A_NSDON [0] is available when no signal detection is OFF. 15. Clock Rate Conversion The sampling rate converter converts an input video signal sampled at 4fsc into 13.5MHz, and outputs synchronized signals with video data. 16. Sharpness Sharpness of the image can be adjusted by detecting and forcibly correcting the edge of the luminance signal when the image is scanned horizontally. Adjustments to the enhancing frequency range and level of enhancement are possible. Sharpness can be turned ON or OFF using I2DSH_ON.The enhancing frequency range can be selected using I2DSH_FILTER, and the level of enhancement can be adjusted using I2DSH_ATT. 17. Contrast/Brightness Brightness adjusts the brightness of the entire screen and Contrast adjusts the brightness gain. 1) Contrast Contrast can be controlled using I2DCB_CONT. 00H: × 0 to 80H: × 1 to FFH: × 2 2) Brightness Brightness can be controlled using I2DCB_BRIGHT. 00H: -128 to 80H: ±0 to FFH: +127 18. CTI (Color Transient Improvement) The color transient can be improved by steepening the slope of the input signal. Processed video without overshoot or undershoot can provide more natural video images. The CTI can be switched between ON and OFF using I2DCT_CTIEN. The gain can be controlled using I2DCT_GAIN. The higher the I2DCT_GAIN is set, the more effective the CTI will be. CTI coring can be controlled using I2DCT_CORR. The higher the I2DCT_CORR is set, the less effective coring will be for extremely small amounts of noise. The CTI’s tap parameter can be selected using I2DCT_SMP. The higher the I2DCT_SMP is set, the more the CTI characteristics shift toward lower frequencies. 19. HUE The hue of the screen as a whole can be adjusted. (Refer to Fig.17.) The phase angle can be selected using I2DHU_HUE. 0H: -45° to 80H: 0° to FFH: 44° (with approx. 0.7° increments) Standard R minus plus minus B Standard plus Fig.17 HUE No.A1957-41/45 LC749870W 20. U/ V Gain The saturation (color density) is adjusted by varying the Cb and Cr gain. The Cb gain can be adjusted using I2DUV_UGAIN, and the Cr gain using I2DUV_VGAIN. 21. 8-bit output format conversion The 8-bit output format is converted to a format that is compatible with the ITU-R BT.656 format output. Blue back color can be output in non-signal mode using I2D65_AUTOBBACK. Sepia color can be output using I2D65_SEPIA. Clock 27MHz ♦Input Data Enable Y Cr Cb Y718 Cr359 Cb359 Y719 … … … Y0 Y0 Cr0 Cb0 Y1 Y2 Cr1 Cb1 Y3 ♦Output Data Enable ITU-R BT.656 Y715 Cb358 Y716 Cr358 Y717 Cb359 Y718 Cr359 Y719 EAV … SAV Cb0 Y0 Cr0 Y1 Fig.18 Timing Chart (ITU-R BT.656) * The processing is being performed by a 27MHz free-run clock, and so the number of pixels in one line cannot be guaranteed. The data in the period from SAV to EAV can be guaranteed, so read the data using the SAV standard. (Data cannot be read using the EAV standard.) * If equipment without an ITU-R BT.656 interface is connected, connect the HS and VS, or DE and read the data. Clock 27MHz ♦Input Data Enable Y Cr Cb Y718 Cr359 Cb359 Y719 … … … Y0 Cr0 Cb0 Y1 Y2 Cr1 Cb1 Y3 ♦Output Data Enable YCbCr 4:2:2 Y715 Cb358 Y716 Cr358 Y717 Cb359 Y718 Cr359 Y719 … Cb0 Y0 Cr0 Y1 HS tHWBP Figure 19 Timing Chart (YCbCr 4:2:2) * tHWBP shown in Figure 19 has the same value for each format. It can be adjusted by registers. No.A1957-42/45 LC749870W Application Example Digital 3.3V or1.8V 10kΩ 2 10kΩ I C Controller SDA Video IN 0.1μF AIN0 AIN1 AIN2 AIN3 SCL RESET PDWN DATA[7:0] CK0 CK13 HS 75Ω REFPKV 10μF 0.1μF VRB REFNKV 10μF AFEVRTC 0.1μF VRT VS DE FIELD LC749870W INTREQ MD0 MD1 MD2 XIN 12pF 27MHz 1MΩ XOUT 12pF 0Ω AVDD33 AVSS33 DVDD33 TEST DVSS 0.1μF DVDD11 DVSS Digital 1.1V (Digital core) Analog 3.3V (Analog core) 0.1μF Digital 3.3 or1.8V (IO) 0.1μF 10μF Analog GND Digital GND No.A1957-43/45 LC749870W Other (usage precautions) 1. Precaution when turning-on the power As shown in the figure below, start transfer of the I2C bus command after factoring in the power-on time (A), RST operation time (B) and command transfer start time (C). DVDD33 XVDD33 AVDD33 DVDD11 XVDD11 3.0V 1.0V 2V RESET 0.2VDD Command 0.75VDD A B C A: Power-on time This is the time taken from power-on to when the *VDD11 operating voltage has reached the lowest level (0.99V) and operation has stabilized. The power-on-time depends on the characteristics of the power ICs and other components, so it must be checked separately. With regard to *VDD33 and *VDD11, *VDD11 must be turned on after *VDD33 has turned on. B: RESET operation time This is the time during which the “L”level must be applied continuously for a period of 10ms or more to the RESET pin after the PDWN is released (“H” level). C: Command transfer start time At least an interval of 10ms is required from the time RESET pin is released (“H” level) to the start of command transfer. No.A1957-44/45 LC749870W 2. Precaution when turning-off the power DVDD33 XVDD33 AVDD33 3.0V DVDD11 XVDD11 0.99V A As a basic rule, power-off must be performed in the reverse sequence of power-on. However, no problems are posed if there is no wait time. A: Power-off time This is the time it takes to reach the IO supply voltage and for operation to stabilize from the lowest level (0.99V) of the *VDD11 operating supply voltage. With regard to *VDD33 and *VDD11, *VDD33 must be turned off after *VDD11 has been turned off or they must be turned off at the same time. SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein. SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO Semiconductor Co.,Ltd. products described or contained herein are controlled under any of applicable local export control laws and regulations, such products may require the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written consent of SANYO Semiconductor Co.,Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO Semiconductor Co.,Ltd. product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. Upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third party. SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's intellctual property rights which has resulted from the use of the technical information and products mentioned above. This catalog provides information as of June, 2011. Specifications and information herein are subject to change without notice. PS No.A1957-45/45