LC749880T

Ordering number : ENA1186 LC749880T Overview CMOS IC Silicon gate Image controller LSI for LCD-TV LC749880T is an LSI to display the converted NTSC/PAL analog video signals in the liquid crystal panel of maximum VGA size. This product performs A/D conversion, YC separation, color decoding, IP conversion, resolution conversion, and various enhancements according to the panel. When combined with a microcomputer and LCD panel, this product can readily makes up a video signal processing circuit for flat panel display Features (1) Analog input • 3ch A/D converter incorporated • CVBS, S-Video,YCbCr/YPbPr input (2) YC separation video decoder • Adaptive 3-line comb filter • AGC, ACC (3) Resolution conversion • Interlace - progressive conversion • Expansion/compression possible independently in horizontal and vertical directions (4) Enhancing functions • Adjusting the TV picture quality: Contour correction, color, hue, luminance, contrast • Adjusting the panel display picture quality: White balance, black balance,γ correction • Color exciter (6-phase RGBYMC independent saturation adjustment) • Shadow adjuster (emphaizing the three-dimensionality) • Dither (8bit/6bit) Continued on next page. Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment (home appliances, AV equipment, communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee thereof. If you should intend to use our products for applications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our customer shall be solely responsible for the use. Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer' s products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer' s products or equipment. 51408HKIM 20080319-S00007 No.A1186-1/17 LC749880T Continued from preceding page. (5) Panel interface • Video signal of either RGB 24-bit (single phase) or 18-bit signal output • Timing controller output for panel driver (6) Others • OSD I/F: R, G, B, EN • Clock generator (PLL) incorporated • I2C bus interface incorporated LSI Specifications • Supply voltage Core: 1.8V, I/O block: 3.3V • Maximum operating frequency: 27MHz • Package: TQFP120 Principal Applications • LCD TV Analog Input CVBS×2ch: Composite video input 2channels S-Video: S video input 1channel YCbCr/YPbPr (480i/576i input compatible): Component input 1channel YC Separation Video Decoder A video decoder that converts either the NTSC/PAL video signal or component video signal into the digital video signal is incorporated, which is compatible with the composite video signal, S video signal, and component video signal (480i). Resolution Conversion Two-dimensional IP conversion, and expansion/contraction processings available 1. Interlace progressive conversion (IP conversion) Two-dimensional IP conversion possible for NTSC/PAL input 2. Horizontal vertical scaler functions Expansion/contraction to VGA size possible. Expansion/contraction possible independently in horizontal and vertical directions. Full-screen display and zoom display possible. Enhancement Functions Various enhancement functions are available. Picture quality adjustment can be made appropriate to characteristics of LCD-TV. 1. Adjusting the TV picture quality 1-1. Contour correction (horizontal vertical) Contour correction of the input luminance signal. Adquate peaks are added around the contour. In this case, coring adjustment is possible to prevent emphasizing of the peak amount and extremely small noises. 1-2. Color Saturation can be adjusted by adjusting the color gain of input color-difference signal. 1-3. Hue The hue of the screen as a whole can be adjusted. 1-4. Luminance Luminance of the screen as a whole can be adjusted. 1-5. Contrast Brightness of the screen as a whole can be adjusted. No.A1186-2/17 LC749880T 2. Adjusting the panel picture quality 2-1. White balance White balance adjustment appropriate to LCD-TV is possible. 2-2. Black balance Black balance adjustment appropriate to LCD-TV is possible. 2-3. γ correction γ correction appropriate to LCD-TV is possible. The γ correction curve may be made programmable by means of LUT γ correction can be made independently by RGB. 3. Color exciter A total of 12 colors including red, green, blue, magenta, yellow, cyan, and colors between these colors can be adjusted independently in terms of saturation. 4. Shadow adjuster The three-dimensionality can be emphasized by adding the shading through addition of the adequate peaks before and after the detected input signal contour. 5. Dither In the case of 6-bit output, pseudo-mulltiple tone processing enables the output equivalent to the 8-bit output. Panel Interface 1. Video output Digital RGB 24-bit/18-bit output possible 2. Synchronizing signal (timing controller) output Timing controller output and synchronizing signal output (horizontal/vertical synchronizing signal, data enable) possible. The output can be selected according to specifications of LCD module. Others 1. OSD interface This LSI has no OSD. OSD can be interfaced with the external OSD microcomputer by means of the input pin (Pin Nos.: 105 to 108) and output pin (Pin Nos.: 96,103,104). Interlace synchronization/progressive synchronization can be changed over according to register setting. The closed caption can be displayed. 2. I2C bus interface The internal register is controlled by means of I2C. The slave address can be changed over by controlling the “I2CSEL” pin (Pin No: 33) according to the system. “L” Slave address “88H” I2CSEL I2CSEL “H” Slave address “8AH” I/O Specifications 1. Input Signals Signal type Video signal No. of pins 1 1 1 1 1 1 1 Synchronizing signal 1 1 1 1 1 1 Pin symbol CVBS1 CVBS2 CRIN CBIN YIN SY SC VSI HSI BLKIN RIN GIN BIN Vertical synchronization Horizontal synchronization OSD I/F Description Analog I/F Remarks Composite video signal input 1 Composite video signal input 2 Component video signal input Cr Component video signal input Cb Component video signal input Y S-Video signal input Y S-Video signal input C Vertical synchronizing signal input pin (From Sync. Sep) Horizontal synchronizing signal input pin (From Sync. Sep.) OSD signal OSD signal input enable (From μ-CON) OSD signal R input pin (From μ-CON) OSD signal G input pin (From μ-CON) OSD signal B input pin (From μ-CON) Continued on next page No.A1186-3/17 LC749880T Continued from preceding page. Signal type Clock No. of pins 1 (1) System reset I/F mode selection 1 3 Pin symbol XIN (DCLKO3) RESET MODE Clock Clock (GPIO pin) System reset I/F mode selection System reset input pin (Lo-Active) I/F mode selection signal input pin 0: Two-phase 6-bit output (TCON signal output) 1: Single-phase 8-bit/6-bit output (RGB, TCON signal output) DCLKO3; 3.375MHz output 2: Single-phase 8-bit/6-bit output (RGB, TCON signal output) DCLKO3; Clock input 3,4: Decoder output (RGB/YCbCr/YC (register setting), synchronizing signal output) 5: Single-phase 8-bit/6-bit output (RGB, synchronizing signal output) * Others not applicable because they are not defined. Description Remarks Crystal oscillator input pin (27MHz) Clock input when MODE≠0, 1 2. Output Signals Signal type Video signal No. of pins (36) Pin symbol (VP) Description Digital I/F (GPIO pin) Remarks Video signal output pin. MODE pin. Pin function changed through register setting. 6-bit output for output after dither processing For single-phase 8-bit output(MODE≠0) VP00 to VP07: R0 to R7(Cb0 to Cb7) VP08 to VP15: B0 to B7(Cb0 to Cr7/CbCr0 to CbCr7) VP16 to VP23: G0 to G7(Y0 to Y7) * ( ) shows the YCbCr VP00 to VP05: R0 to R5 VP08 to VP13: B0 to B5 VP16 to VP21: G0 to G5 For two-phase 6-bit output (MODE=0) VP00 to VP05: RO0 to RO5 VP06 to VP11: BO0 to BO5 VP12 to VP17: GO0 to GO5 VP18 to VP23: RE0 to RE5 VP24 to VP29: BE0 to BE5 VP30 to VP35: GE0 to GE5 4:4:4/4:2:2 output (MODE=3,4) For single-phase 6-bit output (MODE≠0) * xO: Odd-numbered picture elements xE: Even-numbered picture elements 1 Synchronizing signal (1) Data enable signal (1) (TIM2) (TIM0) (1) SVO (TIM1) Analog I/F Vertical synchronizing (GPIO pin) Horizontal synchronization (GPIO pin) Data enable (GPIO pin) Internal analog video signal output Applicable when MODE=3, 4, and 5. Synchronizing period, Polarity reversal possible Applicable when MODE≠0. Synchronizing period. Polarity reversal possible Applicable when MODE=3, 4, and 5. H,V composite data enable output. Position, polarity reversal possible Continued on next page No.A1186-4/17 LC749880T Continued from preceding page. Signal type TCON signal No. of pins (1) Pin symbol (GRST) Description TCON signal (GPIO pin) Remarks When MODE=0, the gate reset signal output/clamp pulse output/PWM3 output selectable through register selection When MODE≠0, the gate reset signal output/clamp pulse output selectable through register selection GRST: Pulse width, position, and polarity reversal possible 1 FLM When MODE=0, 1, and 2, gate start pulse signal output Pulse width, position, polarity reversal possible. Hi-Z when FLM2 is used 1 1 1 1 OE CPV STRB SP When MODE=0, 1, and 2, gate output enable signal output. Pulse width, position, polarity reversal possible. When MODE=0, 1, and 2, gate clock signal output. Pulse width, position, polarity reversal possible. When MODE=0, 1, and 2, source strobe signal output. Pulse width, position, polarity reversal possible. When MODE=0, 1, and 2, source start pulse signal output. Pulse width, position, polarity reversal possible. Hi-Z when SP2 is used 1 DEXR When MODE=0, 1, and 2, source picture element reversal signal output. When MODE=0, DEXR output of odd-numbered picture elements 1 POL When MODE=0, 1, and 2, source voltage polarity selection signal output. Position adjustment, 1 line/2 line reversal and 1 frame/2 frame reversal possible (1) (TIM0) When MODE=0, 1, and 2, FLM2 output through register setting Pulse width, position, polarity reversal possible. Hi-Z when FLM is used (1) (TIM1) When MODE=0,1, and 2, SP2 output through register setting Pulse width, position, polarity reversal possible. Hi-Z when SP2 is used (1) Clock 1 1 1 For OSD signal 1 1 1 PWM output (1) (1) (TIM2) DCLKO (DCLKO3) XOUT VSO HSO DCLKO2 (VP32) (VP35) PWM signal (GPIO pin) OSD I/F Dot clock Clock When MODE=0, DEXR (DEXR_E) output of even-numbered picture elements Picture element clock output. Polarity reversal, 1/2 output possible When MODE=0 and 1, clock output (3.357MHz) Crystal oscillator output pin Vertical synchronizing signal output for OSD (To μ-CON) Pulse width, position, polarity reversal possible. Horizontal synchronizing signal output for OSD (To μ-CON) Pulse width, position, polarity reversal possible. Picture-element clock output for OSD (To μ-CON) Polarity reversal, 1/2 output possible When MODE≠0, PWM1 output through register setting. Pulse width, position, polarity reversal possible. When MODE≠0, PWM2 output/PWM3 output/clamp pulse output selectable through register setting. PWM2, 3: Pulse width, position, polarity reversal possible. (1) (GRST) When MODE=0, PWM3 output/GRST output/clamp pulse output selectable through register setting PWM3: Pulse width, position, polarity reversal possible. Clamp pulse (1) (VP35) Clamp pulse (GPIO pin) (1) (GRST) When MODE≠0, clamp pulse output/PWM2 output/PWM3 output selectable through register setting Clamp pulse: Pulse width and position adjustment possible. When MODE=0, clamp pulse output/GRST output/PWM3 output selectable through register setting. When MODE≠0, clamp pulse output/GRST output selectable through register setting Clamp pulse: Pulse width and position adjustment possible. * The signals in parentheses show that one pin has multiple functions or acts as the I/O pin. Selection can be made with the MODE pin or through register setting. No.A1186-5/17 LC749880T 3. Control Signal Signal type I C bus 2 No. of pins 1 1 1 Pin symbol I CSEL SDA SCL 2 Description Slave changeover Data bus Bus clock 2 Remarks I C BUS bus slave address setting (normally “L”) “L”: 88H, “H”: 8AH Slave address for internal register setting and internal status output: ”1000100+(R/W)” 4. Other Signals Signal type SCAN test No. of pins 1 1 Test ADC/AFE 1 3 3 1 1 AGC 1 1 1 PLL 1 1 Pin symbol SCANEN SCANMOD TEST VRT VRB NBIAS VREF VRTC LPFO LPFVDD CHAGPUP VCOR PLL AGC Test ADC/AFE Description SCAN test Test pin (Normally, ”L”) Test pin (Normally, ”L”) Test pin (Normally, ”L”) ADC top level reference output ADC bottom level reference output ADC bias voltage output ADC reference output AGC control voltage input AGC PWM output AGC PWM output buffer power supply Charge pump output for built-in PLL Range resistor for built-in PLL Remarks Package Dimensions unit : mm (typ) 3257A 16.0 14.0 120 1 0.4 (1.2) 1.2MAX (1.0) 0.15 14.0 16.0 0.125 0.1 SANYO : TQFP120(14X14) 0.5 No.A1186-6/17 LC749880T Pin Assignment 90 VP32(GE2/EXCTR1 or PWM1) VP35(GE5/PWM2 or PWM3) 61 VP33(GE3/EXCTR2) VP17(GO5/G1) VP16(GO4/G0) VP15(GO3/B7) VP14(GO2/B6) VP13(GO1/B5) VP12(GO0/B4) VP23(RE5/G7) VP22(RE4/G6) VP21(RE3/G5) VP20(RE2/G4) VP19(RE1/G3) VP18(RE0/G2) VP34(GE4/-) VP31(GE1/-) VP30(GE0/-) VP29(BE5/-) VP28(BE4/-) VP27(BE3/-) VP26(BE2/-) VP25(BE1/-) VP24(BE0/-) DVDD18 DVDD33 DVDD18 DVSS DVDD33 60 55 50 45 40 35 30 60 VP11(BO5/B3) VP10(BO4/B2) VP09(BO3/B1) VP08(BO2/B0) VP07(BO1/R7) VP06(BO0/R6) VP05(RO5/R5) VP04(RO4/R4) VP03(RO3/R3) VP02(RO2/R2) VP01(RO1/R1) VP00(RO0/R0) TIM2(DEXR_E/Hsync) TIM1(FLM2/Vsync) TIM0(SP2/DE) POL(*1) DEXR(*1) DVDD18 DVSS DVDD33 SP(*1) STRB(*1) CPV(*1) OE(*1) FLM(*1) GRST RESET 2 I CSEL SCANMOD SCANEN 31 Top view 91 AVSS18 CHAGPUP VCOR AVDD18 DCLKO3 DCLKO2 DVDD18 DVDD33 XIN XOUT DVSS DCLKO VSI HSI RIN GIN BIN BLKIN HSO VSO PDWN SCL SDA TEST MODE0 MODE1 MODE2 DVDD33 DVSS DVDD18 120 90 DVSS 85 80 75 70 65 95 100 105 LC749880T 110 115 120 5 10 15 20 25 *1: NC for the mode in which built-in TCON is not to be used. CRIN VRT1 VRB1 AVSS33 CBIN AVSS33 SC AVDD33 VRT2 VRB2 NBIAS VREF1 AVSS18 SVO AVDD18 YIN AVSS33 SY AVSS33 CVBS1 AVSS33 CVBS2 AVSS33 VRT3 VRB3 VRTC RVSS33 RVDD33 LPFO LPFVDD No.A1186-7/17 LC749880T Pin Functions Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 Pin symbol CRIN VRT1 VRB1 AVSS33 CBIN AVSS33 SC AVDD33 VRT2 VRB2 NBIAS VREF1 AVSS18 SVO AVDD18 YIN AVSS33 SY AVSS33 CVBS1 AVSS33 CVBS2 AVSS33 VRT3 VRB3 VRTC RVSS33 RVDD33 LPFO LPFVDD SCANEN SCANMOD I2CSEL RESET GRST FLM OE CPV STRB SP DVDD33 DVSS DVDD18 DEXR POL TIM0 TIM1 TIM2 VP00 VP01 VP02 I O O P I P I P O O O O P O P I P I P I P I P O O I P P O I I I I I I/O I/O I/O I/O I/O I/O P P P I/O I/O O O O O O O G G E E E E E E A A C C C B G G G G G G Digital 3.3V Digital GND Digital 1.8V Source picture element reversal signal (or test input) Source line reversal signal (or test input) Data enable signal output/FLM2 (register selection) Vertical synchronizing signal output/SP2 (register selection) Horizontal synchronizing signal output Video signal output R0/R_ODD_0 (MODE pin select=0) Video signal output R1/R_ODD_1 (MODE pin select=0) Video signal output R2/R_ODD_2 (MODE pin select=0) A A A Analog GND Analog 3.3V A A A A A Analog 1.8V Analog IF Analog GND Analog IF Analog GND Analog IF Analog GND Analog IF Analog GND Top level reference voltage connection pin for ADC3 Bottom level reference voltage connection pin for ADC3 AGC control voltage input VREF generator circuit analog GND VREF generator circuit analog 3.3V AGC PWM output AGC PWM output buffer power supply Test pin (Normally, Lo) Test pin (Normally, Lo) I2C slave addresses L=0×88, H=0×8A System reset (Active Lo) Gate reset signal (or test input) Gate start signal (or test input) Gate OE signal (or test input) Gate lock signal (or test input) Source strobe signal (or test input) Source start signal (or test input) Analog CVBS2 input (ADC3) Analog CVBS1 input (ADC3) Analog S-Y input (or CVBS) (ADC3) Analog Y input (or S-Y,CVBS) (ADC3) A A A A Analog GND ADC3 input internal analog video signal output A A I/O format I/O Format A A A Analog GND Analog IF Analog GND Analog IF Analog 3.3V Top level reference voltage connection pin for ADC2 Bottom level reference voltage connection pin for ADC2 Bias voltage connection pin for ADC Reference voltage connection pin for ADC Analog S-C input (ADC2) Analog CB input (or S-C) (ADC2) Analog IF Analog CR input (ADC1) Top level reference voltage connection pin for ADC1 Bottom level reference voltage connection pin for ADC1 Connected to Remarks Continued on next page. No.A1186-8/17 LC749880T Continued from preceding page. Pin No. 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 Pin symbol VP03 VP04 VP05 VP06 VP07 VP08 VP09 VP10 VP11 DVDD33 DVSS DVDD18 VP12 VP13 VP14 VP15 VP16 VP17 VP18 VP19 VP20 VP21 VP22 VP23 VP24 VP25 VP26 VP27 VP28 DVDD33 DVSS DVDD18 VP29 VP30 VP31 VP32 VP33 VP34 VP35 AVSS18 CHAGPUP VCOR AVDD18 DCLKO3 DCLKO2 DVDD18 DVDD33 XIN XOUT DVSS DCLKO VSI HSI I/O format I/O O O O O O O O O O P P P O O O O O O O O O O O O I/O I/O I/O I/O I/O P P P I/O I/O I/O I/O I/O I/O I/O P O I P I/O O P P I O P O I I F B B Digital GND Panel clock output Vertical synchronizing signal input Horizontal synchronizing signal input D H F Digital 1.8V Digital 3.3V Crystal oscillator connection pin (27MHz) Crystal oscillator connection pin A A Analog 1.8V Clock I/O Clock output (dedicated to microcomputer, with 1/2 or DE) G G G G G G G Analog GND Charge pump output Range resistor for PLL E E E E E E E E E E E E G G G G G Digital 3.3V Digital GND Digital 1.8V -/Video signal output B_EVEN_5 (MODE pin select=0) -/Video signal output G_EVEN_0 (MODE pin select=0) -/Video signal output G_EVEN_1 (MODE pin select=0) -/Video signal output G_EVEN_2 (MODE pin select=0) -/Video signal output G_EVEN_3 (MODE pin select=0) PWM signal/Video signal output G_EVEN_4 (MODE pin select=0) PWM signal/Video signal output G_EVEN_5 (MODE pin select=0) Format E E E E E E E E E Digital 3.3V Digital GND Digital 1.8V Video signal output B4/G_ODD_0 (MODE pin select=0) Video signal output B5/G_ODD_1 (MODE pin select=0) Video signal output B6/G_ODD_2 (MODE pin select=0) Video signal output B7/G_ODD_3 (MODE pin select=0) Video signal output G0/G_ODD_4 (MODE pin select=0) Video signal output G1/G_ODD_5 (MODE pin select=0) Video signal output G2/R_EVEN_0 (MODE pin select=0) Video signal output G3/R_EVEN_1 (MODE pin select=0) Video signal output G4/R_EVEN_2 (MODE pin select=0) Video signal output G5/R_EVEN_3 (MODE pin select=0) Video signal output G6/R_EVEN_4 (MODE pin select=0) Video signal output G7/R_EVEN_5 (MODE pin select=0) -/Video signal output B_EVEN_0 (MODE pin select=0) -/Video signal output B_EVEN_1 (MODE pin select=0) -/Video signal output B_EVEN_2 (MODE pin select=0) -/Video signal output B_EVEN_3 (MODE pin select=0) -/Video signal output B_EVEN_4 (MODE pin select=0) Video signal output R3/R_ODD_3 MODE pin select=0) Video signal output R4/R_ODD_4 (MODE pin select=0) Video signal output R5/R_ODD_5 (MODE pin select=0) Video signal output R6/B_ODD_0 (MODE pin select=0) Video signal output R7/B_ODD_1 (MODE pin select=0) Video signal output B0/B_ODD_2 (MODE pin select=0) Video signal output B1/B_ODD_3 (MODE pin select=0) Video signal output B2/B_ODD_4 (MODE pin select=0) Video signal output B3/B_ODD_5 (MODE pin select =0) Connected to Remarks Continued on next page. No.A1186-9/17 LC749880T Continued from preceding page. Pin No. 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 Pin symbol RIN GIN BIN BLKIN HSO VSO PDWN SCL SDA TEST MODE0 MODE1 MODE2 DVDD33 DVSS DVDD18 I I I I O O I I I/O I I I I P P P I/O format I/O Format C C C C E E B B G C C C C Digital 3.3V Digital GND Digital 1.8V R input of microcomputer OSD G input of microcomputer OSD B input of microcomputer OSD BLK input of microcomputer OSD Horizontal synchronizing signal output for microcomputer Vertical synchronizing signal output for microcomputer Power DOWN (Active Lo) I2C bus clock I2C bus data Test pin (normally, Lo) I/F mode pin I/F mode pin I/F mode pin Connected to Remarks No.A1186-10/17 LC749880T Pin Type I/O type A Function Analog I/O Equivalent circuit Applicable pins CRIN, VRT1, VRB1, CBIN, SC, VRT2, VRB2, NBIAS, VREF1, SVO, YIN, SY, CVBS1, CVBS2, VRT3, VRB3, VRTC, LPFO, LPFVDD, CHAGPUP, VCOR B 5V withstand Schmidt trigger CMOS input* RESET, VSI, HSI, PDWN, SCL C 5V withstand With Pull-down CMOS input* SCANEN, SCANMOD, I2CSEL, RIN, GIN, BIN, BLKIN, TEST, MODE0, MODE1, MODE2 D Oscillator circuit I/O XIN, XOUT E 8mA 3-STATE drive CMOS output* TIM0, TIM1, TIM2, VP00, VP01, VP02, VP03, VP04, VP05, VP06, VP07, VP08, VP09, VP10, VP11, VP12, VP13, VP14, VP15, VP16, VP17, VP18, VP19, VP20, VP21, VP22, VP23, HSO, VSO F 12mA 3-STATE drive CMOS output* DCLKO2, DCLKO G 8mA 3-STATE drive CMOS I/O* GRST, FLM, OE, CPV, STRB, SP, DEXR, POL, VP24, VP25, VP26, VP27, VP28, VP29, VP30, VP31, VP32, VP33, VP34, VP35, SDA H 12mA 3-STATE drive CMOS I/O* DCLKO3 *: 5V Tolerant No.A1186-11/17 LC749880T Electrical Characteristics Absolute Maximum Ratings at Ta = 25°C, DVSS = 0V, AVSS = 0V Parameter Maximum supply voltage (I/O) Maximum supply voltage (core) Digital input voltage Digital output voltage Storage temperature Operating temperature Maximum allowable loss Symbol DVDD33 AVDD33 DVDD18 AVDD18 VI VO Tstg Topr Pd max Rating -0.3 to +4.0 -0.3 to +2.2 -0.5 to 6.0 -0.3 to VDD + 0.3 -55 to +125 -30 to +70 0.6 Unit V V V V °C °C W Allowable Operation Range at Ta = -30 to +70°C Parameter Supply voltage (I/O) Supply voltage (core) Input voltage range Symbol DVDD33 AVDD33 DVDD18 AVDD18 VIN min 3.15 1.71 0 typ 3.3 1.8 max 3.45 1.89 5.5 Unit V V V I/O Pin Capacity at Ta = 25°C, VDD = VI = 0V Parameter Input pin Output pin I/O pin CIN COUT CI/O Symbol Conditions f=1MHz f=1MHz f=1MHz min typ max 10 10 10 Unit pF pF pF DC Characteristics at Ta = -30 to +70°C, DVDD33 = 3.3V±5%, DVDD18 = 1.8V±5% Parameter Input high-level voltage Symbol VIH Conditions CMOS compatible CMOS compatible schmidt Oscillator circuit input Input low-level voltage VIL CMOS compatible CMOS compatible schmidt Oscillator circuit input Input high-level current IIH VI=VDD VI=VDD with pull-down resistor Input low-level current Output high-level voltage IIL VOH VI=VSS CMOS Oscillator circuit output Output low-level voltage VOL CMOS Oscillator circuit output Output leak current Pull-down resistor Operating current Operating current (AVDD33) Operating current (AVDD18) Operating current (DVDD33) Operating current (DVDD18) Current drain at rest *1 IDDST IOZ RDN IDDOP IDDOP tck=27MHz tck=27MHz gray scale tck=27MHz gray scale tck=27MHz gray scale tck=27MHz gray scale Output release,VI=VSS or VDD 15 70 20 90 10 At output of high-impedance -10 43 58 min 2.0 2.0 2.0 -0.3 -0.3 -0.3 -10 +10 -10 2.4 2.4 0.4 0.4 +10 118 typ max 5.5 5.5 3.465 +0.8 +0.8 +0.8 +10 +100 +10 Unit V V V V V V μA μA μA V V V V μA kΩ mA mA mA mA mA μA *1: There is an input pin incorporating pull-down resistor. Note that, depending on circuit composition, the current drain at rest may not be guaranteed. No.A1186-12/17 LC749880T A/D Convertor Characteristics at Ta = -30 to +70°C, DVSS = 0V, AVSS = 0V Parameter Clock frequency Clamp pulse width External capacitance Analog input coupling capacitance Top level reference fixed capacitance Bottom level reference capacitance VREF1 bias fixed capacitance NBIAS bias fixed capacitance Analog input frequency Analog input amplitude (Max amplitude) In the non-AGC operation mode In the AGC operation mode *1 ADC reference input voltage In the non-AGC operation mode Bottom level reference input In the AGC operation mode Bottom level reference input VRBI 0.65 V VRBI 0.65 V FS1AIN FS2AIN 0.6 1.0 1.1 Vp-p Vp-p Analog video pin VRTx pin VRBx pin VREF1 pin NBIAS pin FAIN 0.01 0.01 0.01 0.01 0.01 4 10 μF μF μF μF μF MHz Symbol/pin Fclk Tcl 0.45 min typ max 27 Unit MHz μs DC Characteristics at Ta=25°C, VDD3=3.3V±5%,VDD=1.8V±5%, DVSS = 0V, AVSS = 0V Parameter Operating supply current 3.3V power supply 1.8V power supply Standby supply current 3.3V power supply 1.8V power supply ISB VDD=1.8V Fclk=0MHz IDD ISB3 VDD=1.8V Fclk=27MHz VDD3=3.3V -10 -10 Symbol IDD3 VDD3=3.3V Conditions min typ 16 16 +10 +10 max Unit mA mA μA μA ADC Conversion Characteristics at Ta=25°C,VDD3=3.3V±5%,VDD=1.8V±5%, DVSS = 0V, AVSS = 0V Parameter Resolution Symbol RES Conditions min typ max 10 Unit bits I/O Data Timing (1) Input data timing 1 tHI XIN tSU tHD Input data tLO VDD33/2 tCK VDD33/2 Pin name XIN Parameter Clock L-level time Clock H-level time Clock cycle Symbol tLO tHI tCK tSU tHD min 18.5 18.5 37 3.5 3.5 max Unit ns ns ns ns ns VP24-34 POL, FLM, OE, CPV, STRB SP, DEXR RIN, GIN, BIN, BLKIN Input data setup time Input data hold time * The recommended duty ratio of input clock is 50% No.A1186-13/17 LC749880T (2) Input data timing 2 tHI DCLKO3 SDCLK tCK VDD33/2 tSU tHD tLO VDD33/2 Input data Pin name DCLKO3 Parameter Clock L-level time Clock H-level time Clock cycle Symbol tLO tHI tCK tSU tHD min 18.5 18.5 37 3.5 3.5 max Unit ns ns ns ns ns VSI HSI Input data setup time Input data hold time (3) Output data timing (1) tHI DCLKO tAC tHD Output data tLO tCK VDD33/2 VDD33/2 Pin name DCLKO Parameter Clock L-level time Clock H-level time Clock cycle Symbol tLO tHI tCK tAC tHD min 18.5 18.5 37 -3.5 30.0 max Unit ns ns ns +3.5 ns ns VP00-31 TIM0, TIM1, TIM2 POL, FLM, OE, CPV, STRB SP, DEXR, GRST Output data delay time Output data hold time (3) Output data timing (2) tHI DCLKO2 tAC tHD tLO VDD33/2 tCK VDD33/2 Output data Pin name DCLKO2 Parameter Clock L-level time Clock H-level time Clock cycle Symbol tLO tHI tCK tAC tHD min 18.5 18.5 37 -3.5 30.0 max Unit ns ns ns +3.5 ns ns VSO,HSO Output data delay time Output data hold time No.A1186-14/17 LC749880T I/O Clock Timing (1) Input system clock timing tHI Input XIN tOUT1 Output DCLKO tOUT2 Output DCLKO2 tOUT3 Output DCLKO3 VDD33/2 VDD33/2 tLO VDD33/2 tCK VDD33/2 Pin name XIN Parameter Clock L-level time Clock H-level time Clock cycle Symbol tLO tHI tCK tOUT1 tOUT2 tOUT3 min 18.5 18.5 37 max Unit ns ns ns 18.5 18.5 12.5 ns ns ns DCLKO DCKLO2 DCKLO3 DCLKO delay time DCLKO2 delay time DCLKO3 delay time No.A1186-15/17 LC749880T Sample Application Circuit AU1 AU2 Multiplex LV1116 LA4635A Tuner (2in1) LC749880T CVBS1 CVBS2 S-Y S-C Y Cb Cr SVO AFE & ADC YC Sep. & Chroma Dec. NoiseCanceller R Sharpness Brightness Contrast & White Balance & Black Balance & γ Correction G B Timing Controller DCLK Timings LCD Panel (VGA) Color Tint Color Exitor Shadow Adjuster Scaler DHS DVS DDE HSI VSI PLL CNT1 Inverter SDA SCL XIN XOUT HSO VSO CLKO LC87xxxx (μ-CON) RIN X’tal GIN BIN EN 27.0MHz Others (for TEST ⋅ ⋅ ⋅) LV78200 (Sync. Sep.) X’tal 32.768kHz No.A1186-16/17 LC749880T SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein. SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO Semiconductor Co.,Ltd. products described or contained herein are controlled under any of applicable local export control laws and regulations, such products may require the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written consent of SANYO Semiconductor Co.,Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO Semiconductor Co.,Ltd. product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. Upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third party. SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's intellectual property rights which has resulted from the use of the technical information and products mentioned above. This catalog provides information as of May, 2008. Specifications and information herein are subject to change without notice. PS No.A1186-17/17