LC75391M

Ordering number :EN*5201A CMOS LSI LC75391, 75391M Single-Chip Electronic Volume Control System Overview The LC75391 and LC75391M are single-chip electronic volume and tone control systems that support volume control, tone control, and input and output signal switching functions controlled by serial input data. Package Dimensions unit: mm 3196-DIP30SD [LC75391] Functions • Input and output signal switching: The four I/O switches can be set to on or off independently. • Volume control: Independent control of the left and right channels can be used to implement a balance function. 0 to –20 dB in 2 dB steps, –20 to –32 dB in 3 dB steps, –32 to –53 dB in 4 dB steps, –52 to –70 dB in 4.5 dB steps, and –∞. • Tone controls: Four frequency characteristic types selectable by setting internal switches. Also supports a buffer function that requires no external components. • Two general-purpose output ports: These ports allow this LSI to control motorized volume controls and general-purpose logic. SANYO: DIP30SD unit: mm 3216-MFP30S [LC75391M] • CCB is a trademark of SANYO ELECTRIC CO., LTD. • CCB is SANYO’s original bus format and all the bus addresses are controlled by SANYO. Specifications Absolute Maximum Ratings at Ta = 25°C, VSS = 0 V Parameter Maximum supply voltage Maximum input voltage Allowable power dissipation Operating temperature Storage temperature Symbol VDD max VIN max Pd max Topr Tstg VDD CL, DI, CE, L1 to L4, R1 to R4 Ta ≤ 85°C Conditions SANYO: MFP30S Ratings 12 VSS – 0.3 to VDD + 0.3 160 –40 to +85 –50 to +125 Unit V V mW °C °C SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN N3095HA (OT) No. 5201-1/13 LC75391, 75391M Allowable Operating Ranges at Ta = 25°C, VSS = 0 V Parameter Supply voltage Input high-level voltage Input low-level voltage Output high-level voltage Output low-level voltage Input voltage amplitude Input pulse width Setup time Hold time Operating frequency Symbol VDD VIH VIL VOH VOL VIN tøW tset up thold fopg VDD CL, DI, CE CL, DI, CE PA, PB: IO = 5 mA PA, PB: IO = 5 mA L1 to L4, R1 to R4 CL CL, DI, CE CL, DI, CE CL Conditions min 5.5 4.0 VSS VDD – 2 VSS VSS 1.0 1.0 1.0 500 typ max 11.0 VDD 1.0 VDD 2.0 VDD Unit V V V V V Vp-p µs µs µs kHz Electrical Characteristics at Ta = 25°C, VDD = 10 V, VSS = 0 V Parameter [Input Block] Input resistance [Overall Characteristics] THD (1) Total harmonic distortion THD (2) Crosstalk Maximum attenuation CT VO min VN (1) Output noise voltage VN (2) Current drain Input high-level current Input low-level current IDD IIH IIL VIN = 100 mVrms, f = 1 kHz, overall, buffer mode off, flat state VIN = 100 mVrms, f = 20 kHz, overall, buffer mode off, flat state VIN = 1 Vrms, f = 1 kHz, overall, Rg = 1 kΩ, buffer mode off, flat state VIN = 1 Vrms, f = 1 kHz, main volume at –∞, buffer mode on Flat overall (IHF-A), Rg = 1 kΩ, buffer mode off, flat state Flat overall (DIN-AUDIO), Rg = 1 kΩ, buffer mode off, flat state VDD – VSS = 11 V CL, DI, CE, VIN = 10 V CL, DI, CE, VIN = 0 V –10 0.013 0.013 81 –80 15 22 7 10 10 % % dB dB µV µV mA µA µA Rin L1 to L4, R1 to R4 500 kΩ Symbol Conditions min typ max Unit No. 5201-2/13 LC75391, 75391M Equivalent Circuit Block Diagram No. 5201-3/13 LC75391, 75391M Test Circuits 1. Total harmonic distortion No. 5201-4/13 LC75391, 75391M 2. Output noise voltage No. 5201-5/13 LC75391, 75391M 3. Crosstalk No. 5201-6/13 LC75391, 75391M Pin Assignment Pin Functions Pin No. Symbol Function Circuit configuration 1 30 PA PB Digital CMOS output port 2 29 LVROUT RVROUT Volume control circuit outputs 3 28 LTOUT RTOUT Tone control circuit outputs 4 27 LTCOM RTCOM Tone control circuit operational amplifier inverting inputs Continued on next page. No. 5201-7/13 LC75391, 75391M Continued from preceding page. Pin No. 8 7 6 5 23 24 25 26 12 11 10 9 19 20 21 22 13 18 17 Symbol LT1 LT2 LT3 LT4 RT1 RT2 RT3 RT4 L1 L2 L3 L4 R1 R2 R3 R4 VDD Vref VSS Power supply Analog system ground Ground Audio signal inputs and outputs Connections for the external components that determine the tone control pattern Function Circuit configuration 14 15 CL DI Serial data and clock inputs for device control Chip enable 16 CE Data is read into internal latches and all analog switches change state when this input changes from high to low. Data transfer is enabled when this input is high. No. 5201-8/13 LC75391, 75391M Volume Control Equivalent Circuit No. 5201-9/13 LC75391, 75391M Control System Timing and Data Formats The LC75391 is controlled by applying the stipulated data to the CE, CL, and DI pins. The data structure consists of a total of 32 bits, of which 8 bits are address and 24 bits are data. Note: The bits D20, D21, and D22 are test mode selection bits. These bits must be set to 0 by user applications. No. 5201-10/13 LC75391, 75391M Application Circuit Example 1 (3-input type) Usage Notes 1. The internal analog switch states are undefined when power is first applied. Signals should be muted externally until the control data has been set up. 2. Cover the CL, DI, and CE pin signal lines with the ground pattern or use shielded cable for those lines to prevent the high-frequency digital signals transmitted to the CL, DI, and CE pins from entering the analog system as noise. 3. Use bipolar capacitors if at all possible for capacitors for which no polarity is indicated. 4. We recommend making large changes in the electronic volume control setting, such as from 0 dB to –∞ dB, by using several intermediate steps as shown in the example below. This can reduce the switching noise associated with large changes. Example: 0 dB → –10 dB → –20 dB → –40 dB → –70 dB → –∞ No. 5201-11/13 LC75391, 75391M Application Circuit Example 2 (4-input type) Usage Notes 1. The internal analog switch states are undefined when power is first applied. Signals should be muted externally until the control data has been set up. 2. Cover the CL, DI, and CE pin signal lines with the ground pattern or use shielded cable for those lines to prevent the high-frequency digital signals transmitted to the CL, DI, and CE pins from entering the analog system as noise. 3. If at all possible, use bipolar capacitors for capacitors which have no polarity indicated. 4. We recommend using several intermediate steps as shown in the example below to make large changes in the electronic volume control setting, such as from 0 dB to –∞ dB. This can reduce the switching noise associated with these large changes. Example: 0 dB → –10 dB → –20 dB → –40 dB → –70 dB → –∞ No. 5201-12/13 LC75391, 75391M s No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. s Anyone purchasing any products described or contained herein for an above-mentioned use shall: Œ Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use:  Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. s Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of November, 1995. Specifications and information herein are subject to change without notice. PS No. 5201-13/13