LC75394

Ordering number : EN5466 CMOS LSI LC75394NE Single-Chip Electronic Volume Control System Overview The LC75394NE is an electronic volume control system providing control over volume, balance, 5-band equalizer, and input switching based on serial inputs. Package Dimensions unit: mm 3159-QFP64E [LC75394NE] Functions • Volume control: The chip provides 25 levels of volume attenuation: in 2dB steps between 0 dB and –20 dB, 3-dB steps between –20 dB and –32 dB, 4-dB steps between –32 dB and –52 dB, 4.5-dB steps between –52 dB and –70 dB, and – ∞. Independent control over left and right channels provides balance control. • Equalizer: The chip provides control in 2-dB steps over the range between +10 dB and –10 dB. Four of the five bands have peaking equalization; the remaining one, shelving equalization. • Selector: The left and right channels each offer a choice of four inputs. An external constant determines the amplification for the input signal. SANYO: QFP64E Features • Built-in buffer amplifiers reduce the number of external parts necessary. • Silicon gate CMOS reduces switching noise. • Serial data input —Supports CCB* format communication with the system controller. • A built-in reference voltage circuit divides the supply voltage (VDD) in half. * • CCB is a trademark of SANYO ELECTRIC CO., LTD. • CCB is SANYO’s original bus format and all the bus addresses are controlled by SANYO. Specifications Absolute Maximum Ratings at Ta = 25°C, VSS = 0 V Parameter Maximum supply voltage Maximum input voltage Allowable power dissipation Operating temperature Storage temperature Symbol VDD max VIN max Pd max Topr Tstg VDD CL, DI, CE, L1 to L4, R1 to R4, LTIN, RTIN, LVRIN, RVRIN Ta ≤ 85°C Conditions Ratings 12 VSS – 0.3 to VDD + 0.3 310 –30 to +85 –40 to +125 Unit V V mW °C °C SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN 91096HA (OT)/81095HA (OT) No. 5466-1/17 LC75394NE Allowable Operating Ranges at Ta = 25°C, VSS = 0 V Parameter Supply voltage Input high level voltage Input low level voltage Input voltage amplitude Input pulse width Setup time Hold time Operating frequency Symbol VDD VIH VIL VIN tøW tSETUP tHOLD fopg VDD CL, DI, CE CL, DI, CE CL, DI, CE, L1 to L4, R1 to R4, LTIN, RTIN, LVRIN, RVRIN CL CL, DI, CE CL, DI, CE CL Conditions min 6.0 4.0 VSS VSS 1.0 1.0 1.0 500 typ max 11.0 VDD 1.0 VDD Unit V V V Vp-p µs µs µs kHz Electrical Characteristics at Ta = 25°C, VDD = 10 V, VSS = 0 V Parameter [Input block] Input resistance Clipping level Output load resistance [Volume control block] Input resistance [Equalizer control block] Control range Step resolution Internal feedback resistance [Overall characteristics] Total harmonic distortion Crosstalk Output at maximum attenuation Output noise voltage Current drain Input high level current Input low level current THD (1) THD (2) CT VO min VN (1) VN (2) IDD IIH IIL VIN = 1 Vrms, f = 1 kHz, with all controls flat overall VIN = 1 Vrms, f = 20 kHz, with all controls flat overall VIN = 1 Vrms, f = 1 kHz, with all controls flat overall, Rg = 1 kΩ VIN = 1 Vrms, f = 1 kHz, main volume – ∞ With all controls flat overall (IHF-A), Rg = 1 kΩ With all controls flat overall (DIN-AUDIO), Rg = 1 kΩ VDD – VSS = 11 V CL, DI, CE, VIN = 11 V CL, DI, CE, VIN = 0 V –10 0.0033 0.012 86 –90 3.9 5.4 25 33 10 % % dB dB µV µV mA µA µA Geq Estep Rfeed Max, boost/cut ±8 1 17 ±10 2 28 ±12 3 39 dB dB kΩ Rin LVRIN, RVRIN 60 100 140 kΩ Rin Vcl RL L1 to L4, R1 to R4 LSELO, RSELO: THD = 1.0% LSELO, RSELO 3 1 2.65 MΩ Vrms kΩ Symbol Conditions min typ max Unit Input Amplifier Characteristics at Ta = 25°C, VDD – VSS = 10 V Parameter Input offset voltage Input offset current Open-loop voltage gain Width of 0 dB band Allowable load resistance Symbol VIO IIO AO fT RL 3 VSS ≤ VIN ≤ VDD Conditions min –10 ±10 80 2.5 typ max +10 Unit mV nA dB MHz kΩ No. 5466-2/17 LC75394NE Equivalent Block Diagram and Sample Application Circuit No. 5466-3/17 LC75394NE Test Circuits 1. Total Harmonic Distortion No. 5466-4/17 LC75394NE 2. Output Noise Voltage No. 5466-5/17 LC75394NE 3. Crosstalk No. 5466-6/17 LC75394NE Pin Assignment No. 5466-7/17 LC75394NE Pin Functions Pin No. 12 11 10 37 38 39 9 8 7 40 41 42 6 5 4 43 44 45 3 2 1 46 47 48 Symbol LF1C1 LF1C2 LF1C3 RF1C1 RF1C2 RF1C3 LF2C1 LF2C2 LF2C3 RF2C1 RF2C2 RF2C3 LF3C1 LF3C2 LF3C3 RF3C1 RF3C2 RF3C3 LF4C1 LF4C2 LF4C3 RF4C1 RF4C2 RF4C3 F4 band control block for right channel. Connect to external capacitors. F4 band control block for left channel. Connect to external capacitors. F3 band control block for right channel. Connect to external capacitors. F3 band control block for left channel. Connect to external capacitors. F2 band control block for right channel. Connect to external capacitors. F2 band control block for left channel. Connect to external capacitors. F1 band control block for right channel. Connect to external capacitors. F1 band control block for left channel. Connect to external capacitors. Function Note 13 36 LTIN RTIN Tone control inputs. Must be driven with low-impedance circuits. 14 35 LSELO RSELO Input selector outputs 64 49 LF5 RF5 F5 band control block. Connect to external capacitors. 21 19 17 16 28 30 32 33 57 22, 26 27 L1 L2 L3 L4 R1 R2 R3 R4 VDD VSS AVSS Power supply connection Grounds for internal logic Ground for internal operational amplifier Signal inputs Continued on next page. No. 5466-8/17 LC75394NE Continued from preceding page. Pin No. Symbol Function Note 56 Vref VDD/2 voltage generator block. Connect capacitors between Vref and VSS to minimize the effects of power supply ripple. 63 50 LVref RVref Pins common to volume control, tone control, and input selection blocks. Select the capacitors between these pins and VSS carefully as they contribute residual resistance when the volume is turned down. The voltage must never exceed VDD. 15 34 LINVIN1 RINVIN1 Operational amplifier inverted input for specifying input gain. 62 51 LINVIN2 RINVIN2 Operational amplifier inverted input for specifying graphic equalization. Connecting a capacitor across INVIN2 and TOUT permits the removal of unwanted bands and reduces the risk of oscillation. 61 52 LTOUT RTOUT Tone control output 60 53 LVRIN RVRIN Volume control input. Must be driven with low-impedance circuits. 58 55 LVROUT RVROUT Volume control output 25 CE Chip enable pin. The chip uses falling edge timing to write data to the internal latch and shift analog switches. The high level enables data transfer. 24 23 18 20 29 31 54 59 DI CL NC NC NC NC NC NC Serial data and clock input used for control Leave unconnected No. 5466-9/17 LC75394NE Input Block Internal Equivalent Circuit Diagram Volume Control Block Internal Equivalent Diagram No. 5466-10/17 LC75394NE Equalizer Control Block Internal Equivalent Circuit (Bands F1 to F4) Calculating the Size of External Capacitors The LC75394NE supports four bands with peaking characteristics and one band with shelving characteristics 1. Peaking Characteristics (bands F1 to F4) The external capacitor functions as the structural element of a simulated inductor. The equivalent circuit and the calculations required to achieve the desired center frequency are shown below. • Equivalent circuit for the simulated inductor No. 5466-11/17 LC75394NE • Calculation example Specifications: Central frequency, FO = 107 Hz Q factor at maximum boost, Q+10 dB = 0.8 — Calculate QO, the sharpness of the simulated inductance itself. QO = (R1 + R4)/R1 × Q+10dB Note: R4 is from the separately issued internal block diagram. ≠ 4.270 — Calculate C1 C1 = 1/2πFOR1QO ≠ 0.536 (µF) — Calculate C2 C2 = QO/2πFOR2 ≠ 0.021 (µF) • Sample results Central frequency FO (Hz) 107 340 1070 3400 C1 (F) 0.536 µ 0.169 µ 0.054 µ 0.017 µ C2 (F) 0.021 µ 6663 P 2117 P 666 P • Shelving characteristics (Band F5) Achieving the desired control of 2-dB steps over the range between +10 dB to –10 dB requires choosing a capacitor, C3, with an impedance of 650 Ω. No. 5466-12/17 LC75394NE Control System Timing and Data Formats The LC75394NE receives its control sequences via a serial interface comprised of pins CE, CL, and DI. Each sequence consists of 40 bits: an 8-bit address followed by 32 bits of data. No. 5466-13/17 LC75394NE No. 5466-14/17 LC75394NE No. 5466-15/17 LC75394NE Usage Notes 1. When the power is first applied, the internal analog switches are in indeterminate states. The chip therefore requires muting or other external measures until it has received the proper data. 2. Provide grounding patterns or shielding for the lines to the CL, DI, and CE pins so as to prevent their high-frequency data signals from interfering with the operation of nearby analog circuits. No. 5466-16/17 LC75394NE s No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. s Anyone purchasing any products described or contained herein for an above-mentioned use shall: Œ Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use:  Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. s Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of September, 1996. Specifications and information herein are subject to change without notice. No. 5466-17/17