LC75852E

Ordering number : EN4828A CMOS LSI LC75852E, 75852W Asynchronous Silicon Gate 1/2 Duty LCD Driver with On-Chip Key Input Function Overview The LC75852E and LC75852W are 1/2 duty dynamic LCD display drivers. In addition to being able to directly drive LCD panels with up to 90 segments, they can also control up to four general-purpose output ports. These products also include a key scan circuit which allows them to accept input from keypads with up to 30 keys. This allows end product front panel wiring to be simplified. Package Dimensions unit: mm 3159-QFP64E [LC75852E] Features • Up to 30 key inputs (Key scan is only performed when a key is pressed.) • 1/2 duty – 1/2 bias (up to 90 segments) • Sleep mode and the all segments off function can be controlled from serial data. • Segment output port/general-purpose output port usage can be controlled from serial data. • Serial data I/O supports CCB format communication with the system controller. • High generality since display data is displayed directly without decoder intervention • Reset pin that can establish the initial state. SANYO: QIP64E unit: mm 3190-SQFP64 [LC75852W] • CCB is a trademark of SANYO ELECTRIC CO., LTD. • CCB is SANYO’s original bus format and all the bus addresses are controlled by SANYO. Specifications Absolute Maximum Ratings at Ta = 25°C, VSS = 0 V Parameter Maximum supply voltage Input voltage Output voltage Symbol VDD max VIN VOUT IOUT1 Output current IOUT2 IOUT3 Allowable power dissipation Operating temperature Storage temperature Pd max Topr Tstg VDD OSC, CE, CL, DI, RES, KI1 to KI5 OSC, DO, S1 to S45, COM1, COM2, KS1 to KS6, P1 to P4 S1 to S45 COM1, COM2, KS1 to KS6 P1 to P4 Ta = 85°C Conditions SANYO: SQFP64 Ratings –0.3 to +7.0 –0.3 to VDD + 0.3 –0.3 to VDD + 0.3 100 1 5 200 –40 to +85 –55 to +125 Unit V V V µA mA mA mW °C °C SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN 63096HA (OT)/N1594TH (OT) B8-1326, 1328 No. 4828-1/16 LC75852E, 75852W Allowable Operating Ranges at Ta = –40 to +85°C, VSS = 0 V Parameter Supply voltage Input high-level voltage Input low-level voltage Recommended external resistance Recommended external capacitance Guaranteed oscillator range Data setup time Data hold time CE wait time CE setup time CE hold time High-level clock pulse width Low-level clock pulse width Rise time Fall time DO output delay time DO rise time RES switching time Symbol VDD VIH1 VIH2 VIL ROSC COSC fOSC tds tdh tcp tcs tch tøH tøL tr tf tdc tdr t2 VDD CE, CL, DI, RES KI1 to KI5 CE, CL, DI, RES, KI1 to KI5 OSC OSC OSC CL, DI: Figure 1 CL, DI: Figure 1 CE, CL: Figure 1 CE, CL: Figure 1 CE, CL: Figure 1 CL: Figure 1 CL: Figure 1 CE, CL, DI: Figure 1 CE, CL, DI: Figure 1 DO, RPU = 4.7 kΩ, CL = 10 pF*: Figure 1 DO, RPU = 4.7 kΩ, CL = 10 pF*: Figure 1 Figure 2 10 25 160 160 160 160 160 160 160 160 160 1.5 1.5 Conditions min 4.5 0.8 VDD 0.6 VDD 0 62 680 50 100 typ max 6.0 VDD VDD 0.2 VDD Unit V V V V kΩ pF kHz ns ns ns ns ns ns ns ns ns µs µs µs Note: * Since DO is an open-drain output, these values differ depending on the pull-up resistor RPU and the load capacitance CL. Electrical Characteristics in the Allowable Operating Ranges Parameter Hysteresis Input high-level current Input low-level current Input floating voltage Pull-down resistance Output off leakage current Symbol VH IIH IIL VIF RPD IOFFH VOH1 Output high-level voltage VOH2 VOH3 VOH4 VOL1 VOL2 Output low-level voltage VOL3 VOL4 VOL5 Output middle-level voltage VMID1 VMID2 IDD1 IDD2 Conditions CE, CL, DI, RES, KI1 to KI5 CE, CL, DI, RES: VI = 6.0 V CE, CL, DI, RES: VI = 0 V KI1 to KI5 KI1 to KI5: VDD = 5.0 V DO: VO = 6.0 V KS1 to KS6: IO = –1 mA P1 to P4: IO = –1 mA S1 to S45: IO = –10 µA COM1, COM2: IO = –100 µA KS1 to KS6: IO = 50 µA P1 to P4: IO = 1 mA S1 to S45: IO = 10 µA COM1, COM2: IO = 100 µA DO: IO = 1 mA COM1, COM2: VDD = 6.0 V, IO = ±100 µA COM1, COM2: VDD = 4.5 V, IO = ±100 µA Sleep mode, Ta = 25°C VDD = 6.0 V, output open, Ta = 25°C, fOSC = 50 kHz 1.4 2.4 1.65 0.1 3.0 2.25 VDD – 1.0 VDD – 1.0 VDD – 1.0 VDD – 0.6 0.4 1.0 3.0 1.0 1.0 0.6 0.5 3.6 2.85 5 2.5 50 100 –5.0 0.05 VDD 250 6.0 min typ 0.1 VDD 5.0 max Unit V µA µA V kΩ µA V V V V V V V V V V V µA mA Current drain No. 4828-2/16 LC75852E, 75852W 1. When stopped with CL at the low level 2. When stopped with CL at the high level Figure 1 Pin Assignment No. 4828-3/16 LC75852E, 75852W Block Diagram Pin Functions Pin Pin No. Function Segment outputs: Used to output the display data that is transmitted over the serial data input. Pins S1/P1 to S4/P4 can be used as general-purpose outputs according to control data specification. Active I/O Handling when unused S1/P1 to S4/P4 S5 to S43 1 to 4 5 to 43 — O Open COM1 COM2 44 45 Common driver outputs. The frame frequency fO is (fOSC/512) Hz. — O Open KS1/S44, KS2/S45, KS3 to KS6 46 47 48 to 51 Key scan outputs. When a key matrix is formed, normally a diode will be attached to the key scan timing line to prevent shorts. However, since the output transistor impedance is an unbalanced CMOS output, it will not be damaged if shorted. Pins KS1/S44 and KS2/S45 can be used as segment outputs according to control data specification. Key scan inputs: Pins with a built-in pull-down resistor. Oscillator connection: Oscillator circuit can be formed by connecting the pin to a resistor and a capacitor. Serial data interface: Connected to the controller. Since DO is an open-drain output, it requires a pull-up resistor. CE: Chip enable CL: Synchronization clock DI: Transfer data DO: Output data — O Open KI1 to KI5 OSC CE CL DI DO 52 to 56 57 62 63 64 61 H — H I I/O I I GND VDD GND — — I O Open RES 59 Reset input that re-initializes the LSI internal states. During a reset, the display segments are turned off forcibly regardless of the internal display data. All internal key data is reset to low and the key scan operation is disabled. However, serial data can be input during a reset. Power supply connection. A supply voltage of between 4.5 and 6.0 V must be provided. Power supply ground connection. Must be connected to GND. L I GND VDD VSS 60 58 — — — — — — No. 4828-4/16 LC75852E, 75852W Serial Data Input 1. When stopped with CL at the low level 2. When stopped with CL at the high level CCB address......................[42H] D1 to D90 ...........................Display data S0, S1 ................................Sleep control data K0, K1 ................................Key scan output/segment output selection data P0, P1 ................................Segment output port/general-purpose output port selection data SC ......................................Segment on/off control data No. 4828-5/16 LC75852E, 75852W Control Data Functions 1. S0, S1 .................Sleep control data This control data switches the LSI between normal mode and sleep mode. It also sets the key scan output standby states for pins KS1 to KS6. Control data S0 0 0 1 1 S1 0 1 0 1 Mode Normal Sleep Sleep Sleep Oscillator Oscillator Stopped Stopped Stopped Segment outputs Common outputs Operation L L L Key scan standby mode output pin states KS1 H L L H KS2 H L L H KS3 H L L H KS4 H L L H KS5 H L H H KS6 H H H H Note: The KS1/S44 and KS2/S45 output pins are set to the key scan output state. 2. K0, K1................Key scan output/segment output selection data This control data switches the KS1/S44 and KS2/S45 output pins between the key scan output and segment output functions. Control data K0 0 0 1 X: don’t care K1 0 1 X Output pin states KS1/S44 KS1 S44 S44 KS2/S45 KS2 KS2 S45 Maximum number of key inputs 30 25 20 3. P0, P1 .................Segment output port/general-purpose output port selection data This control data switches the S1/P1 to S4/P4 output pins between the segment output port and the general-purpose output port functions. Control data P0 0 0 1 1 P1 0 1 0 1 S1/P1 S1 P1 P1 P1 Output pin states S2/P2 S2 P2 P2 P2 S3/P3 S3 S3 P3 P3 S4/P4 S4 S4 S4 P4 The table below lists the correspondence between the display data and the output pins when the general-purpose output port function is selected. Output pin S1/P1 S2/P2 S3/P3 S4/P4 Corresponding display data D1 D3 D5 D7 For example, if the output pin S4/P4 is set for use as a general-purpose output port, the output pin S4/P4 will output a high level when the display data D7 is 1. 4. SC.......................Segment on/off control data This control data controls the segment on/off states. SC 0 1 Display state On Off No. 4828-6/16 LC75852E, 75852W Display Data and Output Pin Correspondences Output pin S1/P1 S2/P2 S3/P3 S4/P4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 S17 S18 S19 S20 S21 S22 S23 S24 S25 S26 S27 S28 S29 S30 S31 S32 S33 S34 S35 S36 S37 S38 S39 S40 S41 S42 S43 KS1/S44 KS2/S45 COM1 D1 D3 D5 D7 D9 D11 D13 D15 D17 D19 D21 D23 D25 D27 D29 D31 D33 D35 D37 D39 D41 D43 D45 D47 D49 D51 D53 D55 D57 D59 D61 D63 D65 D67 D69 D71 D73 D75 D77 D79 D81 D83 D85 D87 D89 COM2 D2 D4 D6 D8 D10 D12 D14 D16 D18 D20 D22 D24 D26 D28 D30 D32 D34 D36 D38 D40 D42 D44 D46 D48 D50 D52 D54 D56 D58 D60 D62 D64 D66 D68 D70 D72 D74 D76 D78 D80 D82 D84 D86 D88 D90 For example, the output states of output pin S11 are listed in the table below. Display data D21 0 0 1 1 D22 0 1 0 1 Output pin state S11 Segment off for both COM1 and COM2 Segment on for COM2 Segment on for COM1 Segments on for both COM1 and COM2 No. 4828-7/16 LC75852E, 75852W Serial Data Output 1. When stopped with CL at the low level 2. When stopped with CL at the high level CCB address......................[43H] KD1 to KD30 ......................Key data SA ......................................Sleep acknowledge data Note: If key data is read when DO is high, the key data (KD1 to KD30) and sleep acknowledge data (SA) will be invalid. Output Data 1. KD1 to KD30.....Key data When a key matrix with up to 30 keys is formed using the KS1 to KS6 output pins and the KI1 to KI5 input pins, the key data corresponding to a given key will be 1 if that key is pressed. The table below lists that correspondence. Item KS1/S44 KS2/S45 KS3 KS4 KS5 KS6 KI1 KD1 KD6 KD11 KD16 KD21 KD26 KI2 KD2 KD7 KD12 KD17 KD22 KD27 KI3 KD3 KD8 KD13 KD18 KD23 KD28 KI4 KD4 KD9 KD14 KD19 KD24 KD29 KI5 KD5 KD10 KD15 KD20 KD25 KD30 When the output pins KS1/S44 and KS2/S45 are selected for segment output by the control data K0 and K1, the key data items KD1 to KD10 will be 0. 2. SA ......................Sleep acknowledge data This output data is set according to the state when the key was pressed. If the LSI was in sleep mode, SA will be 1, and if the LSI was in normal mode, SA will be 0. Sleep Mode When S0 or S1 in the control data is set to 1, the oscillator at the OSC pin will stop (it will restart if a key is pressed) and the segment and common outputs will all go to the low level. This reduces the LSI power dissipation. However, the S1/P1 to S4/P4 output pins can be used as general-purpose output ports even in sleep mode if selected for such use by the P0 and P1 control data bits. No. 4828-8/16 LC75852E, 75852W Key Scan Operation 1. Key Scan Timing The key scan period is 375T [s]. The key scan is performed twice to reliably determine the key on/off states, and the LSI detects key data agreement. When the key data agrees, the LSI determines that a key has been pressed, and outputs a key read request (by setting DO low) 800T [s] after the key scan started. If a key is pressed again without the key data agreeing, a key scan is performed once more. Thus key on/off operations shorter than 800T [s] cannot be detected. *1 The high or low states of these signals in sleep mode are determined by the S0 and S1 control data bits. 2. Key Scan during Normal Mode • The pins KS1 to KS6 are set high. • A key scan starts if any key is pressed, and the scan continues until all keys have been released. Multiple key presses can be recognized by determining if multiple key data bits have been set. • When a key has been pressed for 800T [s] (where T = 1/fOSC) or longer, a key data read request (DO is set to low) is output to the controller. The controller acknowledges this request and reads the key data. However, DO will go high when CE is high during a serial data transfer. • After the controller has finished reading the key data, the LSI clears the key data read request (by setting DO high) and performs another key scan. Note that since DO is an open drain output, a pull-up resistor of between 1 and 10 kΩ is required. No. 4828-9/16 LC75852E, 75852W 3. Key Scan during Sleep Mode • The pins KS1 to KS6 are set high or low according to the S0 and S1 control data bits. (See the description of the control data function for details.) • If a key for a line corresponding to one of the pins KS1 to KS6 which is high is pressed, the oscillator at the OSC pin starts and a key scan is performed. The key scan continues until all keys have been released. Multiple key presses can be recognized by determining if multiple key data bits have been set. • When a key has been pressed for 800T [s] (where T = 1/fOSC) or longer, a key data read request (DO is set to low) is output to the controller. The controller acknowledges this request and reads the key data. However, DO will go high when CE is high during a serial data transfer. • After the controller has finished reading the key data, the LSI clears the key data read request (by setting DO high) and performs another key scan. Note that since DO is an open drain output, a pull-up resistor of between 1 and 10 kΩ is required. • Key scan example in sleep mode Example: Here S0 = 0 and S1 = 1 (This is a sleep in which only KS6 is high.) Multiple Key Presses Without the insertion of additional diodes, the LC75852 supports key scan for double key presses in general, triple key presses of keys on the lines for input pins KI1 to KI5, and multiple key presses of keys on the lines for the output pins KS1 to KS6. However, if multiple key presses in excess of these limits occur, the LC75852 may recognize keys that were not pressed as having been pressed. Therefore, series diodes must be connected to each key. No. 4828-10/16 LC75852E, 75852W 1/2 Duty - 1/2 Bias LCD Drive Scheme COM1 COM2 S1 to S45 outputs for segments on COM1 side being lit S1 to S45 outputs for segments on COM2 side being lit S1 to S45 outputs for segments on COM1,COM2 sides being lit S1 to S45 outputs for segments on COM1,COM2 sides not being lit RES and the Display Controller Since the LSI internal data (D1 to D90 and the control data) is undefined when power is first applied, the output pins S1/P1 to S4/P4, S5 to S43, COM1, COM2, KS1/S44 and KS2/S45 should be held low by setting the RES pin low at the same time as power is applied. Then, meaningless displays at power on can be prevented by transferring data from the controller and setting RES high when that transfer has completed. Figure 2 No. 4828-11/16 LC75852E, 75852W Internal Block States during the Reset Period (when RES is low) 1. CLOCK GENERATOR Reset is applied and the basic clock stops. However, the state of the OSC pin (the normal or sleep state) is determined after the control data S0 and S1 has been sent. 2. COMMON DRIVER, SEGMENT DRIVER & LATCH Reset is applied and the display is turned off. However, display data can be input to the LATCH. 3. KEY SCAN Reset is applied and at the same time as the internal states are set to their initial states, the key scan operation is disabled. 4. KEY BUFFER Reset is applied and all the key data is set to the low level. 5. CCB INTERFACE, CONTROL REGISTER, SHIFT REGISTER To allow serial data transfers, reset is not applied to these circuits. Output Pin States during the Reset Period (when RES is low) Output pin S1/P1 to S4/P4 S5 to S43 COM1, COM2 KS1/S44, KS2/S45 KS3 to KS5 KS6 State during reset L*3 L L L*3 X*4 H DO H*5 X: don’t care Note: 3. These output pins are forcibly set to the segment output mode and held low. 4. Immediately following power on, these output pins are undefined until the control data S0 and S1 has been sent. 5. Since this output pin is an open-drain output, a pull-up resistor of between 1 and 10 kΩ is required. This pin is held high during the reset period even if key data is read. No. 4828-12/16 LC75852E, 75852W Sample Application Circuit Note: * Since DO is an open-drain output, a pull-up resistor is required. Select a value (between 1 and 10 kΩ) that is appropriate for the capacitance of the external wiring so that the waveforms are not distorted. Notes on Controller Display Data Transfer The LC75852 transfers the display data (D1 to D90) in two operations. To assure visual display quality, all the display data should be sent within a 30 ms or shorter period. No. 4828-13/16 LC75852E, 75852W Notes on Controller Key Data Read Techniques 1. Controller key data reading under timer control • Flowchart • Timing Chart t3 ..................Key scan execution time (800T [s]) when the key scan data for two key scans agrees t4 ..................Key scan execution time (1600T [s]) when the key scan data for two key scans does not agree and a key scan is executed again t5 ..................Key address (43H) transfer time t6 ..................Key data read time 1 T= fOSC • Description When determining key on/off and reading key data, the controller must confirm the state of DO output when CE is low for each period t7. When DO is low, the controller recognizes that a key has been pressed and reads the key data. During this operation t7 must obey the following condition: t7 > t5 + t6 + t4 If key data is read when DO is high, the key data (KD1 to KD30) and the sleep acknowledge data (SA) will be invalid. No. 4828-14/16 LC75852E, 75852W 2. Controller key data reading under interrupt control • Flowchart • Timing Chart t3 ..................Key scan execution time (800T [s]) when the key scan data for two key scans agrees t4 ..................Key scan execution time (1600T [s]) when the key scan data for two key scans does not agree and a key scan is executed again t5 ..................Key address (43H) transfer time t6 ..................Key data read time 1 T= fOSC No. 4828-15/16 LC75852E, 75852W • Description When determining key on/off and reading key data, the controller must confirm the state of DO output when CE is low. When DO is low, the controller recognizes that a key has been pressed and reads the key data. After the time t8, the next key on/off determination and reading key data must be confirmed by the state of DO output when CE is low. During this operation t8 must obey the following condition: t8 > t4 If key data is read when DO is high, the key data (KD1 to KD30) and the sleep acknowledge data (SA) will be invalid. s No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. s Anyone purchasing any products described or contained herein for an above-mentioned use shall: Œ Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use:  Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. s Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of November, 1997. Specifications and information herein are subject to change without notice. No. 4828-16/16