LC7851

Ordering number : EN5691 CMOS LSI LC7851E QPSK Demodulation and Audio Signal-Processing IC for Satellite Broadcast Reception Overview The LC7851E demodulates the QPSK (quadrature phase shift keying) modulated audio data broadcast by the Japanese BS and CS broadcast satellites and converts that data to an analog audio signal. This IC integrates on a single chip the audio system signal processing required for BS and CS receivers from QPSK demodulation to analog audio reproduction. The main functions provided by the LC7851E include QPSK demodulation, differential decoding conversion, descrambling, deinterleaving, and error correction. It also generates a PCM audio signal. The PCM audio signal is converted to an analog audio signal by on-chip digital filters and A/D converters. Features • QPSK demodulator, PCM decoder, digital filters, D/A converters, and operational amplifiers integrated on a single chip. • The number of required external components has been reduced and adjustment-free operation achieved in the QPSK demodulator by implementing that block as a digital circuit on a single chip. • CPU interface using an I2C bus • Interface circuits for CORTEC and SkyPort descramblers • Ten to 14 bit expansion of audio data during A mode broadcasts. • Data protection using majority control for the upper bits of the audio data during B mode broadcasts • Full complement of muting functions — Audio suppression provided (bit 16 of the postmajority decision control bits) — Non-audio signal suppression (bits 2 to 5 of the postmajority decision control bits) — Forced muting — Muting when not synchronized — Muting when large numbers of errors are detected (modifiable conditions) — Channel switching — Charged (pay-per-view) program flag muting — Mute detection output provided. • General-purpose ports (2 input ports and 8 output ports) • EIAJ digital audio interface output • 8× oversampling digital filters • Multi-bit D/A converter (with built-in output operational amplifiers) • 5 V single-voltage power supply • QFP (QIP) 64E package Package Dimensions unit: mm 3195-QFP64E [LC7851E] Functions • QPSK demodulation • Bit timing clock recovery • Differential decoding conversion and parallel-to-serial conversion • Frame synchronization (forward protection: 8 cycles, back protection: 3 cycles): Frame synchronized/not synchronized detection flag output provided. • Tenth-order M-series descrambling • Deinterleaving • BCH (63, 56) error correction and dual error detection: Single error detected flag output provided. • Support for both interpolation and previous data hold when a dual error is detected. Control bit majority judgment protection every 16 frames • Register data previous value hold when dual errors are detected using BCH(7,3) SANYO: QIP64E SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN 83097HA(OT) No. 5691-1/9 Block Diagram Scramble interface 1 Scramble interface 2 8× oversampling digital filters Differential conversion parallel-to-serial converter Descrambler Deinterleaving 10 to 14 bits expansion Upper bit majority protection Sync detection and sync protection Control bit extraction Error detection and correction Range bit error correction For-fee flag detection Audio switching Data interpolation and previous value hold Digital de-emphasis filter LC7851E QPSK demodulator D/A converter Digital audio interface output Audio signal buffer amplifier Bit timing clock recovery CPU interface General-purpose ports No. 5691-2/9 LC7851E Pin Assignment CVDD DVDD CVSS DVSS VSS VDD PVSS PVDD DVSS VVDD VVSS AVSS DVDD Pin Functions Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 Pin BSTRI BSTRO P7 P6 P5 P4 P3 P2 P1 P0 CK5M DVDD TSL AVSS QPSKI AVDD VRM AVSS VRB VCADJ VCIN I I/O I O O O O O O O O O O I I I I I O I O Bit stream input Bit stream output General-purpose output port General-purpose output port General-purpose output port General-purpose output port General-purpose output port General-purpose output port General-purpose output port General-purpose output port Filter adjustment clock output (5.7272 MHz) Digital system power supply Output control for the state when reset by the PHCNT pin (Low: high-impedance, high: 50% duty pulse output) Internal A/D converter ground QPSK modulated signal input Internal A/D converter power supply Internal A/D converter reference (center) output Internal A/D converter ground Internal A/D converter reference (low) output Connection for internal VCO adjustment external resistor Internal VCO control input Function AVDD AVSS Continued on next page. No. 5691-3/9 LC7851E Continued from preceding page. Pin No. 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Pin VVSS VVDD (N.C) PVDD PHCNT PVSS (N.C) VDD XI1 XO1 VSS DVSS DADO (N.C) (N.C) (N.C) (N.C) (N.C) TEST1 TEST2 DVDD CVSS AOUTL REFL REFH AOUTR CVDD RST MUTI MUTO MOD LOIN ERR REQ SDA SCL DVSS DSTRI2 DSTRI1 DSTRO DASL FRM CK2M I I I I O O O O I I I O O O O O I/O I I I I O I O O Test pin Test pin Digital system power supply Internal D/A converter ground Left channel audio data output Internal D/A converter reference voltage: low Internal D/A converter reference voltage: high Right channel audio data output Internal D/A converter power supply Reset input Forced muting input Mute detection output (When muting detected: high) Audio mode detection output (A mode: low, B mode: high) Frame synchronization detection output (When synchronized: low) Error detection output (Error detected: high) Host CPU readout request signal I2C bus data I/O I2C bus clock input Digital system ground Data stream input 2/general-purpose I/O port Data stream input 1/general-purpose I/O port Data stream output (post-error correction data) Descrambler interface switching Frame synchronization signal Bit stream clock (2.048 MHz) I I O I I O Oscillator circuit power supply Crystal oscillator (22.909088 MHz) input Crystal oscillator (22.909088 MHz) output Oscillator circuit ground Digital system ground Digital audio interface output I O I Phase comparator power supply Phase comparator output Phase comparator ground I/O I I Internal VCO ground Internal VCO power supply Function Caution: All NC pins must be left open. No. 5691-4/9 LC7851E Pin Input and Output Circuit Diagrams • Output pins (Output pins other than P0 to P7, SDA, PHCNT, CK5M, VRM, VRB, REFH, REFL, AOUTR, and AOUTL) • Output pins: P0 to P7 These are n-channel open drain outputs. • Output pin: CK5M • Output pin: PHCNT • Input pins (Input pins other than QPSKI, SCL, SDA, DSTRI1, DSTRI2, and VCIN) • Input pins: SCL, DSTRI1, and DSTRI2 • I/O pin: SDA No. 5691-5/9 LC7851E Specifications Absolute Maximum Ratings at Ta = 25°C, VSS = 0 V Parameter Supply voltage Input voltage Symbol VDD VI1 VI2 Output voltage Allowable power dissipation Operating temperature Storage temperature VO Pd max Topr Tstg Ta = –20 to +75°C Pins other than SCL and SDA SCL and SDA Conditions Ratings –0.3 to +7.0 –0.3 to VDD+0.3 –0.3 to +5.3 –0.3 to VDD +0.3 360 –20 to +75 –40 to +125 Unit V V V V mW °C °C Allowable Operating Ranges at Ta = 25°C Parameter Supply voltage Input high-level voltage Input low-level voltage QPSKI input voltage Symbol VDD VIH VIL VQPSKI Conditions Ratings min 4.5 0.75 VDD 0 0.7 0.9 typ 5.0 max 5.5 VDD 0.25 VDD 1.1 Unit V V V V DC Characteristics at Ta = –20 to +75°C, VDD = 4.5 to 5.5 V, GND = 0 V Parameter Current drain Symbol IDD VOH = VDD – 0.4 V ; VOH = VDD – 0.4 V, CMOS output pins:PHCNT, LOIN, MOD, DSTRO, FRM, ERR, CK2M, BSTRO, MUTO, DADO, REQ, SYCKO VOH = VCK5MH – 25 mV, CK5M VOL = 0.4 V ; CMOS output pins: PHCNT, LOIN, MOD, DSTRO, FRM, ERR, CK2M, BSTRO, MUTO, DADO, REQ, SYCKO VOL = 0.4 V, open drain output Pin 1: P0 to P7 VOL = 0.4 V, open drain output Pin 2: SDA VOL = VCK5ML + 25 mV, CK5M IOH = 30 µA, CK5M VI = VDD, Schmitt inputs: TSL, RST, TEST1, TEST2, BSTRI, DSTRI1, DSTRI2, DASL, MUTI, SCL, SDA, P0 to P7 VI = VSS, Schmitt inputs: TSL, RST, TEST1, TEST2, BSTRI, DSTRI1, DSTRI2, DASL, MUTI, SCL, SDA, P0 to P7 AOUTL and AOUTR –10 5.0 Conditions Ratings min typ 68 max 98 Unit mA IOH1 Output high-level current IOH2 IOL1 1.0 mA –350 –100 µA 1.0 mA Output low-level current 1 IOL2 IOL3 IOL4 1.0 4.0 100 236 295 350 354 10 mA mA µA mV µA Output amplitude level Input high-level current VCK5M IIH Input low-level current Output load resistance IIL RL µA kΩ D/A Converter Characteristics at Ta = –20 to +75°C, VDD = 4.5 to 5.5 V, GND = 0 V Parameter Resolution Total harmonic distortion Signal-to-noise ratio Crosstalk Full scale output voltage Symbol RES THD1 THD2 S/N C. T VFS 1 kHz 0 dB 1 kHz A mode, FS - 18 dB * 1 kHz B mode, FS - 18 dB * 1 kHz 0 dB * 1 kHz 0 dB * 2.8 Conditions Ratings min typ 16 0.08 0.05 105 95 3.0 3.2 max Unit Bits % % dB dB Vp-p Note: *Values when measured in the Sanyo evaluation board and with a QPSK modulated signal (1 kHz sine wave) input. No. 5691-6/9 LC7851E I2C Bus Interface at Ta = –20 to +75°C, VDD = 4.5 to 5.5 V, GND = 0 V Parameter SCL frequency Bus release time Start hold time SCL low time SCL high time Data hold time Data setup time Rise time Fall time Stop setup time Symbol fSCL TBUF THD STA TLOW THIGH THD DAT TSU DAT TR TF TSU STO 4.0 4.7 4.0 4.7 4.0 0 250 1000 300 Conditions Ratings min typ max 100 Unit kHz µs µs µs µs ns ns ns ns µs S: Start condition P: Stop condition Descrambler Interface at Ta = –20 to +75°C, VDD = 4.5 to 5.5 V, GND = 0 V Parameter Clock pulse width BSTRO pin output delay time DSTRO pin output delay time BSTRI and DSTRI1 two-pin input setup time Symbol TCK2M TBSDL TDSDL TBSST 10 Conditions Ratings min 244 15 15 typ max Unit ns ns ns ns Reset Timing at Power on at Ta = –20 to +75°C, VDD = 4.5 to 5.5 V, GND = 0 V Parameter Reset time Symbol TRST Conditions TSL pin high; The LC7851E must be used with the TSL pin (pin 13) high. Ratings min 200 typ max Unit ms The LC7851E must be reset with the following timing when power is first applied. Pin I/O Circuit Pin 30 Pin 31 Recommended Crystal Oscillator Constants Supplier Citizen Watch Co., Ltd. Oscillator element CSA-309 (22.909088 MHz) Cin/Cout 5pF (Cin = Cout) No. 5691-7/9 LC7851E Application Circuit Diagram No. 5691-8/9 LC7851E s No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. s Anyone purchasing any products described or contained herein for an above-mentioned use shall: Œ Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use:  Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. s Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of August, 1997. Specifications and information herein are subject to change without notice. No. 5691-9/9