LC78816MB

Ordering number : EN*4250C CMOS LSI LC78816MB, 78816MC 16-Bit D/A Converter for Use in Digital Audio Products Preliminaly Overview The LC78816MB and 78816MC are 16-bit CMOS D/A converters for use in digital audio products. They employ a dynamic level shift conversion technique that combines a resistor string (for the upper 9 bits), PWM (for the middle 3 bits), and level shifting (for the lower 4 bits). Package Dimensions unit: mm 3036B-MFP20 [LC78816MB, 78816MC] Features • Two’s complement data format • Two D/A converter channels built in (in-phase outputs) • Maximum conversion frequency of 400 kHz (support for 8 times oversampling) • Built-in output op amps • No deglitching circuit required • Si gate CMOS process (low power consumption) • 5 V single-voltage power supply • Low voltage (3.5 V) operation possible SANYO: DIP20 Specifications Absolute Maximum Ratings at Ta = 25°C Parameter Maximum power supply voltage Input voltage Output voltage Operating temperature Storage temperature Symbol VDD max VIN VOUT Topr Tstg Conditions Ratings –0.3 to +7.0 –0.3 to VDD + 0.3 –0.3 to VDD + 0.3 –30 to +75 –40 to +125 Unit V V V °C °C Allowable Operating Ranges Parameter Power supply voltage Reference voltage high Reference voltage low Operating temperature Symbol VDD VrefH VrefL Topr Conditions Ratings min 3.5 VDD – 0.3 0 –30 typ 5.0 max 5.5 VDD 0.3 +75 Unit V V V °C SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN 63096HA (OT)/D1694TH(OT)/61893JN No. 4250-1/11 LC78816MB, 78816MC DC Characteristics at Ta = –30 to +75°C, VDD = 3.5 to 5.5 V, VSS = 0 V Parameter Input high level voltage (1) Input low level voltage (1) Input high level voltage (2) Input low level voltage (2) Symbol VIH VIL VIH VIL Conditions Input pins other than SYSCLK Input pins other than SYSCLK The SYSCLK pin The SYSCLK pin 0.7 VDD 0.3 VDD Ratings min 2.2 0.8 typ max Unit V V V V AC Characteristics at Ta = –30 to +75°C, VDD = 3.5 to 5.5 V, VSS = 0 V Parameter Symbol Conditions Ratings min typ max Unit Clock pulse width Setup time Hold time tCW tBCW tDS tDH SYSCLK BCLK LRCK/WCLK DATAL DATAR 25 35 20 20 ns ns ns ns No. 4250-2/11 LC78816MB, 78816MC Electrical Characteristics (1) at Ta = 25°C, DVDD = AVDD = VrefH = 5.0 V, DGND = AGND = VrefL = 0.0 V Parameter Resolution Conversion frequency Total harmonic distortion Total harmonic distortion Dynamic range Cross talk Signal to noise ratio Full scale output voltage Power dissipation Output load resistance Symbol RES fs THD1 THD1 DR C·T S/N VFS Pd RL Pins 1 and 20 5 LC78816MB at 1 kHz, 0 dB LC78816MC at 1 kHz, 0 dB At 1 kHz, –60 dB At 1 kHz, 0 dB JIS-A 96 3.0 3.3 35 3.5 60 94 96 –85 Conditions Ratings min typ 16 400 0.05* 0.08 max Unit Bits kHz % % dB dB dB Vp-p mW kΩ Notes: *: Screened units Test circuit: based on the sample application circuit, with a sampling frequency (fs) of 88.2 kHz. Electrical Characteristics (2) at Ta = 25°C, DVDD = AVDD = VrefH = 5.0 V, DGND = AGND = VrefL = 0.0 V Parameter Resolution Conversion frequency Total harmonic distortion Total harmonic distortion Dynamic range Cross talk Signal to noise ratio Full scale output voltage Power dissipation Output load resistance Symbol RES fs THD1 THD1 DR C·T S/N VFS Pd RL Pins 1 and 20 15 LC78816MB at 1 kHz, 0 dB LC78816MC at 1 kHz, 0 dB At 1 kHz, –60 dB At 1 kHz, 0 dB JIS-A 96 2.0 2.3 10 2.5 20 92 94 –85 Conditions Ratings min typ 16 400 0.06* 0.09 max Unit Bits kHz % % dB dB dB Vp-p mW kΩ Notes: *: Screened units Test circuit: based on the sample application circuit, with a sampling frequency (fs) of 88.2 kHz. Pin Assignment No. 4250-3/11 LC78816MB, 78816MC Block Diagram Pin Functions Pin No. 1 2 3 4 5 Pin Name CH1OUT REFH VrefH AVDD LRCK/WCLK Channel 1 output pin (left channel) Reference voltage high level pin Normally connected to AGND through a capacitor. Reference voltage high level input pin Analog system power supply voltage pin LR clock and word clock input pin Used to generate the internal signal that latches the digital audio data (DATAL and DATAR). Digital audio data input pin Data is input from the MSB bit serially. When FSEL is low, channel 1 data is input. When FSEL is high, channel 1 and channel 2 data are input using time division. Digital audio data input pin Data is input from the MSB bit serially. When FSEL is low, channel 2 data is input. When FSEL is high, functions as the interface switching pin. Bit clock input pin This is the clock for reading in digital audio data bit serially. Also functions as the IC’s system clock when SYSCLK is fixed low or high. System clock input pin This is the system clock that drives the IC. However, in certain modes it is used as the interface switching pin. (See the timing charts.) Digital system power supply voltage pin Output pin for IC testing When low, digital audio data is input simultaneously from the DATAL and DATAR pins. When high, digital audio data is input from the DATAL pin in time division mode. Interface switching pins. (See the timing charts.) Digital system ground pin Reference voltage low level pin. Normally connected to AGND through a capacitor. Analog system ground pin Reference voltage low level input pin No connection Channel 2 output pin (right channel) Function and Operational Description 6 DATAL 7 DATAR 8 BCLK 9 10 11 12 13 14 15 16 17 18 19 20 SYSCLK DVDD TSTOUT FSEL MODE1 MODE2 DGND REFL AGND VrefL NC CH2OUT No. 4250-4/11 LC78816MB, 78816MC Operation (1) Input of digital audio data Digital audio data is a 16-bit serial signal in an MSB first two’s complement format. The 16-bit serial data is read into the IC from MSB on the rising edge of the BCLK signal. The LC78816MB and 78816MC can handle various interface types. See the timing charts for details. DSP ICs for CD players: See timing chart (1)-x when interfacing with the LC7868KE or the 7869E. (2) Converter operation (See Figure 1.) The LC78816MB and 78816MC have independent D/A converter circuits for channel 1 and channel 2. These D/A converters use a dynamic level shift conversion technique that combines resistor string (R-string DAC), PWM (pulse width modulation), and level shifting D/A converters. After latching, the 16-bit input digital audio data (D15 to D0) is sent to these separate D/A converters as follows: Upper 9 bits (D15 to D7): To the R-string DAC. Middle 3 bits (D6 to D4): To the PWM DAC. Lower 4 bits (D3 to D0): To the level shifting DAC. x R-string DAC The resistor string D/A converter consists of 512 (29) unit resistances (R) connected in series. The voltage applied at the terminals of this resistor string is divided into 512 equal divisions to form the 9-bit D/A converter outputs. The upper 9 bits of the input data value are used to select (using a switching circuit) two adjacent potentials, V1 and V2, from the divided voltages. These are output to the PWM DAC. The relationship between these two voltages is given by the following formula: V2 – V1 = (VH – VL)/512 y PWM DAC The PWM DAC is a 3-bit D/A converter that divides the interval between the two voltages, V1 and V2 output by the R-string DAC, into 8 using PWM (pulse width modulation). Either V1 or V2, depending on the value of the middle three bits of the data, is output to the CH1OUT (or CH2OUT) pin. SYSCLK is used for the PWM clock when timing chart (2)-y and (2)-z are used, and BCLK is used for all other timing charts. z Level Shift DAC Two variable resistors, VRH and VRL, are connected in series at the ends of the R-string DAC resistor string to implement a 4-bit D/A converter circuit. The variable resistors VRH and VRL operate as follows in response to the lower 4 bits of the data value. • Independent of the data value, the sum of the resistances (VRH + VRL) remains constant. • According to the data value, VRH and VRL vary in the range from 0 to 15R/128 (where R is the value of the resistors in the R-string DAC) in steps of R/128. As a result, the R-string DAC outputs V2 and V1 vary according to the lower 4 bits of the data in steps of ∆V/128 over a range 0 to 15 × ∆V/128 (where ∆V = (VH – VL)/512). No. 4250-5/11 LC78816MB, 78816MC D/A Conversion Technique Used in the LC78816MB and 78816MC Figure 1 D/A Conversion Technique Used in the LC78816MB and 78816MC Vref pins (See Figure 1.) The Vref pins that provide the reference voltages for the resistor string are normally set at VrefH = 5 V and VrefL = 0 V. Also, a capacitor of about 47 µF should be connected between REFH and AGND, and another between REFL and AGND. As a result of the built-in resistors RH and RL, the maximum output amplitude of the LC78816MB and 78816MC is in a range of 0.5 V (min) to 3.8 V (max) (3.3 Vp-p) for 0 dB playback. No. 4250-6/11 Timing Charts (1) For time division input of the CH1 and CH2 data (FSEL = high) (1)-x MODE1 = “L”, MODE2 = “L”, FSEL = “H” DATAR = “L” SYSCLK = “L” LC78816MB, 78816MC (1)-y MODE1 = “L”, MODE2 = “H”, FSEL = “H” No. 4250-7/11 When SYSCLK = “L”: “LRCK/WCLK1”, when “H”: “LRCK/WCLK2” When DATAR = “L”: “DATAL1”, when “H”: “DATAL2” (1)-z MODE1 = “H”, MODE2 = “L”, FSEL = “H” Timing Charts LC78816MB, 78816MC When SYSCLK = “L”: “LRCK/WCLK1”, when “H”: “LRCK/WCLK2” When DATAR = “L”: “DATAL1”, when “H”: “DATAL2” No. 4250-8/11 (1)-{ MODE1 = “H”, MODE2 = “H”, FSEL = “H” Timing Charts When SYSCLK = “L”: “LRCK/WCLK1”, when “H”: “LRCK/WCLK2” When DATAR = “L”: “DATAL1”, when “H”: “DATAL2” LC78816MB, 78816MC (2) For simultaneous input of CH1 and CH2 data (FSEL = low) (2)-x MODE1 = “L”, MODE2 = “L”, FSEL = “L” No. 4250-9/11 When SYSCLK = “L”: “LRCK/WCLK1”, when “H”: “LRCK/WCLK2” (2)-y MODE1 = “L”, MODE2 = “H”, FSEL = “L” Timing Charts LC78816MB, 78816MC (2)-z MODE1 = “H”, MODE2 = “H”, FSEL = “L” No. 4250-10/11 LC78816MB, 78816MC Sample Application Circuit Notes: 1. DVDD and DGND must be connected to the digital system power supply, and AVDD and AGND to the analog system power supply. 2. Use a low impedance high stability power supply (a unit equivalent to a commercial three terminal regulator) for VDD and VrefH. 3. Since latchup is possible if there is a discrepancy between the power supply rise times for pin 4 (AVDD) and pin 10 (DVDD), design the system so that there is no time lag between the pin 4 and pin 10 power application times. s No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. s Anyone purchasing any products described or contained herein for an above-mentioned use shall: Œ Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use:  Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. s Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. T his catalog provides information as of December, 1997. Specifications and information herein are subject to change without notice. No. 4250-11/11