LC78856V

Ordering number : EN*5128A CMOS LSI LC78856M, 78856V Built-in Digital Filter D/A Converters for Digital Audio Preliminaly Overview The LC78856M and LC78856V are ∑∆-type digital-audio D/A converter circuits with built-in digital filters. Package Dimensions unit: mm 3091A-MFP28 [LC78856M] Features • • • • • • • • 8× oversampling digital filter Digital de-emphasis (supports fs = 44.1 kHz) Soft muting Double speed support Support for a 384fs system clock PWM outputs 5 V single-voltage power supply Si-gate CMOS process SANYO: MFP28 unit: mm 3191-SSOP30 [LC78856V] SANYO: SSOP30 Specifications Absolute Maximum Ratings at Ta = 25°C Parameter Maximum supply voltage Maximum input voltage Maximum output voltage Operating temperature Storage temperature Symbol VDD max VIN max VOUT max Topr Tstg Conditions Ratings –0.3 to +7.0 –0.3 to VDD + 0.3 –0.3 to VDD + 0.3 –30 to +75 –40 to +125 Unit V V V °C °C SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN 53096HA (OT)/62095HA (OT) No. 5128-1/8 LC78856M, 78856V Allowable Operating Ranges at Ta = –30 to +75°C Parameter Supply voltage Input voltage Symbol VDD VIN Conditions Ratings min 3.0 0 typ max 5.5 VDD Unit V V DC Characteristics at Ta = –30 to +75°C, VDD = 4.5 to 5.5 V, VSS = 0 V Parameter Input high-level voltage (1) Input low-level voltage (1) Input high-level voltage (2) Input low-level voltage (2) Output high-level voltage Output low-level voltage Power dissipation Symbol VIH1 VIL1 VIH2 VIL2 VOH VOL Pd The XIN pin The XIN pin Pins other than the XIN pin Pins other than the XIN pin IOH = –1 µA IOL = 1 µA VDD = 5.0 V 140 VDD – 0.1 0.1 200 2.2 0.8 Conditions Ratings min 0.7 VDD 0.3 VDD typ max Unit V V V V V V mW DC Characteristics at Ta = –30 to +75°C, VDD = 4.5 to 5.5 V, VSS = 0 V Parameter Oscillator frequency BCLK frequency BCLK pulse width Data setup time Data hold time LRCK setup time LRCK hold time Symbol fX fBCX tWB tDS tDH tLS tLH 100 20 20 50 50 Conditions Ratings min typ 16.9 max 18.5 2.4 Unit MHz MHz ns ns ns ns ns Timing Chart Analog Characteristics at Ta = 25°C, VDD = 5.0 V Parameter Total harmonic distortion Signal-to-noise ratio Crosstalk Dynamic range Symbol THD + N S/N CT DR f = 1 kHz, 0 dB JIS-A f = 1 kHz, 0 dB JIS-A Conditions Ratings min typ 0.005 100 98 94 max Unit % dB dB dB No. 5128-2/8 LC78856M, 78856V Block Diagram Filter Characteristics Standard Speed (de-emphasis off) Double Speed (de-emphasis off) No. 5128-3/8 LC78856M, 78856V Pin Assignments No. 5128-4/8 LC78856M, 78856V Pin Functions SSOP 1 2 3 4 5 6 7 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 MFP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Symbol RSTB CNT1 CNT2 CNT3 BCLK LRCK DATA MODE CKO XVDD XIN XOUT XGND DGND MRO TEST AVDD4 OUTRA AGND2 OUTRB AVDD3 AVDD2 OUTLB AGND1 OUTLA AVDD1 MLO DVDD Function Reset input (A low-level input resets the LSI internal circuits.) Emphasis on/off switching input Standard speed/double speed switching input Soft mute input Bit clock input LR clock input Digital audio data input Input format setting Clock output Oscillator amplifier power supply Oscillator amplifier input Oscillator amplifier output Oscillator amplifier ground Digital system ground Right channel mute signal output Test pin (Must be tied low in normal operation.) Analog system power supply Right channel output A Analog system ground Right channel output B Analog system power supply Analog system power supply Left channel output B Analog system ground Left channel output A Analog system power supply Left channel mute signal output Digital system power supply Operating Description The LC78856M and LC78856V internal circuits can be roughly divided into the digital filter block and the 1-bit D/A converter block. [Digital Filter Block] 1. Standard Speed The LC78856M and LC78856V implements 8× oversampling using three FIR filters: a 43rd-order filter, an 11thorder filter, and a 3rd-order filter. A 1st-order IIR filter is used for de-emphasis. 2. Double Speed Double-speed playback is used, for example, for dubbing CDs to audio tape at double speed. Here, the same frequency is used for XIN, but BCLK, LRCK and DATA are input at twice the rates used in standard-speed playback. After de-emphasis is applied with a 1st-order IIR filter, the signal is 4× oversampled using a 43rd-order FIR filter and a 3rd-order FIR filter. No. 5128-5/8 LC78856M, 78856V 3. One-Bit D/A Converter Block The 1-bit D/A converter accepts 8fs data input and outputs a 384fs 1-bit data stream. LC78856M/V Inputs 1. Input Data Format • Format 1 (MODE = high) • Format 2 (MODE = low) 2. Control Signals (CNT1 to CNT3) Symbol CNT1 CNT2 CNT3 Function Emphasis switching Standard speed/double speed Soft mute L Off Standard speed Off H On Double speed On 3. Initialization The LC78856M and LC78856V requires initialization when power is first applied and when settings are changed. The LC78856M and LC78856V is initialized by setting the RSTB pin low. The length of the low-level period must extend 1 µs beyond the point where the XIN input is applied. When RSTB is low, all digital filter and noise shaper internal data is set to 0, and the D/A converter outputs an analog 0. No. 5128-6/8 LC78856M, 78856V LC78856M/V Outputs 1. CKO CKO outputs a clock signal with the same frequency as the signal input to the XIN pin. 2. MLO, MRO These pins output a high level when either the attenuator coefficient has become 0, or when the corresponding channel data has been 0 for 213 or more cycles. 3. OUTLA, OUTLB, OUTRA, OUTRB These four pins produce outputs in synchronization with the XIN clock. High-precision analog signals can be acquired by differentially amplifying the output signals and passing that result through an LPF. The figure below shows a sample circuit structure. Sample Output Circuit Structure No. 5128-7/8 LC78856M, 78856V Sample Application Circuit s No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. s Anyone purchasing any products described or contained herein for an above-mentioned use shall: Œ Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use:  Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. s Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of December, 1997. Specifications and information herein are subject to change without notice. No. 5128-8/8