LC7930NW

Ordering number: EN2778C CMOS LSI LC7930N, 7930NW LCD Drivers Overview The LC7930N, 7930NW are CMOS LSIs which incorporate 20-bit shift register, latch, and two sets of 20 LCD drivers. They also have two switching pins: one of them (channel 2) can be used as a scan-line driver (back plate) and the other (channel 1) as a segment driver. They are optimal for LCD interface with microcontroller (4 or 8 bits) or dot matrix controller circuit incorporating character generator. Package Dimensions unit : mm 3055A-QFP60C [LC7930N] Features . Two channels of 20 output segment drivers . The configuration of 20 output segment drivers + 20 terminal drivers available . scanningdata to connect with the microcontroller and three A series . control signals in series for large display . Able to be connected shift register can be shifted in the Built-in bidirectional easy . direction that makes wiringOperating temperature: Operating supply voltage/ to 5.5 to +75°C . V = 4.5current V / ToprI = –201.0 mA max Operating drain : = (Logic LCD = 1 kHz) . Package= :400 kHz,Flat LC7930N : QIP60 Pin 60 DD DD SANYO : QIP60C unit : mm 3190-SQFP64 [LC7930NW] Pin 64 Flat LC7930NW : SQFP64 SANYO : SQFP64 SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN 13097HA(II)/12593JN/6031JN/6218TA,TS No.2778-1/7 LC7930N, 7930NW Specifications Absolute Maximum Ratings at Ta = 25 ± 2°C Parameter Maximum supply voltage Maximum input voltage Maximum output voltage Allowable power dissipation Operating temperature Storage temperature Symbol VDD max VEE max VI max VO max Pd max Topr Tstg V1, V2, V3, V4, V5, V6 Output transistor OFF, Y1 to Y40 Conditions Ratings –0.3 to +7.0 VDD–13.5 to VDD+0.3 –0.3 to VDD+0.3 VEE to VDD+0.3 –0.3 to VDD+0.3 VEE to VDD+0.3 100 –20 to +75 –55 to +125 Unit V V V V V V mW °C °C Note : Don’t soak the whole of IC into the tank filled with melted solder for soldering Allowable Operating Conditions at Ta = –20 to +75°C, VSS = 0 V, VEE = –4 to –6 V Parameter Supply voltage High-level input voltage Low-level input voltage Shift frequency High-level clock width Low-level clock width Data setup time Clock setup time Clock transition time Data retention time Symbol VDD VIH VIL fCL tCWH tCWL tSU tSL tLS tct tDH Conditions VDD Note (1) Note (1) CLKSR CLKSR, CLKLA CLKSR LDATA1, LDATA2, RDATA1, RDATA2 CLKSR, CLKLA CLKSR, CLKLA CLKSR, CLKLA LDATA1, LDATA2, RDATA1, RDATA2 min 4.5 0.7VDD VSS 800 800 300 CLKSR → CLKLA CLKLA → CLKSR 500 500 200 300 typ max 5.5 VDD 0.3VDD 400 Unit V V V kHz ns ns ns ns ns ns ns Electirical Characteristics at Ta = –20 to +75°C, VDD = +5 V ± 10%, VSS = 0 V, VEE = –4 to –6 V Parameter Input leakage current High-level output voltage Low-level output voltage Vi to Yj voltage down Symbol IIH IIL VOH VOL Vd1 Vd2 IVH Vi quiescent current IVL IDD Supply current IEE Output propagation delay time tPD VEE LDATA1, LDATA2, RDATA1, RDATA2 V1 to V6 VDD Note (1) Note (1) LDATA1, LDATA2, RDATA1, RDATA2 LDATA1, LDATA2, RDATA1, RDATA2 Y1 to Y40 Note (2) Y1 to Y40 Note (2) V1 to V6 Conditions Vin = VDD Vin = VSS IOH = –0.4 mA IOL = 0.4 mA Ion = 100 µA, single output Ion = 50 µA, all outputs Open output pins Vin = VDD Open output pins Vin = VEE Open output pins CLKSR = 400 kHz Open output pins M = 1 kHz CL = 15 pF min –5 VDD–0.4 0.4 1.1 1.5 10 –10 1.0 10 500 typ max 5 Unit µA µA V V V V µA µA mA µA ns Note (1): Applied to the pins; CLKSR, CLKLA, LDATA1, RDATA1, LDATA2, RDATA2, M, L/R1, L/R2, CH2-BP (2): The equivalent circuit between Vi to Yj (i = 1 to 6, j = 1 to 40) No.2778-2/7 LC7930N, 7930NW Switching Waveforms Internal Equivalent Circuit LCD driver (Channel 1) 20-bit latch 20-bit bidirectional shift register 20-bit bidirectional shift register 20-bit latch LCD driver (Channel 2) No.2778-3/7 LC7930N, 7930NW Pin Assignment [LC7930N] Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 [LC7930NW] Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 Name V5 V4 V3 V2 V1 CH2-BP L/R2 L/R1 M RDATA2 LDATA2 RDATA1 LDATA1 VSS CLKSR CLKLA VEE Y1 Y2 Y3 Y4 Y5 Input/Output Input Input Input Input Input Input Input Input Input Input/Output Input/OUtput Input/Output Input/Output — Input Input — Output Output Output Output Output Number 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Name Y6 VDD Y7 Y8 Y11 Y10 Y9 Y12 Y13 N.C. Y14 Y15 Y16 Y17 Y18 Y19 Y20 Y21 Y22 Y23 Y24 Y25 Input/Output Output — Output Output Output Output Output Output Output — Output Output Output Output Output Output Output Output Output Output Output Output Number 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Name Y26 Y27 Y28 Y29 N.C. Y34 Y33 Y32 Y31 Y30 N.C. N.C. Y35 Y36 Y37 Y38 Y39 Y40 V6 N.C. Input/Output Output Output Output Output — Output Output Output Output Output — — Output Output Output Output Output Output Input — Name Y30 Y31 Y32 Y33 Y34 Y29 Y28 Y27 Y26 Y25 Y24 Y23 Y22 Y21 Y20 Y19 Y18 Y17 Y16 Y15 Input/Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Number 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Name Y14 Y13 Y12 Y9 Y10 Y11 Y8 Y7 VDD Y6 Y5 Y4 Y3 Y2 Y1 VEE CLKLA CLKSR VSS LDATA1 Input/Output Output Output Output Output Output Output Output Output — Output Output Output Output Output Output — Input Input — Input/Output Number 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 Name RDATA1 LDATA2 RDATA2 N.C. M L/R1 L/R2 CH2-BP V1 V2 V3 V4 V5 V6 Y40 Y39 Y38 Y37 Y36 Y35 Input/Output Input/Output Input/Output Input/Output — Input Input Input Input Input Input Input Input Input Input Output Output Output Output Output Output No.2778-4/7 LC7930N, 7930NW Pin Descriptions Pin Name VDD VSS VEE Y1 to Y20 Y21 to Y40 V1, V2 V3, V4 V5, V6 L/R1 Logic circuitry power supply (+5 V ±10%) 0V LCD driver power supply (–4 to –6 V) Channel 1 LCD driver output pins Channel 2 LCD driver output pins Reference voltage for selected driver outputs Reference voltage for non-selected driver outputs (channel 1) Reference voltage for non-selected driver outputs (channel 2) Shift direction for channel 1 shift register L/R1 High-level Low-level L/R2 LDATA1 Output Input RDATA1 Input Output Function Shift direction for channel 2 shift register L/R2 High-level Low-level LDATA2 Output Input RDATA2 Input Output LDATA1 RDATA1 LDATA2 RDATA2 M CLKLA CLKSR CH2-BP Serial data input/output pins for channel 1 shift register Serial data input/output pins for channel 2 shift register Switching clock signal for LCD driver. Latches channael 1 data on the falling edge. This also will latch channel 2 data on the falling edge if CH2-BP is low. Shift channel 1 data on the falling edge. This also will shift channel 2 data on the falling edge if CH2-BP is low. Switches the mode of channel 2. Exchanges the latch signal for the shift signal of channel 2 and invert the M signal. Channel 2, then, can be used as a scan-line driver. Channel 2 Latch CLKSR CLKLA Shift CLKLA CLKSR CH2-BP High Low M M M For scan-line driver For signal line driver Functional Description LC7930N, LC7930NW are serial data transfer type LCD drivers. Data inputted serially from the data pin is shifted successively by the synchronizing clock (CLKSR) and latched by the latch clock (CLKLA) when the all data are shifted. . Segment terminal . When CH2-BP goes to low, the data of channel 1 and channel 2 are shifted at the falling edge of CLKSR, and then latched at the falling edge of the CLKLA. The reference pulse will be switched to selected or unselected due to the latched data. Scan terminal When CH2-BP goes to high, the data of channel 2 is shifted at the rising edge of CLKLA, and then latched at the rising edge of the CLKSR. When FLM signal, as a data, is inputted, the output will be scan terminal drive mode. Continued on next page. No.2778-5/7 LC7930N, 7930NW Continued from preceding page. (1) Waveform Diagrams for Segment Drive Mode (CH2 – BP = ‘‘L’’) (FLM) M CLKLA(latch) CLKSR(shift) Serial input data Latch outputs (Y1 to Y40) (2) Waveform Diagrams for Scan-Line/Segment Drive Mode (CH2–BP = ‘‘H’’) LDATA2/RDATA2 (FLM) M CLKLA (shift) CLKSR(latch) Y21 to Y40 Table 1. LCD Driver Output Voltages (V1 to V6) for Y1 to Y40 CH2–BP Serial Input Data 1 (selected) 0 (un-selected) 1 Low level (2) 0 M H L H L H L H L Output Y1 to Y20 V1 V2 V3 V4 V1 V2 V3 V4 Y21 to Y40 V2 V1 V6 V5 V1 V2 V5 V6 High level (1) No.2778-6/7 LC7930N, 7930NW LCD Interface Examples (Although the LCD divided voltage generator circuit is not shown here.) (1) 40-segment bar-graph display (static) 4-bit microcontroller Output port 40 lines 4 lines (2) 6-digit, 7-segment + sign display. (1/3 duty cycle, 1/3 voltage bias) 3 lines Drive controller Output port 4-bit microprocessor 3 lines 5 lines 20 lines (3 lines/1 digit) (3) 20 × 60 pixel graphic display. (1/20 duty cycle, 1/5 voltage bias) 20 lines Drive controller 20 × 60 dots 20 lines 8-bit microprocessor or dedicated controller 40 lines 3 lines 3 lines 3 lines No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. Anyone purchasing any products described or contained herein for an above-mentioned use shall: 1 Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: 2 Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of January, 1997. Specifications and information herein are subject to change without notice. No.2778-7/7