LC7940KD

Ordering number : ENA0573 LC7940KD LC7941KDR Overview CMOS IC Dot-Matrix LCD Drivers The LC7940KD and LC7941KDR are segment driver LSIs for driving large, dot-matrix LCD displays. They read 4-bit parallel or serial input, display data from a controller into an 80-bit latch, and then generate LCD drive signals corresponding to that data. The LC7940KD and LC7941KDR feature mirror-image pin assignments, allowing them to be used together to increase component density. They are designed to be used with the LC7942KD (QIP80D) common driver to drive large LCD panels. Features • 80 built-in LCD display drive circuits • 1/8 to 1/128 display duty cycle • Serial or 4-bit parallel data input • Chip disable for low power dissipation for large-sized panels • Bias supply voltage can be supplied externally • Operating supply voltage and ambient temperature VDD (logic block): 2.7 to 5.5V/-20 to +85°C VDD-VEE (LCD block): 8 to 20V/-20 to +85°C • CMOS process • Package: QIP100D(LC7940KD)/QIP100DR(LC7941KDR) Any and all SANYO Semiconductor products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft's control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO Semiconductor representative nearest you before usingany SANYO Semiconductor products described or contained herein in such applications. SANYO Semiconductor assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor products described or contained herein. N2206HKIM B8-8529 No.A0573-1/13 LC7940KD / LC7941KDR Package Dimensions unit: mm (typ) 3180 [LC7940KD] 23.2 20.0 0.825 1.6 0.3 51 50 0.15 0.575 80 81 0.65 17.2 14.0 0.65 1.6 2.15 21.6 0.8 SANYO : QIP100D(14X20) Package Dimensions unit: mm (typ) 3329 [LC7941KDR] 23.2 80 81 51 50 100 1 0.65 (0.58) 0.3 30 31 0.15 2.45MAX 0.1 (2.15) SANYO : QIP100DR(14X20) 14.0 17.2 0.8 20.0 0.8 1 30 2.45max 100 31 15.6 No.A0573-2/13 LC7940KD / LC7941KDR Pin Assignment O72 O71 O70 O69 O68 O67 O66 O65 O64 O63 O62 O61 O60 O80 O79 O78 O77 O76 O75 O74 O73 O59 O58 O57 O56 O55 O54 O53 O52 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 NC CDO NC DISPOFF P/S VSS VEE V4 V3 NC VDD V1 M DI1 DI2 DI3 SDI LOAD CDI CP 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 123456 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 O50 O49 O48 O47 O46 O45 O44 O43 O42 O41 O40 O39 O38 O37 O36 O35 O34 O33 O32 O31 LC7940KD 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 O9 O10 O11 O12 O13 O14 O15 O16 O17 O18 O19 O20 O21 O1 O2 O3 O4 O5 O6 O7 O8 O22 O23 O24 O25 O26 O27 O28 O29 O26 O27 O28 O29 O30 Top view O30 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 O7 O8 O9 O10 O11 O12 O13 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 CP CDI LOAD SDI DI3 DI2 DI1 M V1 VDD NC V3 V4 VEE VSS P/S DISPOFF NC CDO NC 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 123456 O80 O79 O78 O77 O31 O32 O33 O34 O35 O36 O37 O38 O39 O40 O41 O42 O43 O44 O45 O46 O47 O48 O49 O50 LC7941KDR 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 O67 O66 O65 O64 O63 O62 O61 O60 O72 O71 O70 O69 O68 O59 O58 O57 O56 O55 O54 O53 O52 O51 Top view No.A0573-3/13 O76 O75 O74 O73 O14 O15 O16 O17 O18 O19 O20 O21 O22 O23 O24 O25 O1 O2 O3 O4 O5 O6 O51 LC7940KD / LC7941KDR Block Diagram O79 O80 O1 O2 V1 V3 V4 VEE 80 Level Shifter (80 bits) M 80 2nd Latch (80 bits) 80 1st Latch (80 bits) 4 SDI DI3 DI2 DI1 4 bits Data Bus Interface 20 Address Decoder DISPOFF 4 Level LCD Drive Circuit (80 bits) VDD VSS O3 Address Counter (7bits) P/S SER/PAR Control Chip Disable & Latch Control CDO CDI CP LOAD No.A0573-4/13 LC7940KD / LC7941KDR Pin Function Pin No LC7940KD 91 86 87 92 89 88 100 99 98 97 96 LC7941KDR 90 95 94 89 92 93 81 82 83 84 85 VDD VSS VEE V1 V3 V4 CP CDI LOAD SDI DI3 I I I I I Supply Supply LCD panel drive voltage supplies VDD-VSS is the logic supply. VDD-VEE is the LCD supply. LCD panel drive voltage supplies V1 and VEE are selected levels. V3 and V4 are not-selected levels. Display data input clock (falling edge trigger). Chip disable. Data is read in When LOW, and not read in When HIGH. Display data latch clock (falling edge trigger). On the falling edge, the LCD drive signals set by the display data are output. Serial data input. 4-bit parallel data input pins. Data input SDI 95 86 DI2 I DI3 DI2 DI1 94 87 DI1 I O4 O3 O2 O1 LCD driver output O8 O7 O6 O5 → O80 O79 O78 O77 Symbol I/O Function In serial data input mode, DI1 to DI3 should all be tied HIGH or LOW. 93 85 82 88 96 99 M P/S CDO I I O LCD panel drive voltage output alternation control signal. Data input mode select. 4-bit parallel input when HIGH, and serial input when LOW. Cascade connection pin for extension segment drivers. Data is read out when HIGH. Goes LOW after data is read out. Connected to the CDI input of the next chip. 1 to 80 80 to 1 O1 to O80 O LCD drive outputs. The output drive level is determined by the display data, M signal and DISPOFF input as shown below. M L L H H * Q L H L H * DISPOFF H H H H L Output V3 V1 V4 VEE V1 Note* don’t care (tied HIGH or LOW) 84 97 DISPOFF I O1 to O80 output control input pin. When LOW, V1 is output on the O1 to O80 outputs. See the truth table. 81 83 90 91 98 100 NC NC NC No connection. No.A0573-5/13 LC7940KD / LC7941KDR Specifications Absolute Maximum Ratings at Ta=25±2°C, VSS = 0V Parameter Maximum supply voltage (logic) Maximum supply voltage (LCD) Maximum input voltage Operating temperature range Storage temperature range Symbol VDD max VDD-VEE max VI max Topr Tstg *1 Conditions Ratings -0.3 to +7.0 0 to 22 -0.3 to VDD +0.3 -20 to +85 -40 to +125 Unit V V V °C °C Note *1 The following relations between elements should be maintained: VDD≥V1>V3>V4>VEE, VDD-V3≤7V, V4-VEE≤7V Allowable Operating Ranges at Ta = -20 to 85°C, VSS = 0V Parameter Supply voltage (logic) Supply voltage (LCD) Input high level voltage Input low level voltage CP Shift clock frequency CP pulse width LOAD pulse width DIn and SDI to CP setup time DIn and SDI to CP hold time CP to LOAD time Symbol VDD VDD-VEE VIH VIL fCP tWC tWL tSETUP tHOLD tCL1 tCL2 LOAD to CP time CP rise time CP fall time LOAD rise time LOAD fall time tLC tR tF tRL tFL *2, 3 CP, CDI, DI1 to DI3, M, SDI, P/S, DISPOFF, and LOAD CP, CDI, DI1 to DI3, M, SDI, P/S, DISPOFF, and LOAD CP CP LOAD DIn and SDI to CP DIn and SDI to CP CP to LOAD CP to LOAD LOAD to CP CP CP LOAD LOAD Conditions min 2.7 8 0.8VDD 100 100 80 80 0 100 100 Ratings typ 50 50 50 50 0.2VDD 3.3 max 5.5 20 V V V V MHz ns ns ns ns ns ns ns ns ns ns ns Unit Note *2 The following relations between elements should be maintained: VDD≥V1>V3>V4>VEE, VDD-V3≤7V, V4-VEE≤7V *3 When the power is turned on, either the logic system power must be turned on before the LCD drive system power or else they must both be turned on at the same time. When the power is turned off, either the LCD drive system power must be turned off before the logic system power, or else both must be turned off at the same time. No.A0573-6/13 LC7940KD / LC7941KDR Electrical Characteristics at Ta = 25±2°C, VDD = 2.7 to 5.5V Parameter Input high level current Input low level current Output high level voltage Output low level voltage Driver on resistance Standby current drain Symbol IIH IIL VOH VOL RON IST ISS *5 IEE *6 Conditions min VIN = VDD: LOAD, CP, CDI, P/S, DI1 to DI3, SDI, M, and DISPOFF VIN = VSS: LOAD, CP, CDI, P/S, DI1 to DI3, SDI, M, and DISPOFF IOH = -400µA: CDO IOL = 400µA: CDO VDD-VEE = 18V, |VDE-Vo| = 0.25V *4 CDI = VDD, VDD-VEE = 18V, CP = 3.3MHz, Output unloaded: VSS Operating current drain VDD-VEE = 18V, CP = 3.3MHz, LOAD = 5.156kHz M = 52Hz: VSS VDD-VEE = 18V, CP = 3.3MHz, LOAD = 5.156kHz M = 52Hz: VEE -1 VDD-0.4 Ratings typ 0.7 0.4 2 200 1.0 0.1 max 1 µA µA V V kΩ µA mA mA Unit Note *4 VDE = one of V1, V3, V4 or VEE. V1 = VDD, V3 = 9/11(VDD-VEE), V4 = 2/11(VDD-VEE) *5 ISS is the current flowing from VDD-VSS. *6 IEE is the current flowing from VDD-VEE Switching Characteristics at Ta = 25±2°C, VSS = 0V, VDD = 2.7 to 5.5V Parameter Output delay time Symbol tD CL=30pF: CDO Conditions min Ratings typ max 200 ns Unit Switching Characteristics Diagram tR tWC tF tWC 0.8VDD CP 0.2VDD tSETUP tHOLD 0.8VDD 0.2VDD SDI DI1 to 3 0.8VDD 0.2VDD tCL(1) tRL tCL(2) tFL tLC LOAD tWL tD tD 0.8VDD CDO 0.2VDD No.A0573-7/13 Controller FLM M M LC7942KD CP #1 O64 DIO64 V1 V2 V5 VEE 100 LCD Panel (240×100 Pixels) 4 DIO1 O1 Application Notes LCD Panel1 LOAD CP Serial Data VDD 240 239 161 160 159 •••• •••• •••• DIO1 O1 M LC7942KD •••• V1 CP #2 O36 2 1 80 79 81 V2 CDI LC7940KD-#3 4 M 4 V1 V3 V4 VEE 4 V1 V3 V4 VEE CDO 6 + V1 V2 V5 VEE •••• CDI LC7940KD-#2 CDO LC7940KD-#1 LC7940KD / LC7941KDR R + V3 7R + V4 M V1 V3 V4 VEE M R V5 + R VEE LOAD CP Serial Data •••• R CDI V1 V3 V4 VEE LOAD CP SDI No.A0573-8/13 2 4 2 4 2 4 2 4 Controller M V1 V3 V4 VEE 4bit Data LC7941KDR-#8 LC7941KDR-#2 CDO •••• CP LOAD 4bit Data O1 CDI LC7941KDR-#1 O80 Application Notes LCD Panel2 M M DIO1 O1 LOAD 100 LCD Panel (640×200 Pixels) O64 CP LC7942KD-#1 CP 4bit Data DIO64 VDD M DIO1 O1 V1 CP O36 LC7942KD-#2 O80 CDO LC7940KD-#8 LC7940KD-#2 •••• •••• •••• •••• LC7940KD / LC7941KDR R V2 + R + 4 V1 V3 V4 VEE 2 4 4 V3 6 V1 V2 V5 VEE 4 M 7R + V4 R V5 + 2 4 R No.A0573-9/13 4 VEE Power supply circuit •••• •••• •••• FLM O1 LC7940KD-#1 4bit Data V1 V3 V4 VEE CP LOAD 2 4 2 CDI 4 LC7940KD / LC7941KDR 100×240-Pixel LCD Panel Application A100×240-Pixel LCD Panel requires the following drivers. • 3×LC7940KD (or LC7941KDR) drivers • 2×LC7942KD drivers An example using 1/100 duty cycle is shown below. 1,79 Frame signal (m, n): Pixel address Segment line (n) Common line (m) O1 1 ,1 2 ,1 1 ,2 2 ,2 DIO1 RS/LS O2 LC7942KD ∼ 1,79 1,80 1,81 1,82 ∼ 1,160 1,161 ∼ 1,240 2,240 #1 CP M O63 LCD Panel (100×240 Pixels) 63 ,1 64 ,1 65 ,1 66 ,1 ∼ 63 ,2 64 ,2 65 ,2 66 ,2 ∼ ∼ ∼ ∼ ∼ DIO64 O64 DIO1 O1 64,80 65,80 64,81 65,81 ∼ ∼ ∼ 64,160 64,161 65,160 65,161 ∼ ∼ ∼ 64,240 65,240 RS/LS O2 LC7942KD #2 CP M O36 DIO64 O37 to 64 are open. 100,1 CDI P/S CP LOAD M LOAD Alternating signal Data latch clock Serial data (1) The LC7942KD chips are cascaded by connecting DIO64 on chip 1 to DIO1 on chip 2. For a 100-bit shift register, O37 to O64 on chip 2 are left open. (2) The LC7940KD (or LC7941KDR) chips are cascaded by connecting CDO on chip 1 to CDI on chip 2, and CDO on chip 2 to CDI on chip 3. CDI on chip 1 is tied to GND, and CDO on chop 3 is not used. This configulation allows the input of 240-bit serial data. Data shift clock P/S DI1 DI2 DI3 SDI SDI DI1 DI2 DI3 DI1 DI2 DI3 CP M CP LOAD M No.A0573-10/13 SDI P/S ∼ O1 100,2 O2 O79 LC7940KD (LC7941KDR) #1 ∼ ∼ 100,79 100,80 100,81 100,82 ∼ O80 CDO ∼ ∼ O1 ∼ ∼ 100,160 100,161 ∼ O1 100,240 ∼ O2 O80 LC7940KD CDI (LC7941KDR) #2 CDO LC7940KD O80 (LC7941KDR) CDO CDI #3 LC7940KD / LC7941KDR 100×240-pixel LCD Panel Timing Diagram M LOAD CP SDI 1,1 1,2 ∼ 1,79 1,80 1,81 ∼ 1,160 1,161 ∼ 1,240 #1 CDO #2 #3 Chip 1 data read 1 line (240 bits) Chip 2 data read Chip 3 data read M LOAD CP SDI 1,1 1,2 ∼ 1,239 1,240 2,1 ∼ 2,240 3,1 ∼ 100,240 1st line data read 1 frame (100×240 bits) M 2nd line data read #1 DIO1 LOAD O1 1,1 2,1 ∼ ∼ ∼ ∼ ∼ ∼ ∼ 98,1 99,1 100,1 1,1 ∼ ∼ ∼ ∼ ∼ ∼ ∼ 99,1 100,1 #1 O2 1,2 2,2 98,2 99,2 100,2 1,2 99,2 100,2 LCD driver output data O80 ∼ 1,80 2,80 O1 1,81 2,81 98,80 99,80 100,80 1,80 99,80 100,80 98,81 99,81 100,81 1,81 99,81 100,81 ∼ O80 1,160 2,160 98,160 99,160 100,160 1,160 99,160 100,160 O1 1,161 2,161 98,161 99,161 100,161 1,161 99,161 100,161 #2 ∼ O80 1,240 2,240 #3 98,240 99,240 100,240 1,240 99,240 100,240 No.A0573-11/13 LC7940KD / LC7941KDR Segment Data Not Multiples of 4 Example. LCD Panel (100×230 pixels) ∼ O1 • • • • • O80 LC7940KD #1 ∼ O1 • • • • • O80 LC7940KD #2 ∼ O1 • • • • • O70 LC7940KD #3 LOAD SDI m,1 m,2 ∼ ,228 m,229 m,230 m+1,1 m+1,2 ,228 m+1,229 m+1,230 If this timing data is sent, data elements (m, 229), (m, 230), (m+1, 229),(m+1, 230)… will not appear in the output (O69 and O70 on chip 3). This is because the LC7940KD (or LC7941KDR) converts serial/parallel data in 4-bit units, which also decrease power dissipation. For data that is not a multiple of 4, like 230, the following scheme is used. LOAD SDI m,1 m,2 ∼ ,228 m,229 m,230 m,231 m,232 Valid display data Dummy data Multiple of 4 In this case, (m, 231) is output on O71 on chip 3, and (m, 232) on O72 on chip 3. However, these outputs are not connected to the panel and are, therefore, invalid. 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