LC83025

Ordering number : EN4977A CMOS LSI LC83025E Digital Signal Processor for Karaoke Products Overview The LC83025E is a special-purpose karaoke DSP that implements the signal processing required by karaoke systems, including pitch shift, microphone echo, voice muting and simple surround, with only a single 256Kb external DRAM. Since the LC83025E includes built-in A/D and D/A converters, it can also handle analog inputs and outputs in addition to digital inputs and outputs. The LC83025E uses serial transfer of coefficient data from a microcontroller to handle changes in functions and characteristics required for each application. • Features • Applications — Pitch shift The LC83025E can shift the music pitch or the microphone pitch by ±15 steps in 1/4 interval steps, or ±1 octave in scale tone steps according to command data sent from the microcontroller. Furthermore, the pitch can be changed up to ±1 octave in arbitrary steps by setting internal coefficients. — Microphone echo The LC83025E implements echo processing for the signal input from the microphone A/D converter. The amount of echo, the delay time and other parameters can be changed by setting coefficients. — Voice mute The LC83025E implements processing that removes monaural signal components included in the music signal. This allows CDs with vocals to be used as karaoke CDs. Command data is used to turn the voice mute function on or off. — Simple surround The LC83025E implements a simple surround function by adding delayed components to the music signal. The LC83025E includes six sets of simple surround coefficients as built-in preset data. These values can be switched by sending command data. Applications can implement their own original surround effects by setting the coefficients. However, the algorithm itself is fixed. • • • • • — Flexible input mixing The LC83025E supports hybrid mixing of digital and analog left and right channel song inputs, and thus can handle a wide range of disk processing configurations. Audio inputs and outputs — Inputs: Digital - One system (stereo) A/D converter - Three channels — Outputs: Digital - One system (stereo) D/A converter - Two channels — A/D converter Second order ∆∑ modulation - Three channels — D/A converter 4× oversampling digital filters plus second order noise shaper plus 5-bit PWM system - Two channels Master clock: 768 fs External memory: Up to two 256K (64K × 4-bit) DRAMs can be used Microcontroller input: Synchronous 8-bit serial data Supply voltage: 5 V single-voltage Package: QFP80E Package Dimensions unit: mm 3174-QFP80E [LC83025E] SANYO: QFP80E SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN 62896HA (OT)/63095HA (OT) No. 4977-1/15 LC83025E Pin Assignment No. 4977-2/15 LC83025E Block Diagram Signal Flow Overview No. 4977-3/15 LC83025E Pin Functions Pin No. [Control pins] 13 14 10 11 18 19 17 25 to 21 20 48 50, 49 51 52 OSC1 OSC2 FS384I SELC SAIF SAOF RES TEST5 to TEST1 TEST6 P0 P2, P1 P3 P4 I O I I I I I I O I I O O Crystal oscillator connection (768 fs) Crystal oscillator connection (768 fs) 384 fs input (Apply a clock that is equal to the OSC1/OSC2 768 fs clock divided by 2.) Audio clock source switching (High: Fixes FS384I as the clock) Digital audio input mode switching (Low: backward packed, High: forward packed) Digital audio output mode switching (Low: 48 fs, High: 64 fs) Reset Test (Must be tied to ground in normal operation.) Test (Must be left open in normal operation.) Coefficient transfer mode switching Initial operating mode setting (This pin should be held high in normal operation.) Microphone signal present (low output) or absent (high output) indication output Music signal present (low output) or absent (high output) indication output Symbol I/O Function [External memory interface] 79 80 1 2 68 to 60 69 to 71, 74 to 78 [Audio interface] 9 5 8 4 6 7 3 35 33 37 40 38 42 45 43 47 28 31 LRCKI LRCKO BCKI BCKO FS384O ASI ASO ADL1 ADL2 ADL3 ADR1 ADR2 ADR3 ADM1 ADM2 ADM3 DAOL DAOR I O I O O I O I O O I O O I O O O O ASI L/R clock input (1 fs) ASO L/R clock output (1 fs) ASI bit clock input (32 fs or higher) ASO bit clock output (48 fs or 64 fs) ASO 384 fs output Digital audio data input (MSB first, 16 bits) Digital audio data output (MSB first, backward packed, 16 bits) A/D converter input (left channel) A/D converter output (left channel) A/D converter output (left channel) A/D converter input (right channel) A/D converter output (right channel) A/D converter output (right channel) A/D converter input (microphone) A/D converter output (microphone) A/D converter output (microphone) D/A converter output (left channel) D/A converter output (right channel) RAS CAS DREAD DWRT A8 to A0 D7 to D0 O O O O O I/O RAS signal output CAS signal output External memory read signal output External memory write signal output Address outputs Data I/O (Normally, only D3 to D0 are used.) [Microcontroller interface] 55 59 56 57 58 SIRQ SIAK SI SICK SRDY I O I I I Serial input request signal input Output indicating serial input execution in progress Serial data input from the control microcontroller (8-bit serial data) SI transfer clock input Ready signal input from the control microcontroller that indicates that serial data input has completed Continued on next page. No. 4977-4/15 LC83025E Continued from preceding page. Pin No. Symbol I/O Function [Power supply pins] 12, 26, 53, 72 15, 16, 54, 73 36 41 46 29 32 34 39 44 27 30 VDD VSS ADLVDD ADRVDD ADMVDD DALVDD DARVDD ADLVSS ADRVSS ADMVSS DALVSS DARVSS — — — — — — — — — — — — VDD for the digital block (Connect to +5 V.) (Keep connections as short as possible so that potential differences between the VDD pins do not occur.) VSS for the digital block (Connect to ground.) (Keep connections as short as possible so that potential differences between the VSS pins do not occur.) A/D converter VDD (left channel) (Connect to +5 V.) A/D converter VDD (right channel) (Connect to +5 V.) A/D converter VDD (microphone) (Connect to +5 V.) D/A converter VDD (left channel) (Connect to +5 V.) D/A converter VDD (right channel) (Connect to +5 V.) A/D converter VSS (left channel) (Connect to ground.) A/D converter VSS (right channel) (Connect to ground.) A/D converter VSS (microphone) (Connect to ground.) D/A converter VSS (left channel) (Connect to ground.) D/A converter VSS (right channel) (Connect to ground.) Design the application wiring so that potential differences do not occur between the analog VDD pins and between the digital VDD group and the analog VDD group. Design the application wiring so that potential differences do not occur between the analog VSS pins and between the digital VSS group and the analog VSS group. No. 4977-5/15 LC83025E Pin Circuits Specification Circuit Pins ASO, LRCKO, BCKO, RAS, CAS, DREAD, DWRT, FS384O, A0 to A8 TTL output CMOS intermediate current output P3, P4, SIAK, TEST6 Analog output DAOL, DAOR, ADL2, ADL3, ADM2, ADM3, ADR2, ADR3 Schmitt input Low Schmitt input SI, SICK, SIRQ, SRDY, (OSC1) FS384I, BCKI, ASI, LRCKI Normal input TEST1 to TEST5 Input with built-in pull-up resistor RES Input with built-in pull-down resistor SELC, SAIF, SAOF CMOS intermediate current output Low Schmitt input D0 to D7 N-channel open drain intermediate current output Normal input P0 to P2 Analog input ADL1, ADR1, ADM1 No. 4977-6/15 LC83025E Specifications Absolute Maximum Ratings at Ta = 25°C, VSS = 0 V Parameter Maximum supply voltage Output voltage Input voltage Peak output current Symbol VDD max VO1 V O2 VIN IOP1 IOP2 IOA1 IOA2 Average output current ΣIOA1 ΣIOA2 ΣIOA3 Allowable power dissipation Operating temperature Storage temperature Pd max Topr Tstg Audio interface, external RAM interface Microcontroller interface, P3, P4 Audio interface, external RAM interface: per pin Microcontroller interface, P3, P4: per pin Total for FS384O, LRCKO, BCKO, and ASO Total for DWRT, DREAD, RAS, CAS, A3 to A8 and D0 to D7 Total for A0 to A2, SIAK, P3 and P4 Ta = –30 to +70°C OSC2 output Pins other than OSC2 Conditions Ratings –0.3 to +7.0 Allowed up to the oscillator voltage. –0.3 to VDD + 0.3 –0.3 to VDD + 0.3 –2 to +4 –2 to +10 –2 to +4 –2 to +10 –10 to +10 –30 to +30 –10 to +10 700 –30 to +70 –40 to +125 Unit V V V V mA mA mA mA mA mA mA mW °C °C 1 2 1 2 Note Allowable Operating Ranges at Ta = –30 to +70°C, all VDD = 4.75 to 5.25 V, all VSS = 0 V unless otherwise specified Parameter Operating supply voltage Symbol VDD VIH1 Input high level voltage VIH2 VIH3 VIL1 Input low level voltage VIL2 VIL3 Instruction cycle time [External Clock Input Conditions] Frequency Pulse width Rise time Fall time [Self-Excitation Oscillation Conditions] Oscillator frequency Oscillator stabilization period [Audio Data Input Conditions] Transfer bit clock period Transfer bit clock pulse width Data setup time Data hold time [Serial Input Clock Conditions] Serial clock period Serial clock pulse width Data setup time Data hold time SRDY hold time SRDY pulse width [DRAM Input Conditions] Input data setup time Input data hold time tDSI tDHI Related to external DRAM data input. Shown in Figure 6. (Related to the CAS and D0 to D7 pins.) 20 0 ns ns tSCYC tSCW tSS tSH tSYH tSYW Related to the microcontroller interface. Shown in Figure 5. (Related to the SICK, SI and SRDY pins.) 480 200 70 70 200 200 ns ns ns ns ns ns tBCYC tBCW tS tH Related to the BCKI and ASI pins. Shown in Figure 4. 354 100 70 70 ns ns ns ns fOSC fOSCS OSC1 and OSC2: shown in Figure 2. 44.1 kHz × 768 × ± 0.1% Shown in Figure 3. 33.84 33.90 100 MHz ms fEXT tEXTH tEXTL tEXTR tEXTF Related to the FS384I pin. Shown in Figure 1. max: 44.1 kHz × 384 × 1.005 min: 44.1 kHz × 384 × 0.995 16.85 23 23 9 9 17.01 MHz ns ns ns ns tCYC Audio interface, external RAM interface P0 to P2, SELC, SAIF, SAOF, TEST1 to TEST5 RES, OSC1, microcontroller interface Audio interface, external RAM interface P0 to P2, SELC, SAIF, SAOF, TEST1 to TEST5 RES, OSC1, microcontroller interface 58 Conditions min 4.75 2.4 0.7 VDD 0.75 VDD 0.8 0.3 VDD 0.25 VDD 59.11 typ max 5.25 Unit V V V V V V V ns 4 5 6 4 5 6 Note No. 4977-7/15 LC83025E Electrical Characteristics 1 at Ta = –30 to +70°C, all VDD = 4.75 to 5.25 V, all VSS = 0 V unless otherwise specified Parameter Symbol IIL1 Input low level current IIL2 IIL3 IIH1 Input high level current IIH2 IIH3 Output high level voltage VOH1 VOH2 VOL1 VOL2 IOFF CIO tOH tOD tRP tRAS tCP tCAS tPC tRCD tCSH tRSH tASR tRAH tASC tCAH tWP tWCS tWCH tDSO tDHO C1 C2 L IDD OSC1 and OSC2: shown in Figure 2. Timing for output to the external DRAM. Shown in Figure 8. –30 50 Conditions RES, VIN = VSS (Input pins with built-in pull-up resistor) P0 to P2, VIN = VSS Other input-only pins SELC, SAIF, SAOF, VIN = VDD (Input pins with built-in pull-down resistor) P0 to P2, VIN = VDD (n-channel transistor: off) Other input-only pins IOH = –0.4 mA IOH = –50 µA IOL = 2 mA IOL = 10 mA VO = VSS, VDD –40 4.0 VDD – 1.2 4.98 4.997 0.065 0.32 0.4 1.5 +40 10 min –250 –10 –10 100 250 10 10 typ –100 max Unit µA µA µA µA µA µA V V V V µA pF 1, 8 2, 3, 8 1, 8 2, 3, 8 8 Note 8 Output low level voltage Output off leakage current I/O capacitance [Audio Data Output Timing] Output data hold time Output data delay time [External DRAM Access Timing] RAS high pulse width RAS low pulse width CAS high pulse width CAS low pulse width CAS cycle time RAS to CAS delay time CAS hold time RAS hold time RAS address setup time RAS address hold time CAS address setup time CAS address hold time DWRT pulse width Write command setup time Write command hold time Output data setup time Output data hold time Crystal oscillator BCKO and ASO: shown in Figure 7. ns ns 7 7 80 700 50 95 175 60 170 95 60 20 30 90 95 12 65 30 100 13 29 1.5 60 95 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns pF pF µH mA 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 8 8 8 9 Current drain VDD1, VDD2, VDD3; oscillator frequency: 33.8688 MHz No. 4977-8/15 LC83025E Electrical Characteristics 2 at Ta = 25°C, all VDD = 5.0 V, all VSS = 0 V unless otherwise specified Parameter [A/D Converter Block] 1 kHz, 0 dB: Lch Total harmonic distortion A-THD 1 kHz, 0 dB: Rch 1 kHz, 0 dB: Mic Signal-to-noise ratio Crosstalk [D/A Converter Block] Total harmonic distortion Signal-to-noise ratio Crosstalk Note: 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. D-THD D-S/N D-C · T 1 kHz, –1 dB 1 kHz, –1 dB 1 kHz, –1 dB 0.045 78 –75 % dB dB 10 10 10 A-S/N A-C · T 1 kHz, 0 dB 1 kHz, 0 dB 70 0.065 0.065 0.070 75 –72 % % % dB dB 10, 11 10, 11 10, 11 10, 11 10 Symbol Conditions min typ max Unit Note TTL output level pins: ASO, FS384O, BCKO, LRCKO, D0 to D7, A0 to A8, RAS, CAS, DREAD, DWRT CMOS intermediate current output pins: P3, P4, SIAK, TEST6 N-channel open-drain intermediate current output pins: P0 to P2 Low Schmitt input pins: BCKI, ASI, LRCKI, D0 to D7, FS384I Normal input pins: P0 to P2, TEST1 to TEST5, SELC, SAIF, SAOF Schmitt input pins: RES, SI, SICK, SIRQ, SRDY, OSC1 When the load capacitance is 50 pF The values for the oscillator capacitors C1 and C2 include the wiring capacitances. The value for the current drain is a typical value for VDD = 5 V, room temperature, and a typical sample. With weight A filter present, with Fs = 44.1 kHz, and tested in the Sanyo evaluation board. Varies with the values of the external components. The listed value is for the circuit structure and values shown in Figure 9 in the Sanyo evaluation board. Figure 1 External Clock Input Waveform (FS384I) Figure 2 Crystal Oscillator Circuit Figure 3 Oscillator Stabilization Time No. 4977-9/15 LC83025E Figure 4 Audio Data Input Conditions Figure 5 Microcontroller Interface Figure 6 Timing for Data Input from External DRAM Figure 7 Audio Data Output Timing No. 4977-10/15 LC83025E Figure 8 Timing for Data Output to External DRAM Figure 9 Sample A/D Converter External Circuit No. 4977-11/15 LC83025E Figure 10 Sample D/A Converter External Circuit No. 4977-12/15 LC83025E Sample Peripheral Circuit Connection (For applications that do not use digital input) Whether or not the digital outputs and the analog L/R outputs will be used will be determined by the end product specifications. These pins should be left open if unused. No. 4977-13/15 LC83025E Sample Peripheral Circuit Connection (For applications that use digital input.) Whether or not the analog L/R inputs and the analog L/R outputs will be used will be determined by the end product specifications. A high or low level should be applied to unused input pins, and unused output pins should be left open. No. 4977-14/15 LC83025E s No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. s Anyone purchasing any products described or contained herein for an above-mentioned use shall: Œ Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use:  Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. s Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of November, 1997. Specifications and information herein are subject to change without notice. No. 4977-15/15