LC83026E

Ordering number : EN5663 CMOS IC LC83026E Digital Signal Processor for Karaoke Systems Overview The LC83026E provides the audio signal processing required in karaoke systems, including pitch shift, microphone echo, voice muting, and simple surround simulation. It is a special-purpose DSP that implements karaoke processing with the addition of a single external 256-Kb DRAM. The LC83026E includes on-chip A/D and D/A converters and supports both digital and analog inputs and outputs. Its functions and characteristics can be modified to match the needs of the end product by sending coefficient data from the microcontroller over a serial interface. • Features • Application features — Pitch shift The LC83026E supports pitch shifting of ±15 quarter tone steps, or ±1 octave in scale tone units as specified by command data. This pitch shifting can be applied either to the music track or to the microphone input. It is also possible to set up pitch shifting of ±1 octave in arbitrary steps by setting coefficient values. — Microphone echo The LC83026E can apply echo processing to the input signal from the microphone A/D converter. The echo coefficients, including amount of echo and delay time, can be set. — Voice muting The LC83026E provides attenuation of monaural components in the music signal. This allows CDs that include vocals to be used for karaoke. The voice muting function is turned on or off by command data transferred over the serial interface. — Simple surround The LC83026E implements a simple surround simulation function by adding delay components to the music signal. The LC83026E includes six sets of simple surround coefficients as preset data, and these can be selected and switched using command data transferred over the serial interface. User-original surround effects can be implemented by setting • • • • • coefficients, but the algorithm is fixed. — Versatile input mixing The LC83026E supports hybrid mixing of digital music inputs and analog music inputs for both the left and right channels to support the processing of a wide range of disks. Audio inputs and outputs — Inputs: Digital One system (stereo) A/D converters Three channels — Outputs: Digital One system (stereo) D/A converters Two channels — A/D converters Second-order delta-sigma modulation Three channels — D/A converters 2× oversampling digital filters + third-order noise shaper system Two channels Master clock: 768fs External memory: Up to two 256K (64K × 4 bits) external DRAMs can be used. Microcontroller input: Synchronous 8-bit serial data Power-supply voltage: 5V single-voltage supply Package: QFP80E Package Dimensions unit: mm 3174-QFP80E [LC83026E] SANYO: QIP80E SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN 63097HA(OT) No. 5663-1/16 LC83026E Pin Assignment Block Diagram Program ROM Program counter Loop counter Program decoder Microcontroller interface No. 5663-2/16 LC83026E Pin Functions Pin OSC1 OSC2 FS384I SELC Control pins SAIF SAOF RES Pin No. 19 20 22 8 10 11 9 I/O I O I I I I I I I I O O O O O O O Crystal oscillator connection (768fs) Crystal oscillator connection (768fs) 384fs input Audio clock source switching (High: external, low: internal) Digital audio input mode switching (Low: backward packing, high: forward packing) Digital audio output mode switching (Low: 48fs, high 64fs) Reset Test (Must be connected to ground during normal operation.) Coefficient transfer mode control Initial operating mode control (A high level should be applied for normal operation.) Microphone signal input level: Yes (low output)/No (high output) output Music signal input level: Yes (low output)/No (high output) output RAS signal output CAS signal output External memory read signal output External memory write signal output Address output Function TEST5 to 1 16 to 12 P0 P2 to P1 P3 P4 49 51, 50 52 53 78 79 80 1 67 to 59 68 to 71, 74 to 77 23 4 7 3 5 6 2 34 32 36 40 38 42 45 43 47 25 26 30 29 54 58 55 56 57 External memory interface RAS CAS DREAD DWRT A8 to A0 D7 to D0 LRCKI LRCKO BCKI BCKO FS384O ASI ASO ADL1 I/O Data input and output (Normally only D0 to D3 are used) I O I O O I O I O O I O O I O O O O O O I O I I I ASI L/R clock input (1fs) ASO L/R clock output (1fs) ASI bit clock input (32fs or higher) ASO bit clock output (48fs or 64fs) ASO 384fs output Digital audio data input (16-bits, MSB first) Digital audio data output (16-bits, MSB first, backward packed) A/D converter input (left channel) A/D converter output (left channel) A/D converter output (left channel) A/D converter input (right channel) A/D converter output (right channel) A/D converter output (right channel) A/D converter input (microphone) A/D converter output (microphone) A/D converter output (microphone) D/A converter output (left channel) D/A converter output (left channel) D/A converter output (right channel) D/A converter output (right channel) Input for the serial input request signal Output that indicates that a serial input is in progress Serial data input from the control microcontroller (8-bit serial input) SI pin transfer clock input Ready signal input (from the control microcontroller) that indicates the completion of a serial data input. Audio interface Microcontroller interface ADL2 ADL3 ADR1 ADR2 ADR3 ADM1 ADM2 ADM3 DALP DALN DARP DARN SIRQ SIAK SI SICK SRDY Continued on next page. No. 5663-3/16 LC83026E Continued from preceding page. Pin Pin No. I/O — Digital block VDD (Must be connected to +5 V.) DVSS1 to 3 21, 48, 73 ADLVDD Power supply ADRVDD ADMVDD DALVDD DARVDD ADLVSS ADRVSS ADMVSS DALVSS DARVSS 35 41 46 24 31 33 39 44 27 28 — Digital block VSS (Must be connected to ground.) — — — — — — — — — — A/D converter VDD (left channel) (Connect to +5 V.) A/D converter VDD (right channel) (Connect to +5 V.) A/D converter VDD (microphone) (Connect to +5 V.) D/A converter VDD (left channel) (Connect to +5 V.) D/A converter VDD (right channel) (Connect to +5 V.) A/D converter VSS (left channel) (Connect to ground.) A/D converter VSS (right channel) (Connect to ground.) A/D converter VSS (microphone) (Connect to ground.) D/A converter VSS (left channel) (Connect to ground.) D/A converter VSS (right channel) (Connect to ground.) Design the wiring so that potential differences do not occur between the analog system VSS pins and either other analog system VSS pins or the digital system VSS pins. Design the wiring so that potential differences do not occur between the analog system VDD pins and either other analog system VDD pins or the digital system VDD pins. Function DVDD1 to 3 17, 18, 72 Pin Circuits Pins ASO, LRCKO, BCKO, RAS, CAS, DREAD, DWRT, FS384O, A0 to A8 Specifications TTL output Circuit Output data P3, P4, SIAK CMOS intermediate current output ADL2, ADL3, ADM2, ADM3, ADR2, ADR3 Output data Analog output DALP, DALN, DARP, DARN Output data SI, SICK, SIRQ, SRDY, (OSC1) FS384I, BCKI, ASI, LRCKI Schmitt input Input data Low Schmitt input TEST1 to TEST5 Normal input Input data RES Input with built-in pull-up resistor Input data Input data SELC, SAIF, SAOF Input with built-in pull-down resistor Continued on next page. No. 5663-4/16 LC83026E Continued from preceding page. Pins Specifications Circuit D0 to D7 CMOS intermediate current output Low Schmitt input Input data I/O control Output data Input data P0 to P2 N-channel open drain intermediate current output Normal input Off during normal operation Test output data ADL1, ADR1, ADM1 Analog input Input data Specifications Absolute Maximum Ratings at Ta = 25°C, VSS = 0 V Parameter Maximum supply voltage Input voltage Symbol VDD max VIN VO1 VO2 Peak output current IOP1 IOP2 IOA1 IOA2 Average output current ∑IOA1 ∑IOA2 Allowable power dissipation Operating temperature Storage temperature Pd max Topr Tstg OSC2 output Outputs other than OSC2 Audio interface, external RAM interface Microcontroller interface, P3, P4 Audio interface, external RAM interface: Per pin Microcontroller interface, P3, P4: Per pin FS384O, LRCKO, BCKO, ASO : Total DWRT, DREAD, RAS, CAS, A0 to A8, D0 to D7, SIAK, P3, P4 : Total Ta = –30 to +70°C Conditions Ratings –0.3 to +7.0 –0.3 to VDD +0.3 Values up to the oscillator voltage are allowable. –0.3 to VDD +0.3 –2 to +4 –2 to +10 –2 to +4 –2 to +10 –10 to +10 –10 to +10 700 –30 to +70 –40 to +125 Unit V V V V mA mA mA mA mA mA mW °C °C 1 2 1 2 Notes Output voltage Allowable Operating Ranges at Ta = –30 to +70°C, all VDD = 4.75 to 5.25 V, all VSS = 0 V unless otherwise specified Parameter Operating supply voltage Symbol VDD VIH1 Input high-level voltage VIH2 VIH3 VIL1 Input low-level voltage VIL2 VIL3 Instruction cycle time tCYC Audio interface and external RAM interface P0 to P2, SELC, SAIF, SAOF, TEST1 to TEST5 RES, OSC1, and the microcontroller interface Audio interface and external RAM interface P0 to P2, SELC, SAIF, SAOF, TEST1 to TEST5 RES, OSC1, and the microcontroller interface 58 Conditions Ratings min 4.75 2.4 0.7 VDD 0.75 VDD 0.8 0.3 VDD 0.25 VDD 59.11 typ max 5.25 Unit Notes V V V V V V V ns 4 5 6 4 5 6 Continued on next page. No. 5663-5/16 LC83026E Continued from preceding page. Ratings min typ max Parameter [External Clock Input Conditions] Frequency Pulse width Rise time Fall time Symbol Conditions Unit Notes fEXT fEXTH fEXTL tEXTR tEXF Related to the FS384I pin. See Figure 1. maximum: 44.1 kHz × 384 × 1.005 minimum: 44.1 kHz × 384 × 0.995 16.85 23 23 17.01 MHz ns ns 9 9 ns ns [Self-Excited Oscillation Conditions(crystal oscillator)] Oscillator frequency Oscillator stabilization period [Audio Data Input Conditions] Transfer bit clock period Transfer bit clock pulse width Data setup time Data hold time [Serial I/O Clock Conditions] Serial clock period Serial clock pulse width Data setup time Data hold time SRDY hold time SRDY pulse width [DRAM Input Conditions] Input data setup time Input data hold time tDSI tDHI Related to external DRAM data input. See Figure 6. (Related to CAS and D0 to D7.) 20 0 ns ns tSCYC tSCW tSS tSH tSYH tSYW Related to the microcontroller interface. See Figure 5. (Related to SICK, SI, and SRDY.) 480 200 70 70 200 200 ns ns ns ns ns ns tBCYC tBCW tS tH Related to BCKI. See Figure 4. 354 100 70 70 ns ns ns ns fOSC tOSCS OSC1 and OSC2. See Figure 2. 44.1 kHz/48 kHz × 768 ±0.1% See Figure 3. 33.84 40.55 100 MHz ms Electrical Characteristics 1 at Ta = –30 to +70°C, all VDD = 4.75 to 5.25 V, all VSS = 0 V unless otherwise specified Parameter Symbol Conditions SELC, SAIF, SAOF, VIN = VDD (Input pins with pull-down resistors) P0 to P2, VIN = VDD (Nch transistor OFF) Other input-only pins RES, VIN = VSS (Input pins with pull-up resistors) P0 to P2, VIN = VSS Other input-only pins IOH = –0.4 mA IOH = –50 µA IOL = 2 mA IOL = 10 mA VO = VSS, VDD –40 –250 –10 –10 4.0 VDD –1.2 4.98 4.997 0.065 0.32 0.4 1.5 +40 10 –100 Ratings min typ 100 max 250 10 10 Unit Notes IIH1 Input high-level current IIH2 IIH3 IIL1 Input low-level current IIL2 IIL3 Output high-level voltage VOH1 VOH2 VOL1 VOL2 IOFF CIO tOH tOD µA µA µA µA µA µA V V V V µA pF 8 8 1, 8 2,3,8 1, 8 2,3,8 Output low-level voltage Output off leakage current Input and output capacitance [Audio Data Output Timing] Output data hold time Output data delay time BCK0 and ASO. See Figure 7. –30 50 ns ns 7 7 Continued on next page. No. 5663-6/16 LC83026E Continued from preceding page. Parameter [External DRAM Access Timing] RAS high-level pulse width RAS low-level pulse width CAS high-level pulse width CAS low-level pulse width CAS cycle time RAS to CAS delay time CAS hold time RAS hold time RAS address setup time RAS address hold time CAS address setup time CAS address hold time DWRT pulse width Write command setup time Write command hold time Output data setup time Output data hold time tRP tRAS tCP tCAS tPC tRCD tCSH tRSH tASR tRAH tASC tCAH tWP tWCS tWCH tDSO tDHO C1 Crystal oscillator C2 L Current drain IDD For VDD1, VDD2, and VDD3 when operating at 33.8688 MHz. OSC1 and OSC2. See Figure 2. Output timing to the external DRAM. See Figure 8. Output timing to the external DRAM. See Figure 8. 80 700 50 95 175 60 170 95 60 20 30 90 95 12 65 30 100 13 29 1.5 60 95 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns pF pF µH mA 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 8 8 8 9 Symbol Conditions Ratings min typ max Unit Notes Electrical Characteristics 2 at Ta = 25°C, all VDD = 5.0 V, all VSS = 0 V unless otherwise specified Parameter [A/D Converter Block] Total harmonic distortion Signal-to-noise ratio Crosstalk [D/A Converter Block] Total harmonic distortion Signal-to-noise ratio Crosstalk Notes: D-THD D-S/N D-C · T 1 kHz, at 0 dB 1 kHz, at 0 dB 1 kHz, at 0 dB 0.01 85 –80 % 10 A-THD A-S/N A-C · T 1 kHz, at 0 dB 1 kHz, at 0 dB 1 kHz, at 0 dB 75 0.05 80 –75 % 10 Symbol Conditions Ratings min typ max Unit Notes dB 10,11 dB 10,11 dB 10,11 dB 10,11 1. TTL output level pins: ASO, FS384O, BCKO, LRCKO, D0 to D7, A0 to A8, RAS, CAS, DREAD, DWRT 2. CMOS intermediate current output pins: P3, P4, SIAK 3. N-channel open drain intermediate current output pins: P0 to P2 4. Low Schmitt input pins: BCKI, ASI, LRCKI, D0 to D7, FS384I 5. Normal input pins: P0 to P2, TEST1 to TEST5, SELC, SAIF, SAOF 6. Schmitt input pins: RES, SI, SICK, SIRQ, SRDY, OSC1 7. When the load capacitance is 50 pF. 8. The values for the oscillator capacitors C1 and C2 include the line capacitances. 9. The typical values for the current drain are for VDD = 5 V, room temperature, and typical samples. 10. Fs = 44.1 kHz and 20 kHz low-pass filter used. Measurement is with the external circuit structure and constants in the Sanyo evaluation board. 11. With the weight A filter used. No. 5663-7/16 LC83026E Figure 1 External Clock Input Waveform (FS384I) Lower limit of the operating VDD Figure 2 Crystal Oscillator Circuit Stable oscillation Oscillator stabilization time Figure 3 Oscillator Stabilization Time Transfer bit clock (BCKI) Input data (ASI) Figure 4 Audio Data Input Conditions Serial clock (SICK) Input data (SI) Transfer complete (SRDY) Figure 5 Microcontroller Interface No. 5663-8/16 LC83026E (A0 to A8) (D0 to D3) Figure 6 External DRAM Data Input Timing Transfer bit clock (BCKO) Output data (ASO) Figure 7 Audio Data Output Timing (A0 to A8) (D0 to D3) Figure 8 External DRAM Data Output Timing Differences between the LC83025E and the LC83026E Parameter LC83025E Decimation filter improved Input comparator improved A/D converter block *: The VREF pin was added in association with the improvements to the input comparator. The VREF pin external capacitor must be located as close as possible to the LC83026E, and must be connected with lines that are as short as possible. 4 × oversampling filters used D/A converter block Second-order noise shaping Single-pin output used. Reset time When no digital input is provided (when the SELC pin is low) One or more sampling period The LRCKI and BCKI pins must be connected to the LRCKO and BCKO pins. 2 × oversampling filters used Third-order noise shaping Two-pin output operation Two or more sampling periods The LRCKI and BCKI pins must be connected to either VDD or VSS; they do not need to be connected to the LRCKO and BCKO pins. LC83026E No. 5663-9/16 Overall Signal Flow Clip processing Surround Voice mute Pitch shifter Clip processing LC83026E Bass Clip processing Clip processing A margin of 1 bit Microphone echo DC cut high-pass filter No. 5663-10/16 LC83026E *: The VREF pin capacitor must be located as close as possible to the IC. Note: All external circuits should be located as close as possible to the IC. No. 5663-11/16 Figure 9 A/D Converter External Circuit Example Left channel output LC83026E Identical to the left channel circuit Right channel output No. 5663-12/16 Figure 10 D/A Converter External Circuit Example LC83026E Application Circuit Example Outline (When digital input is not used) DVDD1 to DVDD3 DVSS1 to DVSS3 The values of 29 and 13 pF here include the printed circuit board capacitances. D/A converter external circuit (left channel) A/D converter external circuit (left channel) D/A converter external circuit (right channel) A/D converter external circuit (right channel) D/A converter A/D converter external circuit (microphone) D0 to D3 A0 to A8 Microcontroller (Coefficient transfer mode control pin) (Initial mode selection pins) (Microphone input level display pin) (Music input level display pin) TEST1 to TEST5 D4 to D7 Whether or not the digital inputs and/or analog outputs are used depends on the specifications of the application. If any of these pins are not used, any unused input pins should be tied to high or low and any unused output pins should be left open. No. 5663-13/16 LC83026E Application Circuit Example Outline (When digital input is used 1) Divide-bytwo circuit DVDD1 to DVDD3 DVSS1 to DVSS3 The values of 29 and 13 pF here include the printed circuit board capacitances. D/A converter external circuit (left channel) A/D converter external circuit (left channel) D/A converter external circuit (right channel) A/D converter external circuit (right channel) D/A converter A/D converter external circuit (microphone) CD-DSP or other circuit D0 to D3 A0 to A8 Microcontroller (Coefficient transfer mode control pin) (Initial mode selection pins) (Microphone input level display pin) (Music input level display pin) TEST1 to TEST5 Apply high or low levels to these pins according to the audio interface mode used. D4 to D7 Whether or not the digital inputs and/or analog outputs are used depends on the specifications of the application. If any of these pins are not used, any unused input pins should be tied to high or low and any unused output pins should be left open. No. 5663-14/16 LC83026E Application Circuit Example Outline (When digital input is used 2) DVDD1 to DVDD3 DVSS1 to DVSS3 The values of 29 and 13 pF here include the printed circuit board capacitances. D/A converter external circuit (left channel) A/D converter external circuit (left channel) D/A converter external circuit (right channel) A/D converter external circuit (right channel) D/A converter A/D converter external circuit (microphone) CD-DSP or other circuit D0 to D3 A0 to A8 Microcontroller (Coefficient transfer mode control pin) (Initial mode selection pins) (Microphone input level display pin) (Music input level display pin) TEST1 to TEST5 Apply high or low levels to these pins according to the audio interface mode used. D4 to D7 Whether or not the digital inputs and/or analog outputs are used depends on the specifications of the application. If any of these pins are not used, any unused input pins should be tied to high or low and any unused output pins should be left open. No. 5663-15/16 LC83026E s No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. s Anyone purchasing any products described or contained herein for an above-mentioned use shall: Œ Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use:  Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. s Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of June, 1997. Specifications and information herein are subject to change without notice. No. 5663-16/16