LC863216C

Ordering number : ENA0115A LC863264C,LC863256C LC863248C,LC863240C LC863232C,LC863228C LC863224C,LC863220C LC863216C Overview CMOS IC 64K/56K/48K/40K/32K/28K/24K/20K/16K-byte ROM, CGROM16K-byte on-chip 640/512-byte RAM and 352x9 bit OSD RAM 8-bit 1-chip Microcontroller The LC863264C/56C/48C/40C/32C/28C/24C/20C/16C are 8-bit single chip microcontrollers with the following on-chip functional blocks: • CPU : Operable at a minimum bus cycle time of 0.424µs • On-chip ROM capacity Program ROM : 64K/56K/48K/40K/32K/28K/24K/20K/16K bytes CGROM : 16K bytes • On-chip RAM capacity : 640/512 bytes • OSD RAM : 352×9 bits • Closed-Caption TV controller and the on-screen display controller • Closed-Caption data slicer • Four channels×8-bit AD Converter • Three channels×7-bit PWM • Two 16-bit timer/counters, 14-bit base timer • 8-bit synchronous serial interface circuit • IIC-bus compliant serial interface circuit (Multi-master type) • ROM correction function • 16-source 10-vectored interrupt system Continued on next page. Note : This product includes the IIC bus interface circuit. If you intend to use the IIC bus interface, please notify us of this in advance of our receiving your program ROM code order. Purchase of SANYO IIC components conveys a license under the Philips IIC Patents Rights to use these components in an IIC system, provided that the system conforms to the IIC Standard Specification as defined by Philips. Trademarks IIC is a trademark of Philips Corporation. Ver.1.00 71006HKIM No.A0115-1/21 LC863264C/56C/48C/40C/32C/28C/24C/20C/16C Continued from preceding page. • Integrated system clock generator and display clock generator Only one X’tal oscillator (32.768kHz) for PLL reference is used for both generators TV control and the Closed Caption function All of the above functions are fabricated on a single chip. Features Read-Only Memory (ROM) : 65536×8 bits / 57344×8 bits / 49152×8 bits / 40960×8 bits / 32768×8 bits / 28672×8 bits / 24576×8 bits / 20480×8 bits / 16384×8 bits for program 16128×8 bits for CGROM 512×8 bits (working area) : LC863264C/56C/48C/40C 384×8 bits (working area) : LC863232C/28C/24C/20C/16C 128×8 bits (working or ROM correction function) 352×9 bits (for CRT display) Random Access Memory (RAM) : OSD functions • Screen display : 36 characters×16 lines (by software) • RAM : 352 words (9 bits per word) Display area : 36 words×8 lines Control area : 8 words×8 lines • Characters Up to 252 kinds of 16×32 dot character fonts (4 characters including 1 test character are not programmable) Each font can be divided into two parts and used as two fonts : a 16×17 dot and 8×9 dot character font At least 111 characters need to be divide to display the caption fonts. • Various character attributes Character colors : 16colors Character background colors : 16colors Fringe / shadow colors : 16colors Full screen colors : 16colors Rounding Underline Italic character (slanting) • Attribute can be changed without spacing • Vertical display start line number can be set for each row independently (Rows can be overlapped) • Horizontal display start position can be set for each row independently • Horizontal pitch (9 to 16 dots)*1 and vertical pitch (1 to 32 dots) can be set for each row independently • Different display modes can be set for each row independently Caption • Text mode / OSD mode 1 / OSD mode 2 (Quarter size) / Simplified graphic mode • Ten character sizes *1 Horez. × Vert. = (1×1), (1×2), (2×2), (2×4), (0.5×0.5) (1.5×1), (1.5×2), (3×2), (3×4), (0.75×0.5) • Shuttering and scrolling on each row • Simplified Graphic Display Note *1: range depends on display mode : refer to the manual for details. Data Slicer (NTSC) • Line 21 closed caption data and XDS data extraction No.A0115-2/21 LC863264C/56C/48C/40C/32C/28C/24C/20C/16C Bus Cycle Time / Instruction-Cycle Time Bus cycle time 0.424µs 7.5µs 183.1µs Instruction cycle time 0.848µs 15.0µs 366.2µs System clock oscillation Internal VCO (Ref : X’tal 32.768kHz) Internal RC Crystal 800kHz 32.768kHz 4.5V to 5.5V 4.5V to 5.5V Oscillation frequency 14.156MHz Voltage 4.5V to 5.5V Ports • Input / Output Ports : 5 ports (28 terminals) Data direction programmable in nibble units : 1 port (8 terminals) (If the N-ch open drain output is selected by option, the corresponding port data can be read in output mode.) Data direction programmable for each bit individually : 4 ports (20 terminals) AD converter • 4 channels×8-bit AD converters Serial interfaces • IIC-bus compliant serial interface (Multi-master type) Consists of a single built-in circuit with two I/O channels. The two data lines and two clock lines can be connected internally. • Synchronous 8-bit serial interface PWM output • 3 channels×7-bit PWM Timer • Timer 0 : 16-bit timer/counter With 2-bit prescaler + 8-bit programmable prescaler Mode 0 : Two 8-bit timers with a programmable prescaler Mode 1 : 8-bit timer with a programmable prescaler + 8-bit counter Mode 2 : 16-bit timer with a programmable prescaler Mode 3 : 16-bit counter The resolution of timer is 1 tCYC. • Timer 1 : 16-bit timer/PWM Mode 0 : Two 8-bit timers Mode 1 : 8-bit timer + 8-bit PWM Mode 2 : 16-bit timer Mode 3 : Variable bit PWM (9 to 16 bits) In mode0/1, the resolution of Timer1/PWM is 1 tCYC In mode2/3, the resolution is selectable by program; tCYC or 1/2 tCYC • Base timer Generate every 500ms overflow for a clock application (using 32.768kHz crystal oscillation for the base timer clock) Generate every 976µs, 3.9ms, 15.6ms, 62.5ms overflow (using 32.768kHz crystal oscillation for the base timer clock) Clock for the base timer is selectable from 32.768kHz crystal oscillation, system clock or programmable prescaler output of Timer 0 Remote control receiver circuit (connected to the P73/INT3/T0IN terminal) • Noise rejection function • Polarity switching Watchdog timer External RC circuit is required Interrupt or system reset is activated when the timer overflows ROM correction function Max 128 bytes / 2 addresses No.A0115-3/21 LC863264C/56C/48C/40C/32C/28C/24C/20C/16C Interrupts • 16 sources 10 vectored interrupts 1. External Interrupt INT0 2. External Interrupt INT1 3. External Interrupt INT2, Timer/counter T0L (Lower 8 bits) 4. External Interrupt INT3, base timer 5. Timer/counter T0H (Upper 8 bits) 6. Timer T1H,T1L 7. SIO0 8. Data slicer 9. Vertical synchronous signal interrupt (VS), horizontal line (HS), AD 10. IIC, Port 0 • Interrupt priority control Three interrupt priorities are supported (low, high and highest) and multi-level nesting is possible. Low or high priority can be assigned to the interrupts from 3 to 10 listed above. For the external interrupt INT0 and INT1, low or highest priority can be set. Sub-routine stack level • A maximum of 128 levels (stack is built in the internal RAM) Multiplication/division instruction • 16 bits×8 bits (7 instruction cycle times) • 16 bits÷8 bits (7 instruction cycle times) 3 oscillation circuits • Built-in RC oscillation circuit used for the system clock • Built-in VCO circuit used for the system clock and OSD • X’tal oscillation circuit used for base timer, system clock and PLL reference Standby function • HALT mode The HALT mode is used to reduce the power dissipation. In this operation mode, the program execution is stopped. This mode can be released by the interrupt request or the system reset. • HOLD mode The HOLD mode is used to stop the oscillations; RC (internal), VCO, and X’tal oscillations. This mode can be released by the following conditions. - Pull the reset terminal (RES) to low level. - Feed the selected level to either P70/INT0 or P71/INT1. - Input the interrupt condition to Port 0. Package • DIP42S (Lead-free type) • QIP48E (Lead-free type) Development tools • Flash EEPROM: • Evaluation chip: • Emulator: LC86F3264A LC863096 EVA86000 (main) + ECB863200* or ECB863200A (evaluation chip board) + POD863200 (pod: DIP42S) or POD863201 (pod: QIP48E) * This product is no longer available No.A0115-4/21 LC863264C/56C/48C/40C/32C/28C/24C/20C/16C Package Dimensions unit : mm (typ) 3025C 37.7 42 22 0.95 3.8 5.1max (4.25) 0.51min 1.78 0.48 (1.05) SANYO : DIP42S(600mil) Package Dimensions unit : mm (typ) 3156A 17.2 36 37 25 24 0.8 14.0 14.0 48 1 1.0 (1.5) (2.7) 0.35 12 13 17.2 0.15 3.0max 0.1 SANYO : QIP48E(14X14) 0.25 1 21 15.24 13.8 No.A0115-5/21 LC863264C/56C/48C/40C/32C/28C/24C/20C/16C Pin Assignments P10/SO0 P11/SI0 P12/SCK0 P13/PWM1 P14/PWM2 P15/PWM3 P16 P17/PWM VSS XT1 XT2 VDD P84/AN4 P85/AN5 P86/AN6 P87/AN7 RES FILT CVIN VS HS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 41 40 39 38 P07 P06 P05 P04 P03 P02 P01 P00 P73/INT3/T0IN P72/INT2/T0IN P71/INT1 P70/INT0 P63/SCLK1 P62/SDA1 P61/SCLK0 P60/SDA0 I BL B G R Top view LC863264C/ LC863256C/ LC863248C/ LC863240C/ LC863232C/ LC863228C/ LC863224C/ LC863220C/ LC863216C DIP42S 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 P14/PWM2 P13/PWM1 P12/SCK0 P10/SO0 P11/SI0 P07 P06 P05 P04 38 48 47 46 45 44 43 42 41 40 39 P15/PWM3 P16 P17/PWM VSS XT1 XT2 VDD NC P84/AN4 P85/AN5 P86/AN6 P87/AN7 37 P03 NC NC 1 2 3 4 5 6 7 8 9 10 11 13 14 15 16 12 36 P02 P01 P00 NC P73/INT3/T0IN P72/INT2/T0IN P71/INT1 P70/INT0 P63/SCLK1 P62/SDA1 P61/SCLK0 P60/SDA0 LC863264C/ LC863256C/ LC863248C/ LC863240C/ LC863232C/ LC863228C/ LC863224C/ LC863220C/ LC863216C QIP48E 17 18 19 20 21 22 23 I 24 NC 35 34 33 32 31 30 29 28 27 26 25 FILT CVIN NC G R VS RES HS BL B Top view No.A0115-6/21 LC863264C/56C/48C/40C/32C/28C/24C/20C/16C System Block Diagram Interrupt Control IR PLA Standby Control ROM RC VCO Clock Generator X’tal PC PLL IIC ROM Correct Control ACC SIO0 XRAM B Register Timer 0 Bus Interface C Register Timer 1 Port 1 ALU Base Timer Port 6 ADC Port 7 PSW INT0-3 Noise Rejection Filter Port 8 RAR PWM OSD Control Circuit CGROM RAM Data Slicer VRAM Stack Pointer Port 0 Watch Dog Timer No.A0115-7/21 LC863264C/56C/48C/40C/32C/28C/24C/20C/16C Pin Description Pin Description Table Terminal VSS XT1 XT2 VDD RES I/O I O I O I I I O O O O O Negative power supply Function Description Option Input terminal for crystal oscillator Output terminal for crystal oscillator Positive power supply Reset terminal Filter terminal for PLL Video signal input terminal Vertical synchronization signal input terminal Horizontal synchronization signal input terminal Red (R) output terminal of RGB image output Green (G) output terminal of RGB image output Blue (B) output terminal of RGB image output Intensity ( I ) output terminal of RGB image output Fast blanking control signal Switch TV image signal and caption/OSD image signal •8-bit input/output port, Input/output can be specified in nibble unit •Other functions HOLD release input Interrupt input Pull-up resistor provided/not provided Output Format CMOS/Nch-OD FILT CVIN VS HS R G B I BL Port 0 P00 to P07 I/O Port 1 P10 to P17 •8-bit input/output port Input/output can be specified in a bit •Other functions P10 P11 I/O P12 P13 P14 P15 P17 SIO0 data output SIO0 data input/bus input/output SIO0 clock input/output PWM1 output PWM2 output PWM3 output Timer1 (PWM) output Output Format CMOS/Nch-OD Port 6 P60 to P63 •4-bit input/output port Input/output can be specified for each bit •Other functions I/O P60 P61 P62 P63 IIC0 data I/O IIC0 clock output IIC1 data I/O IIC1 clock output Continued on next page. No.A0115-8/21 LC863264C/56C/48C/40C/32C/28C/24C/20C/16C Continued from preceding page. Terminal Port 7 P70 P71 to P73 I/O I/O •4-bit input/output port Input or output can be specified for each bit •Other functions P70 P71 P72 P73 INT0 input/HOLD release input/ Nch-Tr. output for watchdog timer INT1 input/HOLD release input INT2 input/Timer 0 event input INT3 input (noise rejection filter connected)/ Timer 0 event input Interrupt receiver format, vector addresses Rising INT0 INT1 INT2 INT3 Port 8 P84 to P87 I/O enable enable enable enable Falling enable enable enable enable Rising/ Falling disable disable enable enable H level enable enable disable disable L level enable enable disable disable Vector 03H 0BH 13H 1BH Function Description Option •4-bit input/output port Input or output can be specified for each bit •Other function AD converter input port (4 lines) NC - Unused terminal Leave open • Output form and existence of pull-up resistor for all ports can be specified for each bit. • Programmable pull-up resistor is always connected regardless of port option, CMOS or N-ch open drain output in port 1. Port status in reset Terminal Port 0 Port 1 I/O I I Pull-up resistor status at selecting pull-up option Pull-up resistor OFF, ON after reset release Programmable pull-up resistor OFF No.A0115-9/21 LC863264C/56C/48C/40C/32C/28C/24C/20C/16C Absolute Maximum Ratings / Ta = 25°C, VSS = 0V Parameter Maximum supply voltage Input voltage Output voltage Input/output voltage High level output current Total output current Low level output current Peak output current Total output current Maximum power dissipation Operating temperature range Storage temperature range Tstg -55 +125 Topr -10 +70 ºC ΣIOAH(1) ΣIOAH(2) ΣIOAH(3) IOPL(1) IOPL(2) IOPL(3) ΣIOAL(1) ΣIOAL(2) ΣIOAL(3) Pd max Ports 0, 1 Ports 7, 8 R, G, B, I, BL Ports 0, 1, 6, 8 Port 7 R, G, B, I, BL Ports 0, 1 Ports 6, 7, 8 R, G, B, I, BL DIP42S QIP48E Peak output current IOPH(2) R, G, B, I, BL VI(1) VO(1) VIO IOPH(1) RES , HS , VS , CVIN Symbol VDD max VDD Pins Conditions Ratings VDD[V] min -0.3 -0.3 -0.3 -0.3 typ max +6.5 VDD+0.3 VDD+0.3 VDD+0.3 unit V R, G, B, I, BL, FILT Ports 0, 1, 6, 7, 8 Ports 0, 1, 7, 8 •CMOS output •For each pin. •CMOS output •For each pin. Total of all pins. Total of all pins. Total of all pins. For each pin. For each pin. For each pin. Total of all pins. Total of all pins. Total of all pins. Ta=-10 to +70ºC -4 -5 -20 -10 -15 20 15 5 40 40 15 715 385 mW mA No.A0115-10/21 LC863264C/56C/48C/40C/32C/28C/24C/20C/16C Recommended Operating Range / Ta = -10°C to +70°C, VSS = 0V Parameter Operating supply voltage range Hold voltage VDD(2) VHD VDD Symbol VDD(1) VDD Pins Conditions 0.844µs ≤ tCYC ≤ 0.852µs 4µs ≤ tCYC ≤ 400µs RAMs and the registers data are kept in HOLD mode. High level input voltage VIH(1) VIH(2) Port 0 (Schumitt) •Ports 1,6 (Schumitt) •Port 7 (Schumitt) port input/interrupt • HS , VS RES , (Schumitt) VIH(3) VIH(4) Low level input voltage VIL(1) VIL(2) Port 70 Watchdog timer input •Port 8 port input Port 0 (Schumitt) •Ports 1,6 (Schumitt) •Port 7 (Schumitt) port input/interrupt • HS , VS RES , (Schumitt) VIL(3) VIL(4) CVIN Operation cycle time tCYC(2) VCVIN tCYC(1) Port 70 Watchdog timer input Port 8 port input CVIN •All functions operating •AD converter operating •OSD and Data slicer are not operating tCYC(3) •OSD, AD converter and Data slicer are not operating Oscillation frequency range FmRC Internal RC oscillation 4.5 to 5.5 0.4 0.8 3.0 MHz 4.5 to 5.5 0.844 400 4.5 to 5.5 0.844 30 µs Output disable Output disable 4.5 to 5.5 4.5 to 5.5 5.0 4.5 to 5.5 VSS VSS 1Vp-p -3dB 0.844 1Vp-p 0.848 0.6VDD 0.3VDD 1Vp-p +3dB 0.852 Vp-p* Output disable Output disable 4.5 to 5.5 VSS 0.25VDD Output disable Output disable 4.5 to 5.5 4.5 to 5.5 4.5 to 5.5 VDD-0.5 0.7VDD VSS VDD VDD 0.2VDD V Output disable Output disable 4.5 to 5.5 0.75VDD VDD 4.5 to 5.5 0.6VDD VDD 2.0 5.5 Ratings VDD[V] min 4.5 4.5 typ max 5.5 5.5 unit * Vp-p : Peak-to-peak voltage No.A0115-11/21 LC863264C/56C/48C/40C/32C/28C/24C/20C/16C Electrical Characteristics / Ta = -10°C to +70°C, VSS = 0V Parameter High level input current Symbol IIH(1) Pins Ports 0, 1, 6, 7, 8 Conditions •Output disable •Pull-up MOS Tr. OFF •VIN=VDD (including the offleak current of the output Tr.) IIH(2) Low level input current IIL(1) • RES • HS , VS Ports 0, 1, 6, 7, 8 •Output disable •Pull-up MOS Tr. OFF •VIN=VSS (including the offleak current of the output Tr.) IIL(2) High level output voltage VOH(2) Low level output voltage VOL(1) VOL(2) VOL(3) VOL(4) VOL(5) Pull-up MOS Tr. resistance Bus terminal short circuit resistance (SCL0-SCL1, SDA0-SDA1) Hysteresis voltage Input clump voltage Pin capacitance CP All pins •f=1MHz •Every other terminals are connected to VSS. •Ta=25ºC 4.5 to 5.5 10 pF VCLMP VHYS •Ports 0, 1, 6, 7 • RES • HS , VS CVIN 5.0 2.3 2.5 2.7 Output disable 4.5 to 5.5 0.1VDD V RBS •P60 to P62 •P61 to P63 4.5 to 5.5 130 300 Ω Rpu VOH(1) • RES • HS , VS •CMOS output of ports 0, 1, 71 to 73 R, G, B, I, BL Ports 0, 1, 71 to 73 Ports 0, 1, 71 to 73 •R, G, B, I, BL •Port 6 Port 6 Port 70 Ports 0, 1, 7, 8 IOL=6.0mA IOL=1mA VOH=0.9VDD IOH=-0.1mA IOL=10mA IOL=1.6mA IOL=3.0mA IOH=-1.0mA VIN=VSS 4.5 to 5.5 4.5 to 5.5 4.5 to 5.5 4.5 to 5.5 4.5 to 5.5 4.5 to 5.5 4.5 to 5.5 4.5 to 5.5 4.5 to 5.5 13 38 -1 VDD-1 VDD-0.5 1.5 0.4 0.4 0.6 0.4 80 kΩ V 4.5 to 5.5 -1 •VIN=VDD 4.5 to 5.5 1 µA 4.5 to 5.5 1 Ratings VDD[V] min typ max unit No.A0115-12/21 LC863264C/56C/48C/40C/32C/28C/24C/20C/16C Serial Input/Output Characteristics / Ta = -10°C to +70°C, VSS = 0V Parameter Cycle Input clock Low Level pulse width High Level pulse width Cycle Output clock Low Level pulse width High Level pulse width Data set up time Serial input tICK SI0 •Data set-up to SCK0. •Data hold from Data hold time tCKI SCK0. •Refer to figure 4. Output delay time Serial output (Using external clock) tCKO(1) SO0 •Data hold from SCK0. •Use pull-up Output delay time (Using internal clock) tCKO(2) SO0 resistor (1kΩ) when Nch opendrain output. •Refer to figure 4. 4.5 to 5.5 1/3tCYC +0.2 4.5 to 5.5 7/12tCYC +0.2 4.5 to 5.5 0.1 µs 0.1 tCKH(2) tCKCY(2) tCKL(2) •SCK0 •SCLK0 •Use pull-up resistor (1kΩ) when Nch opendrain output. •Refer to figure 4. 4.5 to 5.5 tCKH(1) Symbol tCKCY(1) tCKL(1) Pins •SCK0 •SCLK0 4.5 to 5.5 Conditions Refer to figure 4. Ratings VDD[V] min 2 1 1 tCYC 2 1/2tCKCY 1/2tCKCY typ max unit IIC Input/Output Conditions / Ta = -10°C to +70°C, VSS = 0V Parameter SCL Frequency BUS free time between stop - start HOLD time of start, restart condition L time of SCL H time of SCL Set-up time of restart condition HOLD time of SDA Set-up time of SDA Rising time of SDA, SCL Falling time of SDA, SCL Set-up time of stop condition fSCL tBUF tHD;STA tLOW tHIGH tSU;STA tHD;DAT tSU;DAT tR tF tSU;STO Symbol Standard min 0 4.7 4.0 4.7 4.0 4.7 0 250 4.0 max 100 1000 300 High speed min 0 1.3 0.6 1.3 0.6 0.6 0 100 20+0.1Cb 20+0.1Cb 0.6 max 400 0.9 300 300 unit kHz µs µs µs µs µs µs ns ns ns µs Refer to figure 10 Note 1: Cb : Total capacitance of all BUS (unit : pF) Serial clock No.A0115-13/21 LC863264C/56C/48C/40C/32C/28C/24C/20C/16C Pulse Input Conditions / Ta = -10°C to +70°C, VSS = 0V Parameter High/low level pulse width Symbol tPIH(1) tPIL(1) tPIH(2) tPIL(2) tPIH(3) tPIL(3) tPIH(4) tPIL(4) tPIL(5) tPIH(6) tPIL(6) •INT0, INT1 •INT2/T0IN INT3/T0IN (1tCYC is selected for noise rejection clock.) INT3/T0IN (16tCYC is selected for noise rejection clock.) INT3/T0IN (64tCYC is selected for noise rejection clock.) RES HS , VS Pins Conditions •Interrupt acceptable •Timer0-countable •Interrupt acceptable •Timer0-countable •Interrupt acceptable •Timer0-countable •Interrupt acceptable •Timer0-countable Reset acceptable •Display position controllable •The active edge of HS and VS must be apart Ratings VDD[V] 4.5 to 5.5 min 1 typ max unit 4.5 to 5.5 2 tCYC 4.5 to 5.5 32 4.5 to 5.5 4.5 to 5.5 128 200 4.5 to 5.5 8 µs at least 1tCYC. •Refer to figure 6. Rising/falling time tTHL tTLH HS Refer to figure 6. 4.5 to 5.5 500 ns AD Converter Characteristics / Ta = -10°C to +70°C, VSS = 0V Parameter Resolution Absolute precision Conversion time tCAD ADCR2=0 (Note 3) ADCR2=1 (Note 3) Analog input voltage range Analog port input current IAINH IAINL VAIN=VDD VAIN=VSS -1 VAIN AN4 to AN7 4.5 to 5.5 VSS 16 32 VDD 1 Symbol N ET (Note 2) Pins Conditions Ratings VDD[V] min typ 8 ±1.5 max unit bit LSB tCYC V µA Note 2: Absolute precision does not include quantizing error (1/2LSB). Note 3: Conversion time is the time till the complete digital conversion value for analog input value is set to a register after the instruction to start conversion is sent. No.A0115-14/21 LC863264C/56C/48C/40C/32C/28C/24C/20C/16C Sample Current Dissipation Characteristics / Ta= -10°C to +70°C, VSS=0V The sample current dissipation characteristics is the measurement result of Sanyo provided evaluation board when the recommended circuit parameters shown in the sample oscillation circuit characteristics are used externally. The currents through the output transistors and the pull-up MOS transistors are ignored. Parameter Current dissipation during basic operation (Note 4) Current dissipation in HALT mode (Note 4) IDDHALT(1) VDD Symbol IDDOP(1) Pins VDD Conditions •FmX’tal=32.768kHz X’tal oscillation •System clock : VCO •VCO for OSD operating •Internal RC oscillation stops •HALT mode •FmX’tal=32.768kHz X’tal oscillation •System clock : VCO •VCO for OSD stops •Internal RC oscillation stops IDDHALT(2) VDD •HALT mode •FmX’tal=32.768kHz X’tal oscillation •VCO for system stops •VCO for OSD stops •System clock : Internal RC IDDHALT(3) VDD •HALT mode •FmX’tal=32.768kHz X’tal oscillation •VCO for system stops •VCO for OSD stops •System clock : X’tal Current dissipation in HOLD mode (Note 4) IDDHOLD VDD •HOLD mode •All oscillation stops. 4.5 to 5.5 0.05 20 µA 4.5 to 5.5 45 200 µA 4.5 to 5.5 300 1000 4.5 to 5.5 3 9 mA 4.5 to 5.5 10 24 mA Ratings VDD[V] min typ max unit Note 4: The currents through the output transistors and the pull-up MOS transistors are ignored. No.A0115-15/21 LC863264C/56C/48C/40C/32C/28C/24C/20C/16C Recommended Oscillation Circuit and Sample Characteristics The sample oscillation circuit characteristics in the table below is based on the following conditions: Recommended circuit parameters are verified by an oscillator manufacturer using a Sanyo provided oscillation evaluation board. Sample characteristics are the result of the evaluation with the recommended circuit parameters connected externally. Recommended oscillation circuit and sample characteristics (Ta = -10 to +70°C) Frequency 32.768kHz Manufacturer SEIKO EPSON Oscillator C1 C-002RX 18pF Recommended circuit parameters C2 18pF Rf OPEN Rd 390kΩ Operating supply voltage range 4.5 to 5.5V Oscillation stabilizing time typ 1.0s max 1.5s Notes Notes: The oscillation stabilizing time period is the time until the VCO oscillation for the internal system becomes stable after the following conditions. (Refer to Figure 2.) 1. The VDD becomes higher than the minimum operating voltage after the power is supplied. 2. The HOLD mode is released. The sample oscillation circuit characteristics may differ applications. For further assistance, please contact with oscillator manufacturer with the following notes in your mind. • Since the oscillation frequency precision is affected by wiring capacity of the application board, etc., adjust the oscillation frequency on the production board. • The above oscillation frequency and the operating supply voltage range are based on the operating temperature of -10°C to +70°C. For the use with the temperature outside of the range herein, or in the applications requiring high reliability such as car products, please consult with oscillator manufacturer. • When using the oscillator which is not shown in the sample oscillation circuit characteristics, please consult with Sanyo sales personnel. Since the oscillation circuit characteristics are affected by the noise or wiring capacity because the circuit is designed with low gain in order to reduce the power dissipation, refer to the following notices. • The distance between the clock I/O terminal (XT1 terminal XT2 terminal) and external parts should be as short as possible. • The capacitors’ VSS should be allocated close to the microcontroller’s GND terminal and be away from other GND. • The signal lines with rapid state changes or with large current should be allocated away from the oscillation circuit. XT1 Rf XT2 Rd C1 X’tal C2 Figure 1 Recommended Oscillation Circuit No.A0115-16/21 LC863264C/56C/48C/40C/32C/28C/24C/20C/16C Power supply VDD VDD limit 0V Reset time RES Internal RC resonator oscillation XT1,XT2 tmsVCO VCO for system stable Operation mode Unfixed Reset Instruction execution mode Reset Time and Oscillation Stabilizing Time HOLD release signal Valid Internal RC resonator oscillation XT1, XT2 tmsVCO VCO for system stable Operation mode HOLD Instruction execution mode HOLD Release Signal and Oscillation Stabilizing Time Figure 2 Oscillation Stabilizing Time No.A0115-17/21 LC863264C/56C/48C/40C/32C/28C/24C/20C/16C VDD RRES RES CRES Note: Determine the CRES, RRES value to generate more than 200µs reset time. Figure 3 Reset Circuit 0.5VDD AC Timing Measurement Point tCKCY tCKL SCK0 tICK SI0 tCKO SO0 SB0 tCKI tCKH VDD 1kΩ 50pF Timing Figure 4 Serial Input / Output Test Condition Test load No.A0115-18/21 LC863264C/56C/48C/40C/32C/28C/24C/20C/16C tPIL (1)-(5) tPIH (1)-(4) Figure 5 Pulse Input Timing Condition - 1 tPIL(6) HS 0.75VDD 0.25VDD tTLH VS tPIL(6) more than ±1tCYC Figure 6 Pulse Input Timing Condition - 2 LC863264C 10kΩ HS HS C536 Figure 7 Recommended Interface Circuit No.A0115-19/21 LC863264C/56C/48C/40C/32C/28C/24C/20C/16C Noise filter C-Video 1000pF 200Ω 1µF CVIN Coupling capacitor Output impedance of C-Video before Noise filter should be less then 100Ω. Figure 8 CVIN Recommended Circuit 100Ω FILT 2.2µF + 33000pF 1M Ω Figure 9 FILT Recommended Circuit (Note) Place FILT parts on board as close to the microcontroller as possible. P S Sr P SDA tBUF tHD;STA tR tF tHD;STA tsp SCL tLOW tHD;DAT tHIGH tSU;DAT tSU;STA tSU;STO S : start condition P : stop condition Sr : restart condition tsp : spike suppression Standard mode : not exist High speed mode : less than 50ns Figure 10 IIC Timing No.A0115-20/21 LC863264C/56C/48C/40C/32C/28C/24C/20C/16C This catalog provides information as of July, 2006. Specifications and information herein are subject to change without notice. PS No.A0115-21/21