LC863424C

Ordering number : ENA0117B LC863448C,LC863440C LC863432C,LC863428C LC863424C,LC863420C LC863416C Overview CMOS IC 48K/40K/32K/28K/24K/20K/16K-byte ROM, CGROM16K-byte on-chip 640/512-byte RAM and 352x9 bit OSD RAM 8-bit 1-chip Microcontroller The LC863448C/40C/32C/28C/24C/20C/16C are 8-bit single chip microcontrollers with the following on-chip functional blocks: • CPU: Operable at a minimum bus cycle time of 0.424μs • On-chip ROM capacity Program ROM: 48K/40K/32K/28K/24K/20K/16K bytes CGROM: 16K bytes • On-chip RAM capacity: 640/512 bytes • OSD RAM: 352×9 bits • Closed-Caption TV controller and the on-screen display controller • Closed-Caption data slicer • Four channels×6-bit AD Converter • Three channels×7-bit PWM • 16-bit timer/counter, 14-bit base timer Continued on next page. Note : This product includes the IIC bus interface circuit. If you intend to use the IIC bus interface, please notify us of this in advance of our receiving your program ROM code order. Purchase of SANYO IIC components conveys a license under the Philips IIC Patents Rights to use these components in an IIC system, provided that the system conforms to the IIC Standard Specification as defined by Philips. Trademarks IIC is a trademark of Philips Corporation. Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment (home appliances, AV equipment, communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee thereof. If you should intend to use our products for applications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our customer shall be solely responsible for the use. Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer' s products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer' s products or equipment. Ver.1.00 O0108HKIM 20080916-S00001 No.A0117-1/18 LC863448C/40C/32C/28C/24C/20C/16C Continued from preceding page. • IIC-bus compliant serial interface circuit (Multi-master type) • ROM correction function • 12-source 8-vectored interrupt system • Integrated system clock generator and display clock generator Only one X’tal oscillator (32.768kHz) for PLL reference is used for both generators TV control and the Closed Caption function All of the above functions are fabricated on a single chip. Features Read-Only Memory (ROM): 49152×8 bits / 40960×8 bits / 32768×8 bits / 28672×8 bits / 24576×8 bits / 20480×8 bits / 16384×8 bits for program 16128×8 bits for CGROM 512×8 bits (working area) : LC863448C/40C 384×8 bits (working area) : LC863432C/28C/24C/20C/16C 128×8 bits (working or ROM correction function) 352×9 bits (for CRT display) Random Access Memory (RAM): OSD Functions • Screen display : 36 characters×16 lines (by software) • RAM : 352 words (9 bits per word) Display area : 36 words×8 lines Control area : 8 words×8 lines • Characters Up to 252 kinds of 16×32 dot character fonts (4 characters including 1 test character are not programmable) Each font can be divided into two parts and used as two fonts (Ex. 16×16 dot character font×2) At least 111 characters need to be divide between a 16×17 dot and 8×9 dot character font to display the caption fonts. • Various character attributes Character colors : 16colors (analog mode: lVp-p output ) / 8colors (digital mode) Character background colors : 16colors (analog mode: lVp-p output ) / 8colors (digital mode) Fringe / shadow colors : 16colors (analog mode: lVp-p output ) / 8colors (digital mode) Full screen colors : 16colors (analog mode: lVp-p output ) / 8colors (digital mode) Rounding Underline Italic character (slanting) • Attribute can be changed without spacing • Vertical display start line number can be set for each row independently (Rows can be overlapped) • Horizontal display start position can be set for each row independently • Horizontal pitch (9 to 16 dots)*1 and vertical pitch (1 to 32 dots) can be set for each row independently • Different display modes can be set for each row independently Caption • Text mode / OSD mode 1 / OSD mode 2 (Quarter size) / Simplified graphic mode • Ten character sizes *1 Horez. × Vert. = (1×1), (1×2), (2×2), (2×4), (0.5×0.5) (1.5×1), (1.5×2), (3×2), (3×4), (0.75×0.5) • Shuttering and scrolling on each row • Simplified Graphic Display Note *1: range depends on display mode : refer to the manual for details. Data Slicer (closed caption format) • Closed caption data and XDS data extraction • NTSC/PAL, and extracted line can be specified No.A0117-2/18 LC863448C/40C/32C/28C/24C/20C/16C Bus Cycle Time / Instruction-Cycle Time Bus Cycle Time 0.424μs 7.5μs 91.55μs 183.1μs Instruction Cycle Time 0.848μs 15.0μs 183.1μs 366.2μs Clock Divider 1/2 1/2 1/1 1/2 System Clock Oscillation Internal VCO (Ref: X'tal 32.768kHz) Internal RC Crystal Crystal Oscillation Frequency 14.156MHz 800kHz 32.768kHz 32.768kHz Voltage 4.5V to 5.5V 4.5V to 5.5V 4.5V to 5.5V 4.5V to 5.5V Ports • Input / Output Ports : 4 ports (23 terminals) Data direction programmable in nibble units : 1 port (8 terminals) (If the N-ch open drain output is selected by option, the corresponding port data can be read in output mode.) Data direction programmable for each bit individually : 3 ports (15 terminals) AD Converter • 4 channels×6-bit AD converters Serial Interfaces • IIC-bus compliant serial interface (Multi-master type) Consists of a single built-in circuit with two I/O channels. The two data lines and two clock lines can be connected internally. PWM Output • 3 channels×7-bit PWM Timer • Timer 0: 16-bit timer/counter With 2-bit prescaler + 8-bit programmable prescaler Mode 0: Two 8-bit timers with a programmable prescaler Mode 1: 8-bit timer with a programmable prescaler + 8-bit counter Mode 2: 16-bit timer with a programmable prescaler Mode 3: 16-bit counter The resolution of timer is 1 tCYC. • Base Timer Generate every 500ms overflow for a clock application (using 32.768kHz crystal oscillation for the base timer clock) Generate every 976μs, 3.9ms, 15.6ms, 62.5ms overflow (using 32.768kHz crystal oscillation for the base timer clock) Clock for the base timer is selectable from 32.768kHz crystal oscillation, system clock or programmable prescaler output of Timer 0 Remote Control Receiver Circuit (connected to the P73/INT3/T0IN terminal) • Noise rejection function • Polarity switching Watchdog Timer External RC circuit is required Interrupt or system reset is activated when the timer overflows ROM Correction Function Max 128 bytes / 2 addresses No.A0117-3/18 LC863448C/40C/32C/28C/24C/20C/16C Interrupts • 12 sources 8 vectored interrupts 1. External Interrupt INT0 2. External Interrupt INT1 3. External Interrupt INT2, Timer/counter T0L (Lower 8 bits) 4. External Interrupt INT3, base timer 5. Timer/counter T0H (Upper 8 bits) 6. Data slicer 7. Vertical synchronous signal interrupt (VS), horizontal line (HS) 8. IIC, Software • Interrupt Priority Control Three interrupt priorities are supported (low, high and highest) and multi-level nesting is possible. Low or high priority can be assigned to the interrupts from 3 to 8 listed above. For the external interrupt INT0 and INT1, low or highest priority can be set. Sub-routine Stack Level • A maximum of 128 levels (stack is built in the internal RAM) Multiplication/Division Instruction • 16 bits×8 bits (7 instruction cycle times) • 16 bits÷8 bits (7 instruction cycle times) 3 Oscillation Circuits • Built-in RC oscillation circuit used for the system clock • Built-in VCO circuit used for the system clock and OSD • X’tal oscillation circuit used for base timer, system clock and PLL reference Standby Function • HALT mode The HALT mode is used to reduce the power dissipation. In this operation mode, the program execution is stopped. This mode can be released by the interrupt request or the system reset. • HOLD mode The HOLD mode is used to stop the oscillations; RC (internal), VCO, and X’tal oscillations. This mode can be released by the following conditions. - Pull the reset terminal (RES) to low level. - Feed the selected level to either P70/INT0 or P71/INT1. Package • MFP36SDJ(375mil) • DIP36S(400mil) Development Tools • Flash EEPROM: • Evaluation chip: • Emulator: : Lead-free type : Lead-free type LC86F3448B LC863096 EVA86000 (main) + ECB863200A (evaluation chip board) + SUB863400A (sub board) + POD36-CABLE (cable) + POD36-DIP (for DIP36S) or POD36-MFP (for MFP36SDJ) No.A0117-4/18 LC863448C/40C/32C/28C/24C/20C/16C Package Dimensions unit : mm (typ) 3263 15.2 36 19 10.5 7.9 1 (0.8) 0.8 0.3 18 0.25 SANYO : MFP36SDJ(375mil) Package Dimensions unit : mm (typ) 3170A 32.4 36 19 0.1 (2.25) 2.45max 0.65 0.95 3.0 3.95max 0.51min (3.25) 1.78 0.48 (1.1) SANYO : DIP36S(400mil) 0.25 1 18 10.16 8.6 No.A0117-5/18 LC863448C/40C/32C/28C/24C/20C/16C Pin Assignment P10/SDA0 P11/SCLK0 P12/SDA1 P13/SCLK1 VSS XT1 XT2 VDD P04/AN4 P05/AN5 P06/AN6 P07/AN7 RES FILT CVIN P30 VS HS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 36 35 34 33 32 31 P03 P02 P01 P00 P17 P16/PWM3 P15/PWM2 P14/PWM1 P73/INT3/T0IN P72/INT2/T0IN P71/INT1 P70/INT0 P32 P31 BL B G R LC863448C LC863440C LC863432C LC863428C LC863424C LC863420C LC863416C 30 29 28 27 26 25 24 23 22 21 20 19 Top view SANYO: MFP36SDJ(375mil) “Lead-free Type” SANYO: DIP36S(400mil) “Lead-free Type” No.A0117-6/18 LC863448C/40C/32C/28C/24C/20C/16C System Block Diagram Interrupt Control IR PLA Standby Control ROM RC VCO Clock Generator X’tal PC PLL IIC ROM Correct Control ACC XRAM B Register Timer 0 Bus Interface C Register Port 1 ALU Base Timer Port 3 ADC Port 7 PSW INT0-3 Noise Rejection Filter RAR PWM CGROM RAM OSD Control Circuit Data Slicer Stack Pointer VRAM Port 0 Watchdog Timer No.A0117-7/18 LC863448C/40C/32C/28C/24C/20C/16C Pin Description Pin Description Table Terminal VSS XT1 XT2 VDD RES FILT CVIN VS HS I/O I O I O I I I O O O O I/O Negative power supply Function Description Option Input terminal for crystal oscillator Output terminal for crystal oscillator Positive power supply Reset terminal Filter terminal for PLL Video signal input terminal Vertical synchronization signal input terminal Horizontal synchronization signal input terminal Red (R) output terminal of RGB image output Green (G) output terminal of RGB image output Blue (B) output terminal of RGB image output Fast blanking control signal Switch TV image signal and caption/OSD image signal • 8-bit input/output port, Input/output can be specified in nibble unit (If the N-ch open drain output is selected by option, the corresponding port data can be read in output mode.) • Other functions AD converter input port (P04 to P07: 4 channels) Pull-up resistor provided/not provided Output Format CMOS/Nch-OD R G B BL Port 0 P00 to P07 Port 1 P10 to P17 I/O • 8-bit input/output port Input/output can be specified for each bit (programmable pull-up resister provided) • Other functions P10 P11 P12 P13 P14 P15 P16 IIC0 data I/O IIC0 clock output IIC1 data I/O IIC1 clock output PWM1 output PWM2 output PWM3 output Output Format CMOS/Nch-OD Port 3 P30 to P32 Port 7 P70 P71 to P73 I/O • 3-bit input/output port Input/output can be specified for each bit (CMOS output/input with programmable pull-up resister) I/O • 4-bit input/output port Input or output can be specified for each bit P70: I/O with programmable pull-up resister P71 to P73: CMOS output/input with programmable pull-up resister • Other functions P70 P71 P72 P73 INT0 input/HOLD release input/ Nch-Tr. output for watchdog timer INT1 input/HOLD release input INT2 input/Timer 0 event input INT3 input (noise rejection filter connected)/ Timer 0 event input Interrupt receiver format, vector addresses Rising INT0 INT1 INT2 INT3 enable enable enable enable Falling enable enable enable enable Rising/ Falling disable disable enable enable H level enable enable disable disable L level enable enable disable disable Vector 03H 0BH 13H 1BH Note: A capacitor of at least 10µF must be inserted between VDD and VSS when using this IC. No.A0117-8/18 LC863448C/40C/32C/28C/24C/20C/16C • Output form and existence of pull-up resistor for all ports can be specified for each bit. • Programmable pull-up resistor is always connected regardless of port option, CMOS or N-ch open drain output in port 1. • Port status in reset Terminal Port 0 Port 1 I/O I I Pull-up resistor status at selecting CMOS output option Pull-up resistor OFF, ON after reset release Programmable pull-up resistor OFF Absolute Maximum Ratings at Ta = 25°C, VSS = 0V Parameter Maximum supply voltage Input voltage Output voltage Input/output voltage High level output current Total output current Low level output current Total output current Maximum power dissipation Operating temperature range Storage temperature range Tstg -55 +125 Topr -10 +70 °C Peak output current ΣIOAH(1) ΣIOAH(2) ΣIOAH(3) IOPL(1) IOPL(2) IOPL(3) ΣIOAL(1) ΣIOAL(2) ΣIOAL(3) Pd max Ports 0, 1 Ports 3, 7 R, G, B, BL Ports 0, 1, 3 Port 7 R, G, B, BL Ports 0, 1 Ports 3, 7 R, G, B, BL MFP36SDJ(375mil) DIP36S(400mil) Peak output current IOPH(2) R, G, B, BL VI(1) VO(1) VIO IOPH(1) RES , HS , VS , CVIN Symbol VDD max VDD Pins Conditions Ratings VDD[V] min -0.3 -0.3 -0.3 -0.3 typ max +6.5 VDD+0.3 VDD+0.3 VDD+0.3 unit V R, G, B, BL, FILT Ports 0, 1, 3, 7 Ports 0, 1, 3, 7 •CMOS output •For each pin. •CMOS output •For each pin. Total of all pins. Total of all pins. Total of all pins. For each pin. For each pin. For each pin. Total of all pins. Total of all pins. Total of all pins. Ta=-10 to +70°C -4 -5 -20 -10 -12 20 15 5 40 20 12 360 610 mW mA No.A0117-9/18 LC863448C/40C/32C/28C/24C/20C/16C Recommended Operating Range at Ta = -10°C to +70°C, VSS = 0V Parameter Operating supply voltage range Hold voltage VDD(2) VHD VDD Symbol VDD(1) VDD Pins Conditions 0.844μs ≤ tCYC ≤ 0.852μs 4μs ≤ tCYC ≤ 400μs RAMs and the registers data are kept in HOLD mode. High level input voltage VIH(1) VIH(2) Port 0 • Ports 1, 3 (Schumitt) • Port 7 (Schumitt) port input/interrupt • HS , VS , RES (Schumitt) VIH(3) Low level input voltage VIL(1) VIL(2) Port 70 Watchdog timer input Port 0 • Ports 1, 3 (Schumitt) • Port 7 (Schumitt) port input/interrupt • HS , VS , RES (Schumitt) VIL(3) CVIN Operation cycle time tCYC(2) VCVIN tCYC(1) Port 70 Watchdog timer input CVIN • All functions operating • OSD and Data slicer are not operating Oscillation frequency range FmRC Internal RC oscillation 4.5 to 5.5 0.4 0.8 3.0 MHz 4.5 to 5.5 0.844 400 Output disable 4.5 to 5.5 5.0 4.5 to 5.5 VSS 0.7Vp-p 0.844 1Vp-p 0.848 0.6VDD 1.4Vp-p 0.852 μs Vp-p* Output disable Output disable 4.5 to 5.5 VSS 0.25VDD Output disable 4.5 to 5.5 4.5 to 5.5 VDD-0.5 VSS VDD 0.2VDD Output disable Output disable 4.5 to 5.5 0.75VDD VDD V 4.5 to 5.5 0.6VDD VDD 2.0 5.5 Ratings VDD[V] min 4.5 4.5 typ max 5.5 5.5 unit * Vp-p: Peak-to-peak voltage No.A0117-10/18 LC863448C/40C/32C/28C/24C/20C/16C Electrical Characteristics at Ta = -10°C to +70°C, VSS = 0V Parameter High level input current Symbol IIH(1) Pins Ports 0, 1, 3, 7 Conditions •Output disable •Pull-up MOS Tr. OFF •VIN=VDD (including the off-leak current of the output Tr.) IIH(2) Low level input current IIL(1) • RES • HS , VS Ports 0, 1, 3, 7 •Output disable •Pull-up MOS Tr. OFF •VIN=VSS (including the off-leak current of the output Tr.) IIL(2) High level output voltage VOH(2) Low level output voltage VOL(1) VOL(2) VOL(3) VOL(4) Pull-up MOS Tr. resistance Bus terminal short circuit resistance (SCL0-SCL1, SDA0-SDA1) Hysteresis voltage Input clump voltage Pin capacitance CP All pins • f=1MHz • Every other terminals are connected to VSS. • Ta=25ºC 4.5 to 5.5 10 pF VCLMP VHYS • Ports 1, 3, 7 • RES • HS , VS CVIN 5.0 2.3 2.5 2.7 Output disable 4.5 to 5.5 0.1VDD V RBS • P10 to P12 • P11 to P13 4.5 to 5.5 130 300 Ω Rpu VOH(1) • RES • HS , VS • CMOS output of ports 0, 1, 3, 71 to 73 R, G, B, BL Ports 0, 1, 3, 71 to 73 Ports 0, 3, 71 to 73 • R, G, B, BL • Port 1 Port 70 Ports 0, 1, 3, 7 IOH=-0.1mA R. G. B: digital mode IOL=10mA IOL=1.6mA IOL=3.0mA R. G. B: digital mode IOL=1mA VOH=0.9VDD IOH=-1.0mA VIN=VSS 4.5 to 5.5 4.5 to 5.5 4.5 to 5.5 4.5 to 5.5 4.5 to 5.5 4.5 to 5.5 4.5 to 5.5 4.5 to 5.5 13 38 -1 VDD-1 VDD-0.5 1.5 0.4 0.4 0.4 80 kΩ V 4.5 to 5.5 -1 •VIN=VDD 4.5 to 5.5 1 μA 4.5 to 5.5 1 Ratings VDD[V] min typ max unit No.A0117-11/18 LC863448C/40C/32C/28C/24C/20C/16C IIC Input/Output Conditions at Ta = -10°C to +70°C, VSS = 0V Parameter SCL Frequency BUS free time between stop - start HOLD time of start, restart condition L time of SCL H time of SCL Set-up time of restart condition HOLD time of SDA Set-up time of SDA Rising time of SDA, SCL Falling time of SDA, SCL Set-up time of stop condition fSCL tBUF tHD;STA tLOW tHIGH tSU;STA tHD;DAT tSU;DAT tR tF tSU;STO Symbol min 0 4.7 4.0 4.7 4.0 4.7 0 250 4.0 Standard max 100 1000 300 min 0 1.3 0.6 1.3 0.6 0.6 0 100 20+0.1Cb 20+0.1Cb 0.6 High speed max 400 0.9 300 300 kHz μs μs μs μs μs μs ns ns ns μs unit Refer to figure 8 Note 1: Cb: Total capacitance of all BUS (unit : pF) Pulse Input Conditions at Ta = -10°C to +70°C, VSS = 0V Parameter High/low level pulse width Symbol tPIH(1) tPIL(1) tPIH(2) tPIL(2) tPIH(3) tPIL(3) tPIH(4) tPIL(4) tPIL(5) tPIH(6) tPIL(6) Pins • INT0, INT1 • INT2/T0IN INT3/T0IN (1tCYC is selected for noise rejection clock.) INT3/T0IN (16tCYC is selected for noise rejection clock.) INT3/T0IN (64tCYC is selected for noise rejection clock.) RES HS , VS Conditions VDD[V] •Interrupt acceptable •Timer0-countable •Interrupt acceptable •Timer0-countable •Interrupt acceptable •Timer0-countable •Interrupt acceptable •Timer0-countable Reset acceptable •Display position controllable •The active edge of HS and VS must be apart Ratings min 1 typ max unit 4.5 to 5.5 4.5 to 5.5 2 tCYC 4.5 to 5.5 32 4.5 to 5.5 4.5 to 5.5 128 200 4.5 to 5.5 3 μs at least 1tCYC. •Refer to figure 4. Rising/falling time tTHL tTLH HS Refer to figure 4. 4.5 to 5.5 500 ns AD Converter Characteristics at Ta = -10°C to +70°C, VSS = 0V Parameter Resolution Absolute precision Conversion time tCAD Vref selection to conversion finish Analog input voltage range Analog port input current IAINH IAINL VAIN=VDD VAIN=VSS -1 VAIN AN4 to AN7 1 bit conversion time=2×Tcyc 4.5 to 5.5 VSS 1.69 Symbol N ET (Note 2) Pins Conditions Ratings VDD[V] min typ 6 ±1 max unit bit LSB μs VDD 1 V μA Note 2: Absolute precision does not include quantizing error (1/2LSB). No.A0117-12/18 LC863448C/40C/32C/28C/24C/20C/16C Analog Mode RGB Characteristics at Ta = -10°C to +70°C, VSS = 0V Parameter Analog output voltage Symbol Pins R.G.B Analog output mode Time setting R.G.B Hi level output 70% 10pf load Conditions Low level output Intensity output 5.0 Ratings VDD[V] min. 0.45 0.90 1.35 typ. 0.5 1.0 1.5 max. 0.55 1.10 1.65 50 ns V unit Sample Current Dissipation Characteristics at Ta = -10°C to +70°C, VSS = 0V The sample current dissipation characteristics is the measurement result of Sanyo provided evaluation board when the recommended circuit parameters shown in the sample oscillation circuit characteristics are used externally. The currents through the output transistors and the pull-up MOS transistors are ignored. Parameter Current dissipation during basic operation (Note 3) Symbol IDDOP(1) Pins VDD Conditions • FmX’tal=32.768kHz X’tal oscillation • System clock : VCO • VCO for OSD operating • OSD is Digital mode • Internal RC oscillation stops IDDOP(2) VDD • FmX’tal=32.768kHz X’tal scillation • System clock: VCO • VCO for OSD operating • OSD is Analog mode • Internal RC oscillation stops IDDOP(3) VDD • FmX’tal=32.768kHz X’tal scillation • System clock : X’tal (Instruction cycle time: 366.2µs) • VCO for system VCO for OSD, internal RC oscillation stop • Data slicer, AD converters stop Current dissipation in HALT mode (Note 3) IDDHALT(1) VDD • HALT mode • FmX’tal=32.768kHz X’tal oscillation • System clock : VCO • VCO for OSD stops • Internal RC oscillation stops IDDHALT(2) VDD • HALT mode • FmX’tal=32.768kHz X’tal oscillation • VCO for system stops • VCO for OSD stops • System clock : Internal RC IDDHALT(3) VDD • HALT mode • FmX’tal=32.768kHz X’tal oscillation • VCO for system stops • VCO for OSD stops • System clock: X’tal (Instruction cycle time: 366.2μs) Current dissipation in HOLD mode (Note 3) IDDHOLD VDD • HOLD mode • All oscillation stops. 4.5 to 5.5 0.05 20 μA 4.5 to 5.5 57 200 μA 4.5 to 5.5 300 1000 4.5 to 5.5 3 9 mA 4.5 to 5.5 65 300 μA 4.5 to 5.5 20 35 mA 4.5 to 5.5 11 25 Ratings VDD[V] min typ max unit Note 3: The currents through the output transistors and the pull-up MOS transistors are ignored. No.A0117-13/18 LC863448C/40C/32C/28C/24C/20C/16C Recommended Oscillation Circuit and Sample Characteristics The sample oscillation circuit characteristics in the table below is based on the following conditions: Recommended circuit parameters are verified by an oscillator manufacturer using a Sanyo provided oscillation evaluation board. Sample characteristics are the result of the evaluation with the recommended circuit parameters connected externally. Recommended oscillation circuit and sample characteristics (Ta = -10°C to +70°C) Frequency Manufacturer Oscillator Recommended circuit parameters C1 32.768kHz EPSON TOYOCOM MC-306 18pF C2 18pF Rf OPEN Rd 390kΩ Operating supply voltage range 4.5 to 5.5V Oscillation stabilizing time typ 1.0s max Applicable 1.5s CL value=12.5pF SMD type Notes Notes: The oscillation stabilizing time period is the time until the VCO oscillation for the internal system becomes stable after the following conditions. (Refer to Figure 2.) 1. The VDD becomes higher than the minimum operating voltage after the power is supplied. 2. The HOLD mode is released. The sample oscillation circuit characteristics may differ applications. For further assistance, please contact with oscillator manufacturer with the following notes in your mind. • Since the oscillation frequency precision is affected by wiring capacity of the application board, etc., adjust the oscillation frequency on the production board. • The above oscillation frequency and the operating supply voltage range are based on the operating temperature of -10°C to +70°C. For the use with the temperature outside of the range herein, or in the applications requiring high reliability such as car products, please consult with oscillator manufacturer. • When using the oscillator which is not shown in the sample oscillation circuit characteristics, please consult with Sanyo sales personnel. Since the oscillation circuit characteristics are affected by the noise or wiring capacity because the circuit is designed with low gain in order to reduce the power dissipation, refer to the following notices. • The distance between the clock I/O terminal (XT1 terminal XT2 terminal) and external parts should be as short as possible. • The capacitors’ VSS should be allocated close to the microcontroller’s GND terminal and be away from other GND. • The signal lines with rapid state changes or with large current should be allocated away from the oscillation circuit. XT1 Rf XT2 Rd C1 X’tal C2 Figure 1 Recommended Oscillation Circuit No.A0117-14/18 LC863448C/40C/32C/28C/24C/20C/16C Power supply VDD VDD limit 0V Reset time RES Internal RC resonator oscillation XT1,XT2 tmsVCO VCO for system stable Operation mode Unfixed Reset Instruction execution mode Reset Time and Oscillation Stabilizing Time HOLD release Valid Internal RC resonator oscillation XT1, XT2 tmsVCO VCO for system stable Operation mode HOLD Instruction execution mode HOLD Release Signal and Oscillation Stabilizing Time Figure 2 Oscillation Stabilizing Time No.A0117-15/18 LC863448C/40C/32C/28C/24C/20C/16C tPIL (1)-(5) tPIH (1)-(4) Figure 3 Pulse Input Timing Condition - 1 tPIL(6) HS 0.75VDD 0.25VDD tTLH VS tPIL(6) more than ±1tCYC Figure 4 Pulse Input Timing Condition - 2 LC863448C 10kΩ HS HS C536 Figure 5 Recommended Interface Circuit No.A0117-16/18 LC863448C/40C/32C/28C/24C/20C/16C Noise filter 1μF C-Video 200Ω 1000pF Coupling capacitor CVIN Output impedance of C-Video before Noise filter should be less then 100Ω. Figure 6 CVIN Recommended Circuit 100Ω FILT + 33000pF 2.2μF 1MΩ Figure 7 FILT Recommended Circuit Note: Place FILT parts on board as close to the microcontroller as possible. P S Sr P SDA tBUF tHD;STA tR tF tHD;STA tsp SCL tLOW tHD;DAT tHIGH tSU;DAT tSU;STA tSU;STO S : start condition P : stop condition Sr : restart condition tsp : spike suppression Standard mode : not exist High speed mode : less than 50ns Figure 8 IIC Timing No.A0117-17/18 LC863448C/40C/32C/28C/24C/20C/16C I ≈ mA 1 ↓ I ↓ I ↓ R≈ 500Ω PAD Figure 9 R.G.B. Analog Output Equivalent Circuit SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein. SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO Semiconductor Co.,Ltd. products described or contained herein are controlled under any of applicable local export control laws and regulations, such products may require the export license from the authorities concerned in accordance with the above law. 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SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's intellectual property rights which has resulted from the use of the technical information and products mentioned above. This catalog provides information as of September, 2008. Specifications and information herein are subject to change without notice. PS No.A0117-18/18