LC865628

Ordering number : ENN*6688 CMOS IC LC86P5632 8-Bit Single Chip Microcontroller w ith One-Time Programmable PROM Preliminary Overview The LC86P5632 is a CMOS 8-bit single chip microcontroller with one-time PROM for the LC865600 series. This microcontroller has the function and the pin description of the LC865600 series mask ROM version, and 32K-byte PROM. DIP/QFP package are available for shipping as well as LC865600 series. It is suitable to set up first release, prototyping, developing and testing of set. Features (1) Option switching by PROM data The option function of the LC865600 series can be specified by the PROM data. LC86P5632 can be checked the function of the trial pieces using the mass production board. (2) Internal one-time PROM capacity : 32768 bytes (3) Internal RAM capacity : 512 bytes Used PROM or RAM capacity are equal ROM or RAM capacity of mask ROM version which applies LC86P5632. Mask ROM version LC865632 LC865628 LC865624 LC865620 LC865616 LC865612 LC865608 PROM capacity 32512 bytes 28672 bytes 24576 bytes 20480 bytes 16384 bytes 12288 bytes 8192 bytes RAM capacity 512 bytes 512 bytes 512 bytes 384 bytes 384 bytes 384 bytes 384 bytes Programming service We offers various services at nominal charges. These include the ROM writing, the ROM reading, the package stamping and the screening. Contact our representative for further information. Ver.1.01 22699 91400 RM (IM) HK No.6688-1/23 LC86P5632 (4) Operating supply voltage : 4.5V to 6.0V (5) Instruction cycle time : 0.98µs to 400µs (6) Operating temperature : -30°C to +70°C (7) The pin and the package compatible with the LC865600 series mask ROM devices (8) Applicable mask ROM version : LC865632/ LC865628/ LC865624/LC865620/LC865616/ LC865612/ LC865608 (9) Factory shipment : DIP64S, QFP64E Notice for use LC86P5632 is provided for the first release and small shipping of the LC865600 series. At using, take notice of the followings. (1) A point of difference LC86P5632 and LC865600 series Item Port form at reset Operation after reset releasing LC86P5632 LC865632/28/24/20/16/12/08 Please refer “Port form at reset “ on next page. The option is specified until 3ms The program is executed from 00H of after going to a ‘H’ level to the reset the program counter immediately after terminal by dgrees. The program going to a ‘H’ level to reset terminal. is executed from 00H of the program counter. 4.5V to 6.0V 2.7V to 6.0V Operating supply voltage range (VDD) Total output current [∑IOAH(1)] [∑IOAH(2)] Power dissipation [IDDOP(1)] [IDDOP(2)] [IDDOP(3)] [IDDOP(4)] Refer to ‘electrical characteristics’ on the semiconductor news. • A kind of the option corresponding of the LC86P5632 Contents of the option 1. Input : No pull-up MOS Tr. Output : N-channel open drain 2. Input : Pull-up MOS Tr. Output : CMOS Port 1,2 1. Input : Programmable pull-up MOS Tr. (Specified in a bit) Output : N-channel open drain 2. Input : Programmable pull-up MOS Tr. Output : CMOS Port 3,4,5 1. Input : No Programmable pull-up MOS (Specified in a bit) Tr. Output : N-channel open drain 2. Input : Programmable pull-up MOS Tr. Output : CMOS Pull-up MOS Tr. Of port7 port7 1. Pull-up MOS Tr. not provided (Specified in a bit) 2. Pull-up MOS Tr. provided * P74 has on pull-up resistor option. The port operation related the option is different at reset. Refer to the next table. A kind of option Input/output form of Input/output ports Pins, Circuits Port 0 (Specified in a bit) No.6688-2/23 LC86P5632 • Port form at reset Pin P0 Contents of the option Input : Not pull-up MOS Tr. Output : N-channel open drain Input : Pull-up MOS Tr. Output : CMOS LC86P5632 (Same as the mask version) Input mode •The pull-up MOS Tr. is not provided during reset or several hundred microseconds after releasing reset. After that, the pull-up MOS Tr. is provided. (Output is OFF) (Same as the mask version) LC865632/28/24/20/16/12/08 Input mode without pull-up MOS Tr. (Output is OFF) Input mode without pull-up MOS Tr. (Output is OFF) P1, P2 P3, P4, P5 P7 Input : Programmable pull-up MOS Tr. Output : N-channel open drain Input : Programmable pull-up MOS Tr. Output : CMOS Input : Not Programmable pull-up MOS Tr. Output : N-channel open drain Input : Programmable pull-up MOS Tr. Output : CMOS Pull-up MOS Tr. not provided Pull-up MOS Tr. provided Input mode without pull-up MOS Tr. (Output is OFF) Input mode without pull-up MOS Tr. (Output is OFF) Input mode without pull-up MOS Tr. (Output is OFF) Input mode without pull-up MOS Tr. (Output is OFF) Input mode without pull-up MOS Tr. Input mode without pull-up MOS Tr. (Same as the mask version) (Same as the mask version) (Same as the mask version) (Same as the mask version) Input mode •The pull-up MOS Tr. is not provided during reset or several hundred microseconds after releasing reset. After that, the pull-up MOS Tr. is provided. (2) Option LC86P5632 uses 256 bytes which is addressed on 7F00H to 7FFFH in the program memory as option data area. This area does not affect the execution of program but the program memory capacity of LC865632 is 32512 bytes which is addressed on 0000H to 7EFFH. The option data is created by the option specified program “SU865000.EXE”. The created option data is linked to the program area by linkage loader “L865000.EXE”. No.6688-3/23 LC86P5632 (3) ROM space Option data 7FFFH 7F00H area 256 bytes 7EFFH 6FFFH 5FFFH 4FFFH 3FFFH 2FFFH 1FFFH Option Data Area Option Data Area Option Data Area Option Data Area Option Data Area Option Data Area Program area 32K bytes 0000H LC865632 Program area 28K bytes Program area 24K bytes Program area 20K bytes Program area 16K bytes Program area 12K bytes Program area 8K bytes LC865628 LC865624 LC865620 LC865616 LC865612 LC865608 (4) Ordering information 1. When ordering the identical mask ROM and PROM devices simultaneously. Provide an EPROM containing the target memory contents together with the separate order forms for each of the mask ROM and PROM versions. 2. When ordering a PROM device. Provide an EPROM containing the target memory contents together with an order form. How to use (1) Specification of option Programming data for PROM of the LC86P5632 is required. Debugged evaluation file (EVA file) must be converted to an INTEL-HEX formatted file (HEX file) with file converter program, EVA2HEX.EXE. The HEX file is used as the programming data for the LC86P5632. (2) How to program for the PROM LC86P5632 can be programmed by the EPROM programmer with attachment ; W86EP5032D, W86EP5032Q. • Recommended EPROM programmer Productor Advantest Andou AVAL Minato electronics EPROM programmer R4945, R4944, R4943 AF-9704 PKW-1100, PKW-3000 MODEL 1890A • “27512 (Vpp=12.5V) Intel high speed programming” mode available. The address must be set to “0000H to 7FFFH” and a jumper (DASEC) must be set to ‘OFF’ at programming. (3) How to use the data security function “Data security” is the disabled function to read the data of the PROM. The following is the process in order to execute the data security. 1. Set ‘ON’ the jumper of attachment. 2. Program again. Then EPROM programmer displays the error. The error means normally activity of the data security. It is not a trouble of the EPROM programmer or the LSI. No.6688-4/23 LC86P5632 Notes • Data security is not executed when the data of all address have ‘FF’ at the sequence 2 above. • The programming by a sequential operation “BLANK⇒PROGRAM⇒VERIFY” cannot be executed data security at the sequence 2 above. • Set to ‘OFF’ the jumper after executing the data security. Data security Data security 1 pin mark of LSI 1 pin Not data security 1 pin Not data security W86EP5032D W86EP5032Q No.6688-5/23 LC86P5632 P10/SO0 P11/SI0/SB0 P12/SCK0 P13/SO1 P14/SI1/SB1 P15/SCK1 P16/BUZ P17/PWM TEST1 RES XT1/P74 XT2 VSS CF1 CF2 VDD P80/AN0 P81/AN1 P82/AN2 P83/AN3 P84/AN4 P85/AN5 P86/AN6 P87/AN7 P70/INT0 P71/INT1 P72/INT2/T0IN P73/INT3/T0IN P30 P31 P32 P33 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 P07 P06 P05 P04 P03 P02 P01 P00 P27 P26 P25 P24 P23 P22 P21 P20 VDDVPP VSS P51 P50 P47 P46 P45 P44 P43 P42 P41 P40 P37 P36 P35 P34 Package Dimension (unit : mm) 3071 SANYO : DIP-64S(750mil) No.6688-6/23 LC86P5632 P14/SI1/SB1 P11/SI0/SB0 P15/SCK1 P12/SCK0 P17/PWM P16/BUZ P13/SO1 P10/SO0 P07 P06 P05 P04 P03 P02 P01 34 48 47 46 45 44 43 42 41 40 39 38 37 36 35 TEST1 RES 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 10 11 12 13 14 15 64 1 2 3 4 5 6 7 8 9 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 16 17 P00 P27 P26 P25 P24 P23 P22 P21 P20 VDDVPP VSS P51 P50 P47 P46 P45 P44 XT1/P74 XT2 VSS CF1 CF2 VDD P80/AN0 P81/AN1 P82/AN2 P83/AN3 P84/AN4 P85/AN5 P86/AN6 P87/AN7 P72/INT2/T0IN P73/INT3/T0IN P70/INT0 P71/INT1 P30 P31 P32 P33 P34 P35 P36 P37 P40 P41 P42 Package Dimension (unit : mm) 3159 SANYO: QIP-64E Notes • The QFP packages should be heat-soaked for 12 hours at 125°C immediately prior to mounting (This baking is called pre-baking). • After pre-baking, a controlled environment must be maintained until soldering. The environment must be held at a temperature of 30°C or less and a humidity level of 70% or less. Please solder within 24 hours. P43 No.6688-7/23 LC86P5632 System Block Diagram Interrupt Control IR PLA A15-A0 D7-D0 TA CE OE Standby Control EPROM Control CF RC X’tal PC Clock Generator EPROM (32KB) DASEC VDDVPP Base Timer Bus Interface ACC SIO0 Port 1 B Register SIO1 Port 7 C Register Timer 0 Port 8 ALU Timer 1 Port 2 ADC Port 3 PSW INT0 to 3 Noise Filter Real Time Service XRAM (128 bytes) Port 4 RAR Port 5 RAM Stack Pointer Port 0 Watch Dog Timer No.6688-8/23 LC86P5632 LC86P5632 Pin description Pin name VSS VDD VDDVPP PORT0 P00 to P07 I/O I/O Power pin (-) Power pin (+) Power pin (+) •8-bit input/output port •Input for port 0 interrupt •Input/output in nibble units •Input for HOLD release •8-bit input/output port •Input/output can be specified in a bit unit •Other pin functions P10 SIO0 data output P11 SIO0 data input/bus input/output P12 SIO0 clock input/output P13 SIO1 data output P14 SIO1 data input/bus input/output P15 SIO1 clock input/output P16 Buzzer output P17 Timer 1 output (PWM0 output) •8-bit input/output port •Input/output can be specified in a bit unit •8-bit input/output port •Input/output can be specified in a bit unit •15V withstand at N-channel open drain output •8-bit input/output port •Input/output can be specified in a bit unit •15V withstand at N-channel open drain output •2-bit input/output port •Input/output can be specified in a bit unit •15V withstand at N-channel open drain output •5-bit input port •Other pin functions P70 : INT0 input/HOLD release/N-channel Tr. output for watchdog timer P71 : INT1 input/HOLD release input P72 : INT2 input/timer 0 event input P73 : INT3 input with noise filter/timer 0 event input P74 : 32.768kHz crystal oscillation terminal XT1 •Interrupt received forms, the vector addresses high low rising falling rising & level falling level INT0 INT1 INT2 INT3 enable enable disable enable enable enable enable disable enable enable enable enable enable disable disable enable enable enable disable disable Function description •Pull-up resistor : Provided/Not provided •Output form : CMOS/N-channel open drain Output form : CMOS/N-channel open drain Option Power for programming PROM mode PORT1 P10 to P17 I/O Data line D0 to D7 PORT2 P20 to P27 PORT3 P30 to P37 PORT4 P40 to P47 PORT5 P50 to P51 PORT7 I/O Output form : CMOS/N-channel open drain Output form : CMOS/N-channel open drain Output form : CMOS/N-channel open drain Output form : CMOS/N-channel open drain •Pull-up resistor : Provided/Not provided (P70,71,72,73) • P74 has no pull-up resistor. Input of PROM control signals DASEC (*1) OE (*2) CE (*3) I/O Address input A7 to A0 Address input A14 to A8 (*5) P47 : TA (*4) I/O I/O P70 P71 to P74 I/O I vector 03H 0BH 13H 1BH Continue. No.6688-9/23 LC86P5632 Pin name PORT8 P80 to 87 RES I/O I Function description •8-bit input port •Other function AD input port (AN7 to AN0) Reset pin Test pin Should be left unconnected. •Input pin for 32.768kHz crystal oscillation •Other function : Input port P74 In case of non use, connect to VDD. •Output pin for 32.768kHz crystal oscillation •Other function In case of non use, should be left unconnected. Input pin for the ceramic resonator oscillation Output pin for the ceramic resonator oscillation - Option - PROM mode I O I - - TEST1 XT1/ P74 XT2 O - - CF1 CF2 I O - - ♦ All of port options can be specified in bit unit. *1 *2 *3 *4 *5 Memory select input for data security Output enable input Chip enable input TA ! PROM control signal input A14 ! Address input * Connect like the following figure to reduce noise into a VDD terminal. Short-circuit the VDD terminal to the VDDVPP terminal. Short-circuit the VSS terminal to the VSS terminal. LSI VDD Power Supply VDDVPP VSS VSS No.6688-10/23 LC86P5632 1. Absolute Maximum Ratings at VSS=0V and Ta=25°C Ratings unit typ. max. +7.0 V VDD+0.3 Parameter Supply voltage Input voltage Symbol Pins Conditions VDD=VDDVPP VDD[V] Input/Output voltage High level output current Peak output current Total output current Peak output current Total output current VDDMAX VDD,VDDVPP VI(1) •Ports 71,72,73, 74 •Port 8 • RES VIO(1) •Ports 0,1,2 •Ports 3,4,5 at CMOS output VIO(2) Ports 3,4,5 at N-ch open drain output option IOPH(1) •Ports 0,1,2,3,4,5 ΣIOAH(1) Ports 0,1,2 ΣIOAH(2) Ports 3,4,5 IOPL(1) IOPL(2) ΣIOAL(1) ΣIOAL(2) ΣIOAL(3) Pdmax(1) Pdmax(2) Topr Ports 0,1,2,3,4,5 Port 70 Ports 0,1,70 Port 2 Ports 3,4,5 DIP64S QFP64E min. -0.3 -0.3 -0.3 VDD+0.3 -0.3 •CMOS output •At each pins The total of all pins The total of all pins At each pins At each pins The total of all pins The total of all pins The total of all pins Ta=-30 to+70°C Ta=-30 to+70°C -30 -4 15 mA -25 -20 20 15 40 40 80 720 420 70 Low level output current Maximum power dissipation Operating temperature range Storage temperature range mW °C Tstg -65 150 Notes • The QFP packages should be heat-soaked for 12 hours at 125°C immediately prior to mounting (This baking is called pre-baking). • After pre-baking, a controlled environment must be maintained until soldering. The environment must be held at a temperature of 30°C or less and a humidity level of 70% or less. Please solder within 24 hours. No.6688-11/23 LC86P5632 2. Recommended Operating Range at Ta=-30°C to +70°C, VSS=0V Ratings typ. max. 6.0 6.0 Parameter Operating Supply voltage Hold voltage Symbol VDD(1) VHD VDD VDD Pins Conditions 0.98µs≤tCYC tCYC≤400µs RAMs and the registers hold voltage at HOLD mode. Output disable Output disable Output N-channel Tr. OFF VDD[V] min. 4.5 2.0 unit V Input high voltage VIH(1) VIH(2) VIH(3) Port 0 (Schmitt) VIH(4) VIH(5) VIH(6) VIH(7) Input low voltage VIL(1) VIL(2) VIL(3) VIL(4) VIL(5) Operation tCYC cycle time Oscillation FmCF(1) frequency range (Note 1) FmCF(2) •Ports 1,2 •Ports 72,73 (Schmitt) •Port 70 (Port input/interrupt) •Port 71 • RES (Schmitt) Port 70 (Watchdog timer) •Port 74 •Port 8 Ports 3,4,5 of CMOS output (Schmitt) Ports 3,4,5 of open drain output (Schmitt) Port 0 (Schmitt) •Ports 1,2,3,4,5 •Ports 72,73 (Schmitt) •Port 70 (Port input/interrupt) •Port 71 • RES (Schmitt) Port 70 (Watchdog timer) •Port 74 •Port 8 4.5 to 6.0 0.4VDD +0.9 4.5 to 6.0 0.75VDD 4.5 to 6.0 0.75VDD VDD VDD VDD Output N-channel Tr. OFF Output N-channel Tr. OFF Output disable Output disable Output disable Output disable N-channel Tr.OFF 4.5 to 6.0 0.9VDD 4.5 to 6.0 0.75VDD 4.5 to 6.0 0.75VDD 4.5 to 6.0 0.75VDD 4.5 to 6.0 4.5 to 6.0 4.5 to 6.0 VSS VSS VSS VDD VDD VDD 13.5 0.2VDD 0.25VDD 0.25VDD N-channel Tr.OFF N-channel Tr.OFF 4.5 to 6.0 4.5 to 6.0 4.5 to 6.0 VSS VSS 0.98 6 0. 8VDD -1.0 0.25VDD 400 µs MHz CF1, CF2 CF1, CF2 FmRC FsXtal XT1, XT2 •6MHz (ceramic resonator oscillation) •Refer to figure 1 •1.5MHz (ceramic resonator oscillation) •Refer to figure 1 RC oscillation •32.768kHz (crystal oscillation) •Refer to figure 2 Continue. 4.5 to 6.0 4.5 to 6.0 1.5 4.5 to 6.0 4.5 to 6.0 0.3 0.8 32.768 3.0 kHz No.6688-12/23 LC86P5632 Ratings typ. max. Parameter Oscillation stabilizing time period (Note 1) Symbol tmsCF(1) Pins CF1, CF2 Conditions •6MHz (ceramic resonator oscillation) •Refer to figure 3 •1.5MHz (ceramic resonator oscillation) •Refer to figure 3 •32.768kHz (crystal oscillation) ”Refer to figure 3 VDD[V] 4.5 to 6.0 min. unit ms tmsCF(2) CF1, CF2 4.5 to 6.0 tssXtal XT1, XT2 4.5 to 6.0 s (Note 1) The oscillation constant is shown on table 1 and table 2. No.6688-13/23 LC86P5632 3. Electrical Characteristics at Ta=-30°C to +70°C, VSS=0V Ratings typ. Parameter Input high current Symbol IIH(1) Pins Ports 3,4,5 at open drain output Conditions •Output disable •VIN=13.5V (including off-leakage current of the output Tr.) •Output disable •Pull-up MOS Tr. OFF. •VIN=VDD (including off-leakage current of the output Tr.) VIN=VDD VDD[V] 4.5 to 6.0 min. max. 5 unit µA IIH(2) •Port 0 without pull-up MOS Tr. •Ports 1,2,3,4,5 4.5 to 6.0 1 IIH(3) •Ports 70,71,72,73 without pull-up MOS Tr. •Port 8 RES 4.5 to 6.0 1 Input low current IIH(4) IIL(1) •Ports 1,2,3,4,5 •Port 0 without pull-up MOS Tr. IIL(2) •Ports 70,71,72,73 without pull-up MOS Tr. •Port 8 RES VIN=VDD •Output disable •Pull-up MOS Tr. OFF. •VIN=VSS (including off-leakage current of the output Tr.) VIN=VSS 4.5 to 6.0 4.5 to 6.0 1 -1 4.5 to 6.0 -1 Output high voltage Output low voltage IIL(3) VOH(1) VOH(2) VOL(1) VOL(2) VOL(3) VOL(4) Rpu VHIS Ports 0,1,2,3,4,5 at CMOS output Ports 0,1,2,3,4,5 Port 70 •Ports 0,1,2,3,4,5 •Ports 70,71,72,73 •Ports 0,1,2,3,4,5 •Ports 70,71,72,73 • RES All pins VIN=VSS IOH=-1.0mA IOH=-0.1mA IOL=10mA IOL=1.6mA IOL=1mA IOL=0.5mA VOH=0.9VDD Output disable 4.5 to 6.0 4.5 to 6.0 4.5 to 6.0 4.5 to 6.0 4.5 to 6.0 4.5 to 6.0 4.5 to 6.0 4.5 to 6.0 4.5 to 6.0 -1 VDD-1 VDD-0.5 1.5 0.4 0.4 0.4 15 40 0.1VDD 70 V Pull-up MOS Tr. resistor Hysteresis voltage Pin capacitance kΩ V CP •f=1MHz •VIN=VSS for all unmeasured terminals. •Ta=25°C 4.5 to 6.0 10 pF No.6688-14/23 LC86P5632 4. Serial Input/Output Characteristics at Ta=-30°C to +70°C, VSS=0V Ratings typ. Parameter Cycle Low Level pulse width High Level pulse width Cycle Low Level pulse width High Level pulse width Data set-up time Input clock Output clock Data hold time Output delay time (External clock using for serial transfer clock) Output delay time (Internal clock using for serial transfer clock) Symbol tCKCY(1) tCKL(1) tCKH(1) tCKCY(2) tCKL(2) tCKH(2) tICK tCKI tCKO(1) Pins SCK0,SCK1 Conditions Refer to figure 5 VDD[V] 4.5 to 6.0 min. 2 1 1 max. unit tCYC Serial clock SCK0,SCK1 Serial input •SI0,SI1 •SB0,SB1 Serial output •SO0,SO1 •SB0,SB1 tCKO(2) •Use pull-up resistor (1kΩ) in the open drain output. •Refer to figure 5 •Data set-up to SCK0,1 •Data hold from SCK0,1 •Refer to figure 5 •Use pull-up resistor (1kΩ) in the open drain output. •Data hold from SCK0,1 •Refer to figure 5 4.5 to 6.0 2 1/2tCKCY 1/2tCKCY 4.5 to 6.0 0.1 0.1 µs 4.5 to 6.0 7/12 tCYC +0.2 1/3 tCYC +0.2 No.6688-15/23 LC86P5632 5. Pulse Input Conditions at Ta=-30°C to +70°C, VSS=0V Ratings typ. max. Parameter High/low level pulse width Symbol tPIH(1) tPIL(1) tPIH(2) tPIL(2) tPIH(3) tPIL(3) tPIL(4) Pins •INT0, INT1 •INT2/T0IN •INT3 INT3 (The noise rejection clock selected to 1/1.) INT3 (The noise rejection clock selected to 1/16.) RES Conditions •Interrupt acceptable •Timer0-countable •Interrupt acceptable •Timer0-countable •Interrupt acceptable •Timer0-countable Reset acceptable VDD[V] 4.5 to 6.0 min. 1 unit tCYC 4.5 to 6.0 2 4.5 to 6.0 32 µs 4.5 to 6.0 200 6. AD Converter Characteristics at Ta=-30°C to + 70°C, VSS=0V Ratings typ. max. 8 ±1.5 65.28 (tCYC= 4.08µs) 130.56 (tCYC= 4.08µs) VDD 1 -1 V µA Parameter Resolution Absolute precision (Note 2) Conversion time Symbol N ET tCAD Pins Conditions VDD[V] 4.5 to 6.0 4.5 to 6.0 4.5 to 6.0 min. unit bit LSB µs AD conversion time = 16 × tCYC (ADCR2=0) (Note 3) AD conversion time = 32 × tCYC (ADCR2=1) (Note 3) AN0 to AN7 VAIN=VDD VAIN=VSS 15.68 (tCYC= 0.98µs) 31.36 (tCYC= 0.98µs) Analog input voltage range Analog port input current VAIN IAINH IAINL 4.5 to 6.0 4.5 to 6.0 4.5 to 6.0 VSS (Note 2) Absolute precision excepts the quantizing error (±1/2 LSB). (Note 3) The conversion time means the time from executing the AD conversion instruction to setting the complete digital conversion value to the register. No.6688-16/23 LC86P5632 7. Current Dissipation Characteristics at Ta=-30°C to +70°C, VSS=0V Ratings typ. 13 Parameter Symbol Pins VDD Conditions •FmCF=6MHz Ceramic resonator oscillation •FsXtal=32.768kHz crystal oscillation •System clock : CF oscillation •Internal RC oscillation stops •FmCF=1.5MHz Ceramic resonator oscillation •FsXtal=32.768kHz crystal oscillation •System clock : CF oscillation •Internal RC oscillation stops •FmCF=0Hz (The oscillation stops) •FsXtal=32.768kHz crystal oscillation •System clock : RC oscillation •FmCF=0Hz (The oscillation stops) •FsXtal=32.768kHz crystal oscillation •System clock : 32.768kHz •Internal RC oscillation stops Continue. Current dissipation IDDOP(1) during basic operation (Note 4) VDD[V] 4.5 to 6.0 min. max. 26 unit mA IDDOP(2) 4.5 to 6.0 7 14 IDDOP(3) 4.5 to 6.0 4 10 IDDOP(4) 4.5 to 6.0 4 8 No.6688-17/23 LC86P5632 Ratings typ. 5 Parameter Symbol Pins Conditions •HALT mode •FmCF=6MHz Ceramic resonator oscillation •FsXtal=32.768kHz crystal oscillation •System clock : CF oscillation •Internal RC oscillation stops •HALT mode •FmCF=1.5MHz Ceramic resonator oscillation •FsXtal=32.768kHz crystal oscillation •System clock : CF oscillation •Internal RC oscillation stops •HALT mode FmCF=0Hz (The oscillation stops) •FsXtal=32.768kHz crystal oscillation •System clock : RC oscillation •HALT mode FmCF=0Hz (The oscillation stops) •FsXtal=32.768kHz crystal oscillation •System clock : 32.768kHz •Internal RC oscillation stops HOLD mode Current dissipation IDDHALT(1) in HALT mode (Note 4) VDD[V] 4.5 to 6.0 min. max. 10 unit mA IDDHALT(2) 4.5 to 6.0 2.2 4.6 IDDHALT(3) 4.5 to 6.0 550 1000 µA IDDHALT(4) 4.5 to 6.0 25 100 Current dissipation IDDHOLD(1) VDD in HOLD mode IDDHOLD(2) (Note 4) 4.5 to 6.0 2.5 to 4.5 0.05 0.02 30 20 (Note 4) The currents of the output transistors and the pull-up MOS transistors are ignored. No.6688-18/23 LC86P5632 Table 1. Ceramic resonator oscillation recommended constant (main clock) Maker Oscillator C1 C2 Rf Murata CSA12.0MTZ 33pF 33pF OPEN CSA12.0MTZ 39pF 30pF OPEN CST12.0MTW on chip OPEN 3MHz ceramic resonator Murata CSA3.00MG040 100pF 100pF OPEN oscillation CST3.00MGW040 on chip OPEN * Both C1 and C2 must use K rank (±10%) and SL characteristics. Oscillation type 12MHz ceramic resonator oscillation Rd 560Ω 0Ω 560Ω 1.5Ω 1.5Ω Table 2. Crystal oscillation recommended constant (sub clock) Oscillation type Maker Oscillator C3 C4 32.768kHz crystal Kyocera KF-38G-13P0200 18pF 18pF oscillation Seiko Epson MC-306,C-002RX,32.768kHz 4pF 4pF * Both C3 and C4 must use J rank (±5%) and CH characteristics. (It is about the application which is not in need of high precision. Use K rank (±10%) and SL characteristics.) (Notes) •Since the circuit pattern affects the oscillation frequency, place the oscillation-related parts as close to the oscillation pins as possible with the shortest possible pattern length. CF1 Rf CF2 XT1 XT2 Rd X’tal C1 CF C2 C3 C4 Figure 1 Main-clock circuit Ceramic oscillation circuit Figure 2 Sub-clock circuit Crystal oscillation No.6688-19/23 LC86P5632 VDD Power supply VDD limit 0V Reset time RES Internal RC resontor oscillation tmsCF CF1, CF2 tssXtal XT1, XT2 Operation mode Unfixed Reset Instruction execution mode HOLD release signal Valid Internal RC resontor oscillation tmsCF CF1, CF2 tssXtal XT1, XT2 Operation mode HOLD Instruction execution mode Figure 3 Oscillation stable time No.6688-20/23 LC86P5632 VDD RRES RES CRES (Note) Fix the value of CRES, RRES that is sure to reset until 200µs, after Power supply has been over inferior limit of supply voltage. Figure 4 Reset circuit 0.5VDD tCKCY tCKL SCK0 SCK1 tICK SI0 SI1 tCKO SO0, SO1 SB0, SB1 50pF tCKI tCKH VDD 1KΩ Figure 5 Serial input / output test condition tPIL tPIH Figure 6 Pulse input timing condition No.6688-21/23 LC86P5632 Notice for use • The construction of the one-time programmable microcomputer with a blank built-in PROM makes it impossible for Sanyo to completely factory-test it before shipping. To probe reliability of the programmed devices, the screening procedure shown in the following figure should always be followed. • It is not possible to perform a writing test on the blank PROM. 100% yield, therefore, cannot be guaranteed. • Keeping the dry packing The environment must be held at a temperature of 30°C or less and a humidity level of 70% or less. • After opening the packing The preparation procedures shown in the following figure should always be followed prior to mounting the packages on the substrate. After opening the packing, a controlled environment must be maintained until soldering. The environment must be held at a temperature of 30°C or less and a humidity level of 70% or less. Please solder within 96 hours. Unused devices should be kept in the dry atmosphere such as inside of desiccator or dry these up before assembling on the board. a. Shipping with a blank PROM (Programming the data by yourself) DIP QFP Programming and verifying Programming and verifying Recommended process of screening Heat-soak 150±5°C, 24 +1 Hr -0 Recommended process of screening Heat-soak 150±5°C, 24 +1 Hr -0 Reading ascertation of program Reading ascertation of program Mounting Mounting b. Shipping with a programmed PROM (Programming the data by Sanyo) DIP QFP Mounting Mounting No.6688-22/23 LC86P5632 PS No.6688-23/23