LC866560

Ordering number : ENN*6691 CMOS IC LC86P6560 8-Bit Single Chip Microcontroller w ith One-Time Programmable PROM Preliminary Overview The LC86P6560 is a CMOS 8-bit single chip microcontroller with one-time PROM for the LC866500 series. This microcontroller has the function and the pin description of the LC866500 series mask ROM version, and 60K-byte PROM. Features (1) Option switching by PROM data The option function of the LC866500 series can be specified by the PROM data. LC86P6560 can be checked the functions of the trial pieces using the mass production board. (2) Internal one-time PROM capacity : 61696 bytes (3) Internal RAM capacity : 1152 bytes Used PROM or RAM capacity are equal ROM or RAM capacity of mask ROM version which applies LC86P6560. Mask ROM version LC866560 LC866556 PROM capacity 61440 bytes 57344 bytes RAM capacity 1152 bytes 1152 bytes (4) Operating supply voltage : 4.5V to 6.0V (5) Instruction cycle time : 1.0µs to 366µs (6) Operating temperature : -30°C to +70°C (7) The pin and the package compatible with the LC866500 series mask ROM devices (8) Applicable mask ROM version : LC866560/LC866556 Programming service We offers various services at nominal charges. These include the ROM writing, the ROM reading, the package stamping and the screening. Contact our representative for further information. Ver.1.03 31297 91400 RM (IM) SK No.6691-1/22 LC86P6560 Notice for use LC86P6560 is provided for the first release and small shipping of the LC866500 series. At using, take notice of the followings. (1) A point of difference LC86P6560 and LC866500 series Item Operation after reset releasing LC86P6560 LC866560/56 Pull-down resistor of the following pins •S0/T0 – S6/T6 •S7/T7 – S15/T15 •S16 – S31 •S32 – S47 •S48 – S51 Power dissipation The option is specified until 3ms after The program is executed from 00H of going to a ‘H’ level to the reset terminal the program counter immediately after by dgrees. The program is executed going to a ‘H’ level to reset terminal. from 00H of the program counter. Pull-down resistor Pull-down resistor provided/not provided provided/not provided Not provided Specified by the option Provided (fixed) Provided (fixed) Provided (fixed) Specified by the option Not provided Specified by the option Not provided Not provided Refer to ‘electrical characteristics’ on the semiconductor news. LC86P6560 uses 256 bytes that is addressed on FF00H to FFFFH in the program memory as the option configuration data area. This option configuration cannot execute all options which LC866500 series have. Next tables show the options that correspond and not correspond to LC86P6560. • A kind of the option corresponding of the LC86P6560 A kind of option Input/output form of Input/output ports Port 0 Pins, Circuits Contents of the option 1. N-channel open drain output 2. CMOS output *1 1. Pull-up MOS Tr. proveded 2. Pull-up MOS Tr. not provided *2 1. Input : Programmable pull-up MOS Tr. Output : N-channel open drain 2. Input : Programmable pull-up MOS Tr. Output : CMOS 1. Input : No Programmable pull-up MOS Tr. Output : N-channel open drain 2. Input : Programmable pull-up MOS Tr. Output : CMOS Port 1 *1 Port 3 *2 *1) Specified in a bit *2) Specified in nibble unit. The port of N-channel open drain output does not have the Pull-up MOS Tr.. • A kind of the option not corresponding of the LC86P6560 A kind of option Pull-down resistor of the high voltage Withstand output terminals Pins, Circuits •S0/T0 to S6/T6 •S16 to S31 •S32 to S47 LC86P6560 Not provided Provided (fixed) Not provided LC866560/56 Specified by the option Specified by the option Specified by the option No.6691-2/22 LC86P6560 (1) Option The option data is created by the option specified program “SU86K.EXE”. program area by linkage loader “L86K.EXE”. The created option data is linked to the (2) ROM space LC86E7248 and LC867200 series use 256 bytes that is addressed on 0FF00H to 0FFFFH in the program memory as the option specified data area. These program memory capacity are 49152 bytes that is addressed on 0000H to 0BFFFH. 0FFFFH 0FF00H 0EFFFH 0DFFFH 0CFFFH 0BFFFH 0AFFFH 9FFFH 8FFFH 7FFFH 6FFFH 5FFFH 4FFFH 3FFFH 2FFFH 1FFFH 0FFFH 0000H Option data area 256 bytes Option data area Option data area Option data area Program area 48K bytes LC867248 Program area 40K bytes LC867240 Program area 32K bytes LC867232 Program area 28K bytes LC867224 (3) Ordering information 1. When ordering the identical mask ROM and PROM devices simultaneously. Provide an EPROM containing the target memory contents together with the separate order forms for each of the mask ROM and PROM versions. 2. When ordering a PROM device. Provide an EPROM containing the target memory contents together with an order form. No.6691-3/22 LC86P6560 How to use (1) Specification of option Programming data for PROM of the LC86P6560 is required. Debugged evaluation file (EVA file) must be converted to an INTEL-HEX formatted file (HEX file) with file converter program, EVA2HEX.EXE. The HEX file is used as the programming data for the LC86P6548. (2) How to program for the PROM LC86P6560 can be programmed by the PROM programmer with attachment ; W86EP6548Q. • Recommended PROM programmer Productor Advantest Andou AVAL Minato electronics EPROM programmer R4945, R4944, R4943 AF-9704 PKW-1100, PKW-3000 MODEL 1890A • “27512 (Vpp=12.5V) Intel high speed programming” mode available. jumper (DASEC) must be set to ‘OFF’ at programming. The address must be set to “0 to 0FFFFH” and a (3) How to use the data security function “Data security” is the disabled function to read the data of the PROM. The following is the process in order to execute the data security. 1. Set ‘ON’ the jumper of attachment. 2. Program again. Then PROM programmer displays the error. The error means normally activity of the data security. It is not a trouble of the PROM programmer or the LSI. Notes • Data security is not executed when the data of all address have ‘FFH’ at the sequence 2 above. • The programming by a sequential operation “BLANK⇒PROGRAM⇒VERIFY” cannot be executed data security at the sequence 2 above. • Set to ‘OFF’ the jumper after executing the data security. Data security 1 pin mark of LSI Not data security 1 pin W86EP6548Q No.6691-4/22 3151 S48/PG0 S49/PG1 S50/PG2 S51/PG3 P00 P01 P02 P03 VSS2 VDD2 P04 P05 P06 P07 P10/SO0 P11/SI0/SB0 P12/SCK0 P13/SO1 P14/SI1/SB1 P15/SCK1 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 P16/BUZZ P17/PWM0 P30 P31 P32 P33 P34 P35 P36 P37 P70/INT0 RES XT1/P74 XT2/P75 VSS1 CF1 CF2 VDD1 P80/AN0 P81/AN1 P82/AN2 P83/AN3 P84/AN4 P85/AN5 P86/AN6 P87/AN7 P71/INT1 P72/INT2/T0IN P72/INT3/T0IN S0/T0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 S47/PF7 S46/PF6 S45/PF5 S44/PF4 S43/PF3 S42/PF2 S41/PF1 S40/PF0 VDD4 S39/PE7 S38/PE6 S37/PE5 S36/PE4 S35/PE3 S34/PE2 S33/PE1 S32/PE0 S31/PD7 S30/PD6 S29/PD5 S28/PD4 S27/PD3 S26/PD2 S25/PD1 S24/PD0 S23/PC7 S22/PC6 S21/PC5 S20/PC4 VP S19/PC3 S18/PC2 S17/PC1 S16/PC0 VDD3 S15/T15 S14/T14 S13/T13 S12/T12 S11/T11 S10/T10 S9/T9 S8/T8 S7/T7 S6/T6 S5/T5 S4/T4 S3/T3 S2/T2 S1/T1 Pin Assignment Package Dimension (unit : mm) LC86P6560 SANYO : QIP-100E No.6691-5/22 LC86P6560 System Block Diagram Interrupt Control IR PLA A15-A0 D7-D0 TA CE OE DASEC Standby Control PROM Control Clock Generator CF RC X’tal PROM(48KB) PC Base Timer Bus Interface ACC SIO0 Port 1 B Register SIO1 Port 3 C Register Timer 0 Port 7 ALU Timer 1 Port 8 ADC PSW INT0-3 Noise Filter SIO Automatic transmission RAR RAM RAM (128 bytes) Stack Pointer Port 0 VFD Controller Watch dog Timer High voltage Output No.6691-6/22 LC86P6560 LC86P6560 Pin description Pin name VSS1,2 VDD1,2,3,4 VP PORT0 P00 – P07 I/O I/O Function description Power pin (-) Power pin (+) *4 *4 •Pull-up resistor : Provided/Not provided (each nibble) •Output form : CMOS/N-channel open drain (each bit) •Output form : CMOS/N-channel open drain (each bit) Option PROM mode Power pin (+) for the VFD output pull-down resist •8-bit input/output port Input/output in nibble units •Input for port 0 interrupt •Input for HOLD release •15V withstand at N-channel open drain output •8-bit input/output port Input/output can be specified in bit unit •Other pin functions P10 SIO0 data output P11 SIO0 data input/bus input/output P12 SIO0 clock input/output P13 SIO1 data output P14 SIO1 data input/bus input/output P15 SIO1 clock input/output P16 Buzzer output P17 Timer 1 output (PWM0 output) •8-bit input/output port Input/output in bit unit •15V withstand at N-channel open drain output •4-bit input/output port Input/output in bit unit •2-bit input port •Other pin functions P70 : INT0 input/HOLD release/N-channel Tr. output for watchdog timer P71 : INT1 input/HOLD release input P72 : INT2 input/timer 0 event input P73 : INT3 input with noise filter/timer 0 event input P74 : 32.768kHz crystal oscillation terminal XT1 P75 : 32.768kHz crystal oscillation terminal XT2 •Interrupt received form, vector address rising falling rising high level & falling PORT1 P10 – P17 I/O Data line D0 to D7 PORT3 P30 – P37 I/O •Output form : CMOS/N-channel open drain (each bit) - - PORT7 PROM control signals DASEC (*1) OE (*2) ‚CE (*3) bE P70-P73 P74 -P75 I/O I low vector level INT0 enable enable disable enable enable 03H INT1 enable enable disable enable enable 0BH INT2 enable enable enable disable disable 13H INT3 enable enable enable disable disable 1BH No.6691-7/22 LC86P6560 Pin name PORT8 P80-P83 P84-P87 S0/T0 to S6/T6 *6 S7/T7 to S15/T15 *7 S16 to S31 *8 I I/O O O I/O Function description •4-bit input/output port Input/output in bit unit •4-bit input port •Other function AD input port (8 port pins) Output for VFD display controller segment/timing in common •Output for VFD display controller segment/timing with internal pull-down resistor in common •Internal pull-down resistor output •Output for VFD display controller segment •Other function S16 : High voltage input port PC0 S17 : High voltage input port PC1 S18 : High voltage input port PC2 S19 : High voltage input port PC3 S20 : High voltage input port PC4 S21 : High voltage input port PC5 S22 : High voltage input port PC6 S23 : High voltage input port PC7 S24 : High voltage input port PD0 S25 : High voltage input port PD1 S26 : High voltage input port PD2 S27 : High voltage input port PD3 S28 : High voltage input port PD4 S29 : High voltage input port PD5 S30 : High voltage input port PD6 S31 : High voltage input port PD7 S32 to S47 *9 I/O •Output for VFD display controller segment •Other function S32 : High voltage input port PE0 S33 : High voltage input port PE1 S34 : High voltage input port PE2 S35 : High voltage input port PE3 S36 : High voltage input port PE4 S37 : High voltage input port PE5 S38 : High voltage input port PE6 S39 : High voltage input port PE7 S40 : High voltage I/O port PF0 S41 : High voltage I/O port PF1 S42 : High voltage I/O port PF2 S43 : High voltage I/O port PF3 S44 : High voltage I/O port PF4 S45 : High voltage I/O port PF5 S46 : High voltage I/O port PF6 S47 : High voltage I/O port PF7 Option PROM mode - TA (*5) I/O - •Address input A15 to A0 No.6691-8/22 LC86P6560 Pin name S48 to S51 *9 I/O I/O Function description •Output for VFD display controller segment •Other function S48 : High voltage I/O port PG0 S49 : High voltage I/O port PG1 S50 : High voltage I/O port PG2 S51 : High voltage I/O port PG3 Reset pin •Input pin for 32.768kHz crystal oscillation •Other function XT1 : Input port P74 In case of non use, connect to VDD1. XT2/P75 O •Output pin for 32.768kHz crystal oscillation •Other function XT2 : Input port P75 In case of non use, connect to VDD1 at using as port or unconnect at using as oscillation. Input pin for ceramic resonator oscillation Output pin for ceramic resonator oscillation Option PROM mode RES I I - - XT1/ P74 CF1 CF2 I O - - *All of port options (except pull-up resistor of port 0) can be specified in bit unit. *1 *2 *3 *4 *5 *6 *7 *8 *9 Memory select input for data security Output enable input Chip enable input Connect like the following figure to reduce noise into a VDD1 terminal. Shorted the VSS1 terminal to the VSS2 terminal and to make the back-up time long. TA ! PROM control signal input S0/T0 to S6/T6 : not provided the pull-down resistor S7/T7 to S15/T15 : provided the pull-down resistor (fixed) S16 to S31 : provided the pull-down resistor (fixed) S32 to S51 : not provided the pull-down resistor LSI VDD1 Power Supply Back-up capacitor VDD2 VDD3 VFD powers VDD4 VSS1 VSS2 No.6691-9/22 LC86P6560 1. Absolute Maximum Ratings at VSS1=VSS2=0V and Ta=25°C Parameter Supply voltage Input voltage Symbol Pins Conditions VDD1=VDD2= VDD3=VDD4 Ratings VDD[V] min. -0.3 -0.3 typ. max. +7.0 VDD+0.3 unit V VDDMAX VDD1, VDD2 VDD3, VDD4 VI(1) •Ports 74 ,75 •Ports 80,81,82,83 •Port 8 • RES Output voltage Input/output voltage VI(2) VO VIO(1) VIO(2) High Peak level output output current current Total output current VIO(3) IOPH(1) IOPH(2) IOPH(3) ΣIOAH(1) ΣIOAH(2) ΣIOAH(3) ΣIOAH(4) ΣIOAH(5) ΣIOAH(6) IOPL(1) IOPL(2) ΣIOAL(1) ΣIOAL(2) ΣIOAL(3) Pdmax VP S0/T0 to S15/T15 •Port 1 •Ports 70,71,72,73 •Ports 84,85,86,87 •Ports 0, 3 at CMOS output option Ports 0, 3 at N-ch open drain output option S16 to S51 Ports 0, 1, 3 S0/T0 to S15/T15 S16 to S51 Port 0 Ports 1, 3 S0/T0 to S15/T15 S16 to S27 S28 to S39 S40 to S51 •Ports 0, 1, 3 •Ports 70,71,72,73 •Ports 84,85,86,87 Port 0 Ports 1, 3, 70 •Ports 71,72,73 •Ports 84,85,86,87 QFP100E VDD-45 VDD-45 -0.3 VDD+0.3 VDD+0.3 VDD+0.3 -0.3 15 Low level output current Peak output current Total output current •CMOS output •At each pins At each pins At each pins The total of all pins The total of all pins The total of all pins The total of all pins The total of all pins The total of all pins At each pins At each pins The total of all pins The total of all pins The total of all pins Ta=-30 to+70°C VDD-45 -10 -30 -15 -30 -30 -55 -60 -60 -60 VDD+0.3 mA 20 15 60 50 20 500 mW Maximum power dissipation Operating temperature range Storage temperature range Topr -30 +70 °C Tstg -55 +125 No.6691-10/22 LC86P6560 2. Recommended Operating Range at Ta=-30°C to +70°C, VSS1=VSS2=0V Ratings typ. Parameter Operating supply voltage range Hold voltage Symbol VDD Pins VDD1=VDD2= VDD3=VDD4 VDD1=VDD2 Conditions 0.98µs ≤ tCYC ≤ 400µs RAMs and the registers hold voltage at HOLD mode. VDD[V] min. 4.5 max. 6.0 unit V VHD 2.0 6.0 Pull-down voltage Input high voltage VP VIH(1) VIH(2) VIH(3) VP Port 0 CMOS output option Port 0 at N-ch open drain output •Port 1 •Ports 72,73 •Port 3 at CMOS output option •Port 3 at N-ch open drain output •Port 70 Port input/interrupt •Port 71 • RES Port 70 Watchdog timer •Port 8 •Ports 74 ,75 S16 to S51 Port 0 at CMOS output option Port 0 at N-ch open drain output •Ports 1,3 •Ports 72,73 •Port 70 Port input/interrupt •Port 71 • RES Port 70 Watchdog timer •Port 8 •Ports 74 ,75 S16 to S51 Output disable Output disable Output disable 4.5-6.0 -35 VDD VDD 13.5 VDD 4.5-6.0 0.33VDD +1.0 4.5-6.0 0.75VDD 4.5-6.0 0.75VDD VIH(4) VIH(5) Output disable Tr. OFF Output disable 4.5-6.0 0.75VDD 4.5-6.0 0.75VDD 13.5 VDD VIH(6) VIH(7) VIH(8) Input low voltage VIL(1) VIL(2) VIL(3) VIL(4) Output disable Output disable Output P-channel Tr. OFF Output disable Output disable Output disable Output disable 4.5-6.0 0.9VDD VDD VDD VDD 0.2VDD 0.25VDD 0.25VDD 0.25VDD 4.5-6.0 0.75VDD 4.5-6.0 0.33VDD +1.0 4.5-6.0 VSS 4.5-6.0 4.5-6.0 4.5-6.0 VSS VSS VSS VIL(5) VIL(6) VIL(7) Operation cycle time tCYC Output disable Output disable Output P-channel Tr. OFF 4.5-6.0 4.5-6.0 4.5-6.0 4.5-6.0 VSS VSS VP 0.98 0.8VDD -1.0 0.25VDD 0.2VDD 400 µs Continue. No.6691-11/22 LC86P6560 Parameter Oscillation frequency range (Note 1) Symbol FmCF(1) Pins CF1, CF2 Conditions •6MHz (ceramic resonator oscillation) •Refer to figure 1 •3MHz (ceramic resonator oscillation) •Refer to figure 1 RC oscillation •32.768kHz (crystal oscillation) •Refer to figure 2 •6MHz (ceramic resonator oscillation) •Refer to figure 3 •3MHz (ceramic resonator oscillation) •Refer to figure 3 •32.768kHz (crystal oscillation) •Refer to figure 3 Ratings VDD[V] 4.5-6.0 min. typ. 6 max. unit MHz FmCF(2) CF1, CF2 4.5-6.0 3 FmRC FsXtal XT1, XT2 4.5-6.0 4.5-6.0 0.3 0.8 32.768 3.0 kHz Oscillation stabilizing time period (Note 1) tmsCF(1) CF1, CF2 4.5-6.0 ms tmsCF(2) CF1, CF2 4.5-6.0 tssXtal XT1, XT2 4.5-6.0 s (Note 1) The oscillation constant is shown on table 1. No.6691-12/22 LC86P6560 3. Electrical Characteristics at Ta=-30°C to +70°C, VSS1=VSS2=0V Ratings typ. Parameter Input high current Symbol IIH(1) Pins Ports 0,3 of open drain output Conditions •Output disable •VIN=13.5V (including the offleak current of the output Tr.) •Output disable •Pull-up MOS Tr. OFF. VIN=VDD (including the offleak current of the output Tr.) •Output disable •VIN=VDD (including the offleak current of the output Tr.) VIN=VDD VIN=VDD •Output P-channel Tr. OFF •VIN=VDD •Output disable •Pull-up MOS Tr. OFF. VIN=VSS (including the offleak current of the output Tr.) •Output disable •VIN=VSS (including the offleak current of the output Tr.) VIN=VSS VIN=VSS IOH=-1.0mA IOH=-0.1mA IOH=-20mA •IOH=-1mA •The current of any unmeasurement pin is not over 1mA. IOH=-5mA The current of any unmeasurement pin is not over 1mA. IOL=10mA IOL=1.6mA IOL=1mA IOL=1.6mA VOH=0.9VDD VDD[V] 4.5-6.0 min. max. 5 unit µA IIH(2) •Port 0 without pull-up MOS Tr. •Ports 1,3 4.5-6.0 1 IIH(3) •Ports 70,71,72,73 •Port 8 4.5-6.0 1 IIH(4) IIH(5) IIH(6) Input low current IIL(1) RES Ports 74 ,75 •S32 to S51 without pull-down resistor •Ports 1,3 vPort 0 without pull-up MOS Tr. 4.5-6.0 4.5-6.0 4.5-6.0 1 1 1 4.5-6.0 -1 IIL(2) •Ports 70,71,72,73 •Port 8 4.5-6.0 -1 Output high voltage IIL(3) IIL(4) VOH(1) VOH(2) VOH(3) VOH(4) RES Ports 74 ,75 Ports 0,1,3 of CMOS output S0/T0 to S15/T15 4.5-6.0 -1 4.5-6.0 -1 4.5-6.0 VDD-1 4.5-6.0 VDD-0.5 4.5-6.0 VDD-1.8 4.5-6.0 VDD-1 V VOH(5) VOH(6) S16 to S51 4.5-6.0 VDD-1.8 4.5-6.0 VDD-1 Output low voltage VOL(1) VOL(2) VOL(3) VOL(4) Rpu Ports 0, 1, 3 Port 70 •Ports 71,72,73 •Ports 84,85,86,87 •Ports 0, 1, 3 4.5-6.0 4.5-6.0 4.5-6.0 4.5-6.0 4.5-6.0 15 40 1.5 0.4 0.4 0.4 70 KΩ Pull-up MOS Tr. resistor Continue. No.6691-13/22 LC86P6560 Parameter Output offleak current Symbol IOFF(1) IOFF(2) Pins S0/T0 to S6/T6, S32 to S51 without pull-down resistor S16 to S51 Conditions •Output P-ch Tr. OFF •VOUT=VSS •Output P-ch Tr. OFF •VOUT=VDD-40V •Output P-ch Tr. OFF •Using as input ports •Output P-ch Tr. OFF •VOUT=3V •Vp=-30V •VSS=GND •Vp=-30V Output disable Ratings VDD[V] 4.5-6.0 4.5-6.0 4.5-6.0 min. -1 -30 200 typ. max. unit µA Resistance of the low level hold Tr. High voltage pull-down resistor VP pull-down resistor Hysteresis voltage Pin capacitance Rinpd KΩ Rpd S7/T7 to S15/T15, S16 to S31 Vp •Port 1 •Ports 70,71,72,73,75 • RES All pins 5.0 60 100 200 Rvppd VHIS 5.0 4.5-6.0 60 100 0.1VDD 200 V CP •f=1MHz •Unmeasurement terminals for the input are set to VSS level. •Ta=25°C 4.5-6.0 10 pF 4. Serial Input/Output Characteristics at Ta=-30°C to +70°C, VSS1=VSS2=0V Ratings VDD[V] 4.5-6.0 min. 2 1 1 SCK0, SCK1 •Use pull-up resistor (1kΩ) when opendrain output. •Refer to figure 5. •Data set-up to SCK0,1 •Data hold from SCK0,1 •Refer to figure 5. •Use pull-up resistor (1kΩ) when open drain output. •Data hold from SCK0,1 •Refer to figure 5. 4.5-6.0 2 1/2 tCKCY 1/2 tCKCY 4.5-6.0 0.1 µs typ. max. Parameter Cycle Low Level pulse width High Level pulse width Cycle Low Level pulse width High Level pulse width Data set up time Input clock Symbol tCKCY(1) tCKL(1) tCKH(1) tCKCY(2) tCKL(2) tCKH(2) tICK Pins SCK0, SCK1 Conditions Refer to figure 5. unit tCYC Serial clock Output clock Serial input •SI0,SI1 •SB0,SB1 Data hold time Output delay time (Serial clock is external clock) Output delay time (Serial clock is internal clock) tCKI tCKO(1) •SO0,SO1 •SB0,SB1 0.1 4.5-6.0 7/12 tCYC +0.2 Serial output tCKO(2) 1/3 tCYC +0.2 No.6691-14/22 LC86P6560 5. Pulse Input Conditions at Ta=-30°C to +70°C, VSS1=VSS2=0V Ratings VDD[V] 4.5-6.0 4.5-6.0 min. 1 2 typ. max. Parameter High/low level pulse width Symbol tPIH(1) tPIL(1) tPIH(2) tPIL(2) Pins •INT0, INT1 •INT2/T0IN INT3/T0IN (The noise rejection clock is selected to 1/1.) INT3/T0IN (The noise rejection clock is selected to 1/16.) INT3/T0IN (The noise rejection clock is selected to 1/64.) RES Conditions •Interrupt acceptable •Timer0-countable •Interrupt acceptable •Timer0-countable unit tCYC tPIH(3) tPIL(3) •Interrupt acceptable •Timer0-countable 4.5-6.0 32 tPIH(4) tPIL(4) •Interrupt acceptable •Timer0-countable 4.5-6.0 128 tPIL(5) Reset acceptable 4.5-6.0 200 µs 6. AD Converter Characteristics at Ta=-30°C to + 70°C, VSS1=VSS2=0V Ratings VDD[V] 4.5-6.0 4.5-6.0 AD conversion time = 16 × tCYC (ADCR2=0) (Note 3) AD conversion time = 32 × tCYC (ADCR2=1) (Note 3) AN0 to AN7 VAIN=VDD VAIN=VSS 4.5-6.0 15.68 (tCYC= 0.98µs) 31.36 (tCYC= 0.98 µs) 4.5-6.0 4.5-6.0 4.5-6.0 VSS min. typ. 8 ±1.5 65.28 (tCYC= 4.08µs) 130.56 (tCYC= 4.08µs) VDD 1 -1 V µA max. Parameter Resolution Absolute precision (Note 2) Conversion time Symbol N ET tCAD Pins Conditions unit bit LSB µs Analog input voltage range Analog port input current VAIN IAINH IAINL (Note 2) Absolute precision excepts quantizing error (±1/2 LSB). (Note 3) The conversion time means the time from executing the AD conversion instruction to setting the complete digital conversion value to the register. No.6691-15/22 LC86P6560 7. Current Dissipation Characteristics at Ta=-30°C to +70°C, VSS1=VSS2=0V Ratings VDD[V] 4.5-6.0 min. typ. 14 max. 33 Parameter Current dissipation during basic operation (Note 4) Symbol IDDOP(1) Pins Conditions •FmCF=6MHz Ceramic resonator oscillation •Internal RC oscillation stops •FsXtal=32.768kHz crystal oscillation •System clock : CF oscillation •1/1 divided •FmCF=3MHz Ceramic resonator oscillation •Internal RC oscillation stops •FsXtal=32.768kHz crystal oscillation •System clock : CF oscillation •1/2 divided •FmCF=0Hz (when oscillation stops) •FsXtal=32.768kHz crystal oscillation •System clock : RC oscillation •1/2 divided •FmCF=0Hz (when oscillation stops) •FsXtal=32.768kHz crystal oscillation •System clock : crystal oscillation •Internal RC oscillation stops •1/2 divided unit mA IDDOP(2) 4.5-6.0 6 18 IDDOP(3) 4.5-6.0 4 13 IDDOP(4) 4.5-6.0 3 10 µA Continue. No.6691-16/22 LC86P6560 Parameter Current dissipation in HALT mode (Note 4) Symbol IDDHALT(1) Pins Conditions •HALT mode •FmCF=6MHz Ceramic resonator oscillation •Internal RC oscillation stops •FsXtal=32.768kHz crystal oscillation •System clock : CF oscillation •1/1 divided •HALT mode •FmCF=3MHz Ceramic resonator oscillation •Internal RC oscillation stops •FsXtal=32.768kHz crystal oscillation •System clock : CF oscillation •1/2 divided •HALT mode FmCF=0Hz (when oscillation stops) •FsXtal=32.768kHz crystal oscillation •System clock : RC oscillation •1/2 divided •HALT mode FmCF=0Hz (when oscillation stops) •FsXtal=32.768kHz crystal oscillation •System clock : crystal oscillation •Internal RC oscillation stops •1/2 divided HOLD mode Ratings VDD[V] 4.5-6.0 min. typ. 5 max. 14 unit mA IDDHALT(2) 4.5-6.0 2.2 7 IDDHALT(3) 4.5-6.0 400 1600 µA IDDHALT(4) 4.5-6.0 25 100 Current dissipation in HOLD mode (Note 4) IDDHOLD 4.5-6.0 0.05 30 (Note 4) The currents of the output transistors and the pull-up MOS transistors are ignored. No.6691-17/22 LC86P6560 Table 1. Ceramic resonator oscillation guaranteed constant (main clock) Oscillation type 6MHz ceramic resonator oscillation Maker Murata Kyocera Oscillator CSA6.00MG CST6.00MGW KBR-6.0MSB PBRC6.00A (chip type) To be determind KBR-6.0MKC PBRC6.00B (chip type) CSA3.00MG CST3.00MGW KBR-3.0MS C1 C2 3MHz ceramic resonator oscillation Murata Kyocera * Both C1 and C2 must use K rank (±10%) and SL characteristics. Table 2. Crystal oscillation recommended constant (sub clock) Oscillation type 32.768kHz crystal oscillation Maker Oscillator C3 C4 Rf Rd * Both C3 and C4 must use J rank (±5%) and CH characteristics. (It is about the application, which is not in need of high precision. Use K rank (±10%) and SL characteristics.) (Notes) •Since the circuit pattern affects the oscillation frequency, place the oscillation-related parts as close to the oscillation pins as possible with the shortest possible pattern length. •If you use other oscillators herein, we provide no guarantee for the characteristics. CF1 CF2 XT1 XT2 Rf Rd CF C1 C2 C3 X’tal C4 Figure 1 Ceramic oscillation circuit Figure 2 Crystal oscillation circuit No.6691-18/22 LC86P6560 Power supply Reset time VDD VDD limit 0V RES Internal RC resonator oscillation tmsCF CF1, CF2 tssXtal XT1, XT2 Instruction execution mode OCR6=1 Operation mode Unfixed Reset Instruction execution mode HOLD release signal Internal RC resonator oscillation Valid tmsCF CF1, CF2 tssXtal XT1, XT2 Operation mode HOLD Instruction execution mode Figure 3 Oscillation stable time No.6691-19/22 LC86P6560 VDD RRES RES CRES (Note) Fix the value of CRES, RRES that is sure to reset until 200µs, after Power supply has been over inferior limit of supply voltage. Figure 4 Reset circuit 0.5VDD tCKCY tCKL SCK0 SCK1 tICK SI0 SI1 tCKO SO0, SO1 SB0, SB1 50pF tCKI tCKH 1KΩ VDD Figure 5 Serial input / output test condition tPIL tPIH Figure 6 Pulse input timing condition No.6691-20/22 LC86P6560 Notice for use • The construction of the one-time programmable microcomputer with a blank built-in PROM makes it impossible for Sanyo to completely factory-test it before shipping. To probe reliability of the programmed devices, the screening procedure shown in the following figure should always be followed. • It is not possible to perform a writing test on the blank PROM. 100% yield, therefore, cannot be guaranteed. • Keeping the dry packing The environment must be held at a temperature of 30°C or less and a humidity level of 70% or less. • After opening the packing The preparation procedures shown in the following figure should always be followed prior to mounting the packages on the substrate. After opening the packing, a controlled environment must be maintained until soldering. The environment must be held at a temperature of 30°C or less and a humidity level of 70% or less. Please solder within 96 hours. Unused devices should be kept in the dry atmosphere such as inside of desiccator or dry these up before assembling on the board. a. Shipping with a blank PROM (Programming the data by yourself) b. Shipping with a programmed PROM (Programming the data by Sanyo) QFP QFP Writing data for program/verifying Mounting Recommended process of screening Heat-soak 150±5°C,24 +1 Hr -0 Reading ascertain of program VDD=5±0.5V Mounting No.6691-21/22 LC86P6560 memo: PS No.6691-22/22