LC86F3G64A

Ordering number : ENA0121A LC86F3G64A Overview CMOS IC 96K-byte Flash Memory (ROM 64K-byte+CGROM 16K-byte +Extended ROM 16K-byte) on-chip 768-byte RAM and 352×9-bit Display RAM 8-bit 1-chip Microcontroller The LC86F3G64A is a CMOS 8-bit single chip microcontroller with Flash Memory for the LC863G00 series. This microcontroller contains the following on-chip functional blocks: • CPU: Operable at a minimum bus cycle time of 0.424µs • On-chip ROM capacity: 96K bytes Flash Memory (Program ROM: 64K bytes, CGROM: 16K bytes, Extended ROM: 16K bytes ) • On-chip RAM capacity: 768 bytes • Display RAM: 352 × 9 bits • Closed-Caption TV controller and the on-screen display controller • Closed-Caption data slicer • Five channels × 8-bit AD Converter • Three channels × 7-bit PWM • Two 16-bit timer/counters, 14-bit base timer • 8-bit synchronous serial interface circuit • IIC-bus compliant serial interface circuit (Multi-master type) • UART interface circuit (full duplex) • ROM correct function • 16-source 10-vectored interrupt system Continued on next page. Note : This product includes the IIC bus interface circuit. If you intend to use the IIC bus interface, please notify us of this in advance of our receiving your program ROM code order. Purchase of SANYO IIC components conveys a license under the Philips IIC Patents Rights to use these components in an IIC system, provided that the system conforms to the IIC Standard Specification as defined by Philips. Trademarks IIC is a trademark of Philips Corporation. * This product is licensed from Silicon Storage Technology, Inc. (USA), and manufactured and sold by SANYO Semiconductor Co., Ltd. Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment (home appliances, AV equipment, communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee thereof. If you should intend to use our products for applications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our customer shall be solely responsible for the use. Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer' s products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer' s products or equipment. Ver.1.00 N0106HKIM 20060830-S00008 No.A0121-1/25 LC86F3G64A Continued from preceding page. • Integrated system clock generator and display clock generator Only one X’tal oscillator (32.768kHz) for PLL reference is used for both generators All of the above functions are fabricated on a single chip. The program is rewritable by using the on-board writing system after the LSI has been installed on the application board. The LC86F3G64A change to LC863200/ LC863300/ LC863800 series by writing program data of LC863200/ LC863300/ LC863800 series into the Flash Memory. Features Built-in Flash Memory 96K bytes • Program ROM • Character ROM • Extended ROM • Rewritable in page units • Page erase / program cycle 64K bytes 16K bytes 16K bytes 128 bytes / page 100 cycle per page Random Access Memory (RAM) 768 × 8 bits (including 128 bytes for ROM correction function) 352 × 9 bits (for CRT display) The LC86F3G64A consists of 64K of ROM space and 768 bytes of RAM space. For this microcontroller, the usable program ROM capacity and RAM capacity are the same size for the mask ROM version. Mask ROM versions compatible with the LC86F3G64A LC863G64/LC863864 LC863264/LC863364 LC863G56/LC863856 LC863256/LC863356 LC863G48/LC863848 LC863248/LC863348 LC863G40/LC863840 LC863240/LC863340 LC863G32/LC863832 LC863232/LC863332 LC863G28/LC863828 LC863228/LC863328 LC863G24/LC863824 LC863224/LC863324 LC863820 LC863220/LC863320 LC863816 LC863216/LC863316 Program ROM limit set for the LC86F3G64A 65536 bytes 65536 bytes 57344 bytes 57344 bytes 49152 bytes 49152 bytes 40960 bytes 40960 bytes 32768 bytes 32768 bytes 28672 bytes 28672 bytes 24576 bytes 24576 bytes 20480 bytes 20480 bytes 16384 bytes 16384 bytes RAM limit set for the LC86F3G64A (including 128 bytes for the ROM correction function) 768 bytes 640 bytes 768 bytes 640 bytes 768 bytes 640 bytes 768 bytes 640 bytes 768 bytes 512 bytes 768 bytes 512 bytes 768 bytes 512 bytes 768 bytes 512 bytes 768 bytes 512 bytes OSD Functions • Screen display : 36 characters × 16 lines (by software) • RAM : 352 words (9 bits per word) Display area : 36 words × 8 lines Control area : 8 words × 8 lines • Characters Up to 252 kinds of 16 × 32 dot characters (4 characters including 1 test character are not programmable) Each font can be divided into two parts and used as two fonts (Ex. 16 × 16 dot character font × 2) At least 111 characters need to be divide between a 16×17 dot and 8 × 9 dot character font to display the caption fonts. No.A0121-2/25 LC86F3G64A • Various character attributes Character colors Character background colors Fringe / shadow colors Full screen colors Rounding Underline Italic character (slanting) : 16 colors : 16 colors : 16 colors : 16 colors • Attribute can be changed without spacing • Vertical display start line number can be set for each row independently (Rows can be overlapped) • Horizontal display start position can be set for each row independently • Horizontal pitch (9 to 16 dot)*1 and vertical pitch (1 to 32 dot) can be set for each row independently • Different display modes can be set for each row independently Caption • Text mode / OSD mode 1 / OSD mode 2 (Quarter size) / Simplified graphic mode • Ten character sizes*1 Horiz. × Vert. = (1 × 1), (1 × 2), (2 × 2), (2 × 4) (1.5 × 1), (1.5 × 2), (3 × 2), (3 × 4), (0.5 × 0.5), (0.75 × 0.5) • Shuttering and scrolling on each row • Simplified Graphic Display • External OSD clock input enable (LC863G00 series only) Note *1: range depends on display mode : refer to manual for details. Data Slicer : closed caption format (LC863200/LC863800/LC863G00 series only) • Closed caption data and XDS data extraction • NTSC/PAL, and extracted line can be specified (LC863800/LC863G00 series) • NTSC, and fixed line 21 (LC863200 series) Bus Cycle Time / Instruction-Cycle Time Bus Cycle Time 0.424µs 7.5µs 91.55µs 183.1µs Instruction Cycle Time 0.848µs 15.0µs 183.1µs 366.2µs Clock Divider 1/2 1/2 1/1 1/2 System Clock Oscillation Internal VCO (Ref: X’tal 32.768kHz) Internal RC Crystal Crystal Oscillation Frequency 14.156MHz 800kHz 32.768kHz 32.768kHz Voltage 4.5V to 5.5V 4.5V to 5.5V 4.5V to 5.5V 4.5V to 5.5V Ports • Input / Output Ports : 5 ports (28 terminals) Data direction programmable in nibble units : 1 port (8 terminals) (If the N-ch open drain output is selected by option, the corresponding port data can be read in output mode.) Data direction programmable for each bit individually : 4 ports (20 terminals) • Input port (LC863300 series only) : 1 port (1 terminal) AD converter • 4-channels × 8-bit AD converters (LC863200/LC863800/LC863G00 series ) • 5-channels × 8-bit AD converters (LC863300 series) Serial interfaces • IIC-bus compatible serial interface (Multi-master type) Consists of a single built-in circuit with two I/O channels the two data lines and two clock lines can be short circuited internally. • Synchronous 8-bit serial interface No.A0121-3/25 LC86F3G64A UART (LC863G00 series only) • Full duplex • 7/8/9 bit data bits selectable • 1 stop bit • Built-in baudrate generator PWM Output • 3 channels×7-bit PWM Timer - Timer 0: 16-bit timer/counter With 2-bit prescaler + 8-bit built-in programmable prescaler Mode 0: Two 8-bit timers with a programmable prescaler Mode 1: 8-bit timer with a programmable prescaler + 8-bit counter Mode 2: 16-bit timer with a programmable prescaler Mode 3: 16-bit counter The resolution of timer is 1 tCYC. - Timer 1: 16-bit timer/PWM Mode 0: Two 8-bit timers Mode 1: 8-bit timer + 8-bit PWM Mode 2: 16-bit timer Mode 3: Variable bit PWM (9 to 16 bits) In mode 0/1, the resolution of Timer1/PWM is 1 tCYC In mode 2/3, the resolution is selectable by program; tCYC or 1/2 tCYC - Base timer Generate every 500ms overflow for a clock application (using 32.768kHz crystal oscillation for the base timer clock) Generate every 976µs, 3.9ms, 15.6ms, 62.5ms overflow (using 32.768kHz crystal oscillation for the base timer clock) Clock for the base timer is selectable from 32.768kHz crystal oscillation, system clock or programmable prescaler output of Timer 0 Remote Control Receiver Circuit (connected to the P73/INT3/T0IN terminal) • Noise rejection function • Polarity switching Watchdog Timer External RC circuit is required Interrupt or system reset is activated when the timer overflows ROM Correction Function Max 128 bytes / 2 addresses Interrupts • 18 source 10 vectored interrupts: (LC863G00 series) • 16 source 10 vectored interrupts: (LC863200/LC863800 series) • 15 source 9 vectored interrupts: (LC863300 series) 1. External Interrupt INT0 2. External Interrupt INT1 3. External Interrupt INT2, Timer/counter T0L (Lower 8 bits) 4. External Interrupt INT3, base timer 5. Timer/counter T0H (Upper 8 bits) 6. Timer T1H, T1L 7. SIO0, UART receive(LC863G00 series only) 8. Data slicer (LC863200/LC863800/LC863G00 series only), UART transmit (LC863G00 series only) 9. Vertical synchronous signal interrupt (VS), scanning line, AD 10. IIC, Port 0 No.A0121-4/25 LC86F3G64A • Interrupt priority control Three interrupt priorities are supported (low, high and highest) and multi-level nesting is possible. Low or high priority can be assigned to the interrupts from 3 to 10 listed above. For the external interrupt INT0 and INT1, low or highest priority can be set. Sub-routine Stack Level • A maximum of 128 levels (stack area is assigned on the internal RAM) Multiplication/Division Instruction • 16 bits×8 bits (7 instruction cycle times) • 16 bits÷8 bits (7 instruction cycle times) 3 Oscillation Circuits • Built-in RC oscillation circuit used for the system clock • Built-in VCO circuit used for the system clock and OSD clock • On-chip X’tal oscillation circuit used for PLL reference and the system clock and base timer clock Standby Function • HALT mode The HALT mode is used to reduce the power dissipation. In this operation mode, the program execution is stopped. This mode can be released by the interrupt request or the system reset. • HOLD mode The HOLD mode is used to stop the oscillations; RC (internal), VCO, and X’tal oscillations. This mode can be released by the following conditions. - Pull the reset terminal (RES) to low level. - Feed the selected level to either P70/INT0 or P71/INT1. - Feed the Port 0 interrupt condition Applicable Mask ROM Version • LC863G64/LC863G56/LC863G48/LC863G40/LC863G32/LC863G28/LC863G24 • LC863864/LC863856/LC863848/LC863840/LC863832/LC863828/LC863824/LC863820/LC863816 • LC863364/LC863356/LC863348/LC863340/LC863332/LC863328/LC863324/LC863320/LC863316 • LC863264/LC863256/LC863248/LC863240/LC863232/LC863228/LC863224/LC863220/LC863216 Package • DIP42S (Lead-free type) • QIP48E (Lead-free type) Development Tools • Evaluation chip: LC863096 • Emulator: LC863G00 series: Special ROM monitor tool (When debugging it, one terminal in the I/O port is used as a pin only for the tool) LC863800 series:EVA86000(main) + ECB863200A (evaluation chip board) + POD863200 (pod:DIP42S) [Shared with LC8632 Series] or POD863201 (QIP48E) [Shared with LC8632 Series] LC863300 series:EVA86000(main) + ECB863200*1 or ECB863200A (evaluation chip board) + POD863300 (pod:DIP42S) or POD863301 (QIP48E) LC863200 series: EVA86000(main) + ECB863200*1 or ECB863200A (evaluation chip board) + POD863200 (pod:DIP42S) or POD863201 (QIP48E) *1 This product is no longer available Write Flash Memory SANYO provides special services including writing data to Flash Memory and stamping. There is a charge for these services. Please feel free to ask our sales persons for details. No.A0121-5/25 LC86F3G64A Package Dimensions unit : mm (typ) 3025C 37.7 42 22 0.95 3.8 5.1max (4.25) 0.51min 1.78 0.48 (1.05) SANYO : DIP42S(600mil) Package Dimensions unit : mm (typ) 3156A 17.2 0.8 14.0 36 37 25 24 14.0 48 1 1.0 (1.5) (2.7) 0.35 12 13 17.2 0.15 3.0max 0.1 SANYO : QIP48E(14X14) 0.25 1 21 15.24 13.8 No.A0121-6/25 LC86F3G64A Pin Assignments P10/SO0 P11/SI0 P12/SCK0 P13/PWM1 P14/PWM2/TX P15/PWM3/RX P16/OSDCK P17/PWM VSS XT1 XT2 VDD P84/AN4 P85/AN5 P86/AN6 P87/AN7 RES FILT CVIN/P83/AN3 VS HS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 41 40 39 38 37 36 35 34 P07 P06 P05 P04 P03 P02 P01 P00 P73/INT3/T0IN P72/INT2/T0IN P71/INT1 P70/INT0 P63/SCLK1 P62/SDA1 P61/SCLK0 P60/SDA0 I BL B G R Top view LC86F3G64A 33 32 31 30 29 28 27 26 25 24 23 22 P14/PWM2/TX P13/PWM1 P12/SCK0 P10/SO0 P11/SI0 P07 P06 P05 P04 38 48 47 46 45 44 43 42 41 40 39 P15/PWM3/RX P16/OSDCK P17/PWM VSS XT1 XT2 VDD NC P84/AN4 P85/AN5 P86/AN6 P87/AN7 37 P03 NC NC 1 2 3 4 5 6 7 8 9 10 11 13 14 15 16 17 18 19 20 21 22 23 24 12 36 35 34 33 32 P02 P01 P00 NC P73/INT3/T0IN P72/INT2/T0IN P71/INT1 P70/INT0 P63/SCLK1 P62/SDA1 P61/SCLK0 P60/SDA0 LC86F3G64A 31 30 29 28 27 26 25 FILT G R NC RES CVIN/P83/AN3 NC VS HS BL B I Top view No.A0121-7/25 LC86F3G64A System Block Diagram Interrupt Control IR PLA Stanby Control Flash Memory (96KB) Generator X’tal RC VCO Clock Flash Memory Control A0-A16 D0-D7 CE OE WE PLL PC ACC IIC ROM Correct Control B Register SIO0 XRAM C Register Timer 0 Bus Interface Timer 1 Port 1 ALU Base Timer Port 6 PSW ADC INT0-3 Noise Rejection Filter PWM Port 7 RAR Port 8 RAM Data Slicer LC863200/LC863800/ LC863G00 only UART LC863G00only OSD Control Circuit CGROM Stack Pointer VRAM Port 0 Watchdog Timer No.A0121-8/25 LC86F3G64A Pin Description Pin Description Table Flash memory mode Terminal VSS XT1 XT2 VDD RES FILT CVIN VS HS R G B I BL Port 0 P00 - P07 I/O I O I O I I I O O O O O I/O Negative power supply Input terminal for crystal oscillator Output terminal for crystal oscillator Positive power supply Reset terminal Filter terminal for PLL Video signal input terminal (LC863200/LC863800/LC863G00 only ) Vertical synchronization signal input terminal Horizontal synchronization signal input terminal Red (R) output terminal of RGB image output Green (G) output terminal of RGB image output Blue (B) output terminal of RGB image output Intensity ( I ) output terminal of RGB image output Fast blanking control signal Switch TV image signal and caption/OSD image signal •8-bit input/output port, Input/output can be specified in nibble unit •Other functions HOLD release input Interrupt input Port 1 P10 - P17 I/O •8-bit input/output port Input/output can be specified in a bit •Other functions P10 P11 P12 P13 P14 P15 P16 P17 SIO0 data output SIO0 data input/bus input/output SIO0 clock input/output PWM1 output PWM2 output / UART transmit (LC863G00 only) PWM3 output / UART receive (LC863G00 only) External OSD clock input (LC863G00 only) Timer1 (PWM) output Pull-up register Present/ not present Output Format CMOS/Nch-OD Output Format CMOS/Nch-OD Data input/output D0 to D7 Address input A0 to A7 Address input A15 Address input A13 Address input A14 Input to set up mode Input to set up mode Address input A16 Function Description Option (Parallel input/ output mode) Port 6 P60 - P63 I/O •4-bit input/output port Input/output can be specified for each bit •Other functions P60 P61 P62 P63 IIC0 data I/O IIC0 clock output IIC1 data I/O IIC1 clock output control signal CE control signal OE control signal WE Address input A12 Continued on next page. No.A0121-9/25 LC86F3G64A Continued from preceding page. Flash memory mode Terminal Port 7 P70 P71 - P73 I/O I/O •4-bit input/output port Input or output can be specified for each bit •Other function P70 P71 P72 P73 INT0 input/HOLD release input/ Nch-Tr. output for watchdog timer INT1 input/HOLD release input INT2 input/Timer 0 event input INT3 input (noise rejection filter attached)/ Timer 0 event input Interrupt receiver format, vector addresses rising INT0 INT1 INT2 INT3 Port 8 P83 I •1-bit input port (LC863300 only) •Other function AD converter input port (1 lines) P84 - P87 I/O •4-bit input/output port Input or output can be specified for each bit •Other function AD converter input port (4 lines) NC unused terminal Leave open enable enable enable enable falling enable enable enable enable rising/ falling disable disable enable enable enable enable disable disable enable enable disable disable 03H 0BH 13H 1BH H level L level vector Function Description Option (Parallel input/ output mode) Address input A8 to A11 • Output form and existence of pull-up resistor for every port can be specified for each bit. • Programmable pull-up resister is always connected regardless of port option, CMOS or N-ch open drain output in port 1. User Options User options can be changed using Flash Memory data. A kind of option Input/output form of input/output ports Port 0 (Specified in a bit) Pin, Circuits 1. Input: Without pull-up MOS Tr. Output: N-channel open drain 2. Input: With pull-up MOS Tr. Output: CMOS Port 1 (Specified in a bit) 1. Input: With programmable pull-up MOS Tr. Output: N-channel open drain 2. Input: With programmable pull-up MOS Tr. Output: CMOS No.A0121-10/25 LC86F3G64A Notice for Use • Input level of terminal RES at power on Terminal RES must be held low for at least 200µs after the supply voltage exceeds the power supply lower limit. Power supply 200µs or more RES VDD limit 0V • Difference between the Mask version and Flash version 1. The operation after release of reset: The mask version operates the program from the address 0 in the program counter as soon as detecting the H level on the reset port. The flash version operates the program from the address 0 in the program counter after setting the option. 2. Current dissipation : Please refer to the latest semiconductor news. • Conditions during reset and after release of reset Port options are set using Flash Memory data. Port options are set internally within approximately 3ms after logic HIGH is applied to the RESET terminal. The configuration of the port outputs change over the duration of this period. Then the Program Counter is set to 0 and program execution begins. During reset, and in the few hundred milliseconds after reset is released, the port options on certain of the ports will not yet have been set. The conditions of the various ports during reset or on release of reset have been collected in the following table. Please refer to it when analyzing circuits where these conditions apply. Pins P0 Options Input: Without pull up MOS transistor Output: N-channel open drain Input: With pull up MOS transistor Output: CMOS Output -off Input mode: High impedance Output-off During reset and in the first few hundred µs after reset is released, the pull-up MOS transistor is OFF. Thereafter, set to input mode with pull-up MOS Tr. ON P1 Input: With programmable pull up MOS transistor Output: N-channel open drain Input: With programmable pull up MOS transistor Output: CMOS P6 P7 No options Output: N-channel open drain No options Input: With programmable pull up MOS transistor Output: N-channel open drain (P70) CMOS (P71 - P73) P8 No options Input: With programmable pull up MOS Transistor (P83: without it) Output: CMOS (P83: input only) Output-off Input mode: Pull up MOS transistor off Output -off Input mode: High impedance Output-off Input mode: Pull up MOS transistor off Output-off Input mode: High impedance Condition during and on release of reset No.A0121-11/25 LC86F3G64A On-board writing system The LC86F3G64A has the On-board writing system. The program is renewable by using SANYO Flash On-board System after the LSI has been installed on the application board. This system is composed of 4 types divided by the combination of the mode setting pin and communication pin. Each type system has to connect the 6 pins (VDD, VSS, RES, communication pins) with the interface board of SANYO Flash On-board System. It is necessary that the pins to be used for the rewriting system should be able to be separated from the application board properly. The system type is selected by the option setting program (Su86K.exe). types type1 type2 type3 type4 mode setting pin RES pin (high voltage(12V) applied) RES pin (high voltage(12V) applied) P00 pin (High level voltage applied) P00 pin (High level voltage applied) communication pins P00(DATA1), P01(DATA0), P02(CLK) P00(DATA1), P60(DATA0), P61(CLK) P00(ENA/DATA1), P01(DATA0), P02(CLK) P00(ENA/DATA1), P60(DATA0), P61(CLK) • Type 3 or 4 is selected: P00 is exclusive for the on-board system. This pin must always be pulled-down, so this pin can’t be used for other applications. Please set P00 pin N-channel open drain output.(option setting) In the user program, “0” is always set to the P00 latch (bit 0 in the Port 0 latch (140h)) because the P0 interrupt must not be requested on the P00 pin . • The loader program must be written into the ROM to use On-board writing system. The loader program should be written into the ROM before the LSI has been installed on the board by the general purpose PROM programs. When the option setting selects the this system to use, the loader program automatically links to the extended ROM field (14000h-147FFh) on the user program linking. Please ask to our sales persons before using On-board writing system. No.A0121-12/25 LC86F3G64A Method of how to rewrite it in FLASH programmer / SANYO FLASH writing tool (SFWS) When reading or writing data to the LC86F3G64A, FLASH programmer of our recommendation or SANYO FLASH writing tool (SFWS) is used. In both cases, exclusive conversion board (W86F3264D, W86F3264Q) is needed. (1) FLASH programmer of our recommendation Single Word Write Manufacture Flash Support Group co. (the former Ando Electric) Name of device AF9708 version Rev2.43 applicable device (code) SANYO LC86F3G64A (3B225) Data protection setting after write operation Protected Write Multiple Words Manufacture Flash Support Group co. (the former Ando Electric) Name of device AF9723 + AF9833 version Rev2.04 +Rev01.85 *1 applicable device (code) SANYO LC86F3G64A (3B225) Data protection setting after write operation Protected *1: Registration is being requested. The LC86F3G64A does not support a silicon signature feature. Do not use the feature (automatic device type selection) when programming this device. To avoid erasing the program, confirm the setting of the protection for activating the written program before using. It can’t be written with device code 29EE010 (2) SANYO FLASH writing tool (SFWS) PC is connected with writer unit (SKK) by USB cable and it uses it. (3) Exclusive writing conversion board • W86F3264D • • • DIP42S purpose (It is common with production discontinuance model (LC86F3264A/LC86F3364A/LC86F3864A) ) • W86F3264Q • • • QIP48E purpose (It is common with production discontinuance model (LC86F3264A/LC86F3364A/ LC86F3864A) ) When using the conversion board, all of the jumper SW must be set to the OFF position. If set to the ON position, read/write operations will not perform correctly. Pin 1 of the conversion board should be located as indicated below. W86F3264D: when viewing from the edge closest to jumper SW, pin 1 is located on the lower right of both the chip and conversion board. W86F3264Q: when viewing from the edge closest to jumper SW, pin 1 of the chip is located on the upper right while pin 1 of the conversion board is located on the lower right. Chip: pin 1 Pin 1 Pin 1 Set jumper SW to OFF W86F3264D Set jumper SW to OFF W86F3264Q No.A0121-13/25 LC86F3G64A Absolute Maximum Ratings at Ta = 25°C, VSS = 0V Parameter Maximum supply voltage Input voltage Output voltage Input/output voltage High level output current Total output current Low level output current Total output current Maximum power dissipation Operating temperature range Storage temperature range Tstg -55 +125 Topr -30 +85 °C Peak output current ΣIOAH(1) ΣIOAH(2) ΣIOAH(3) IOPL(1) IOPL(2) IOPL(3) ΣIOAL(1) ΣIOAL(2) ΣIOAL(3) Pd max •Ports 0, 1 Ports 7, 84-87 R, G, B, I, BL Ports 0, 1, 6, 84-87 Port 7 R, G, B, I, BL Ports 0, 1 Ports 6, 7, 84-87 R, G, B, I, BL DIP42S QIP48E Peak output current IOPH(2) R, G, B, I, BL VI(1) VO(1) VIO(1) IOPH(1) •RES, HS, VS, CVIN/P83 R, G, B, I, BL, FILT •Ports 0, 1, 6, 7, 84-87 •Ports 0, 1, 7, 84-87 •CMOS output •For each pin. •CMOS output •For each pin. The total of all pins. The total of all pins. The total of all pins. For each pin. For each pin. For each pin. The total of all pins. The total of all pins. The total of all pins. Ta=-30 to +85°C Symbol VDD max VDD Pins Conditions VDD[V] min -0.3 -0.3 -0.3 -0.3 -4 -5 -20 -10 -15 15 15 5 40 35 15 500 280 mW mA Specification typ max +6.5 VDD+0. 3 VDD+0.3 VDD+0.3 unit V No.A0121-14/25 LC86F3G64A Recommended Operating Range at Ta = -30°C to +85°C, VSS = 0V Parameter Operating supply voltage range Hold voltage VHD VDD RAMs and the registers data are kept in HOLD mode. High level input voltage VIH(2) •Ports 1,6 (Schumitt CMOS) •Port 7 (Schumitt) port input/interrupt •HS, VS, RES, (Schumitt CMOS) VIH(3) VIH(4) VIH(5) Port 70 Watchdog timer input •Port 8 port input •Port 16 (TTL) •Port 6, HS, VS (Schumitt TTL) LC863G00 only Low level input voltage VIL(1) VIL(2) Port 0 (Schumitt) •Ports 1,6 (Schumitt CMOS) •Port 7 (Schumitt) port input/interrupt •HS, VS, RES, (Schumitt CMOS) VIL(3) VIL(4) VIL(5) Port 70 Watchdog timer input Port 8 port input •Port 16 (TTL) •Port 6, HS, VS (Schumitt TTL) LC863G00 only CVIN Operation cycle time VCVIN tCYC(1) tCYC(2) CVIN •All functions operating •AD converter operating •OSD and Data slicer are not operating tCYC(3) •OSD, AD converter and Data slicer are not operating Oscillation frequency range External OSD clock input frequency range FmICK P16/OSDCK (LC863G00 only) DUTY50±5% of external OSD clock 4.5 to 5.5 13 14 15 MHz FmRC Internal RC oscillation 4.5 to 5.5 0.4 0.8 3.0 MHz 4.5 to 5.5 0.844 400 4.5 to 5.5 0.844 30 µs 5.0 4.5 to 5.5 1Vp-p -3dB 0.844 1Vp-p 0.848 1Vp-p +3dB 0.852 Vp-p* Output disable 4.5 to 5.5 VSS 0.18VDD Output disable Output disable 4.5 to 5.5 4.5 to 5.5 VSS VSS 0.6VDD 0.3VDD 4.5 to 5.5 VSS 0.25VDD Output disable Output disable 4.5 to 5.5 VSS 0.2VDD Output disable 4.5 to 5.5 0.45VDD VDD Output disable Output disable 4.5 to 5.5 4.5 to 5.5 VDD-0.5 0.7VDD VDD VDD V 4.5 to 5.5 0.75VDD VDD Output disable VIH(1) Port 0 (Schumitt) Output disable 4.5 to 5.5 0.6VDD VDD 2.0 5.5 Symbol VDD(1) VDD(2) VDD Pins Conditions VDD[V] 0.844µs ≤ tCYC ≤ 0.852µs 4µs ≤ tCYC ≤ 400µs min 4.5 4.5 Specification typ max 5.5 5.5 unit * Vp-p: Peak-to-peak voltage No.A0121-15/25 LC86F3G64A Electrical Characteristics at Ta = -30°C to +85°C, VSS = 0V Parameter High level input current Symbol IIH(1) Pins Ports 0, 1, 6, 7, 8 Conditions VDD[V] •Output disable •Pull-up MOS Tr. OFF •VIN=VDD (including the off- leak current of the output Tr.) IIH(2) Low level input current IIL(1) •RES •HS, VS Ports 0, 1, 6, 7, 8 •VIN=VDD •Output disable •Pull-up MOS Tr. OFF •VIN=VSS (including the off- leak current of the output Tr.) IIL(2) High level output voltage VOH(2) Low level output voltage VOL(2) VOL(3) VOL(4) VOL(5) Pull-up MOS Tr. resistance Bus terminal short circuit resistance (SCL0-SCL1, SDA0-SDA1) Hysteresis voltage Input clump voltage Pin capacitance CP All pins •f=1MHz •Every other terminals are connected to VSS. •Ta=25°C 4.5 to 5.5 10 pF VCLMP VHYS •Ports 0, 1, 6, 7 •RES •HS, VS CVIN Output disable 4.5 to 5.5 0.1VDD V 5.0 2.3 2.5 2.7 RBS Rpu VOL(1) VOH(1) •RES •HS, VS •CMOS output of ports 0,1,71-73, 84-87 R, G, B, I, BL Ports 0,1,71-73, 84-87 Ports 0,1,71-73, 84-87 •R, G, B, I, BL •Port 6 Port 6 Port 70 •Ports 0, 1, 7, 84-87 •P60-P62 •P61-P63 4.5 to 5.5 130 300 Ω IOL=6.0mA IOL=1mA VOH=0.9VDD IOL=3.0mA IOL=1.6mA IOH=-0.1mA IOL=10mA 4.5 to 5.5 4.5 to 5.5 4.5 to 5.5 4.5 to 5.5 4.5 to 5.5 4.5 to 5.5 4.5 to 5.5 13 38 VDD-0.5 1.5 V 0.4 0.4 0.6 0.4 80 kΩ VIN=VSS IOH=-1.0mA 4.5 to 5.5 VDD-1 4.5 to 5.5 -1 4.5 to 5.5 -1 4.5 to 5.5 1 µA 4.5 to 5.5 1 min Specification typ max unit No.A0121-16/25 LC86F3G64A Serial input/output characteristics at Ta = -30°C to +85°C, VSS = 0V Parameter Cycle Input clock Low Level pulse width High Level pulse width Cycle Output clock Low Level pulse width High Level pulse width Data set up time Serial input tICK SI0 •Data set-up to SCK0. •Data hold from SCK0. •Refer to figure 4. Data hold time tCKI 4.5 to 5.5 0.1 Output delay time Serial output (Using external clock) Output delay time (Using internal clock) tCKO(2) SO0 tCKO(1) SO0 •Data hold from SCK0. •Use pull-up resistor (1kΩ) when Nch open-drain output. •Refer to figure 4. 4.5 to 5.5 4.5 to 5.5 µs 7/12tCYC +0.2 1/3tCYC +0.2 0.1 tCKH(2) tCKCY(2) tCKL(2) •SCK0 •SCLK0 •Use pull-up resistor (1kΩ) when Nch open-drain output. •Refer to figure 4. 4.5 to 5.5 tCKH(1) Symbol tCKCY(1) tCKL(1) Pins •SCK0 •SCLK0 4.5 to 5.5 Conditions VDD[V] Refer to figure 4. min 2 1 1 tCYC 2 1/2tCKCY 1/2tCKCY Specification typ max unit IIC Input/Output Conditions at Ta = -30°C to +85°C, VSS = 0V Parameter SCL Frequency BUS free time between stop - start HOLD time of start, restart condition L time of SCL H time of SCL Set-up time of restart condition HOLD time of SDA Set-up time of SDA Rising time of SDA, SCL Falling time of SDA, SCL Set-up time of stop condition fSCL tBUF tHD;STA tLOW tHIGH tSU;STA tHD;DAT tSU;DAT tR tF tSU;STO 4.0 Symbol min 0 4.7 4.0 4.7 4.0 4.7 0 250 1000 300 Standard max 100 min 0 1.3 0.6 1.3 0.6 0.6 0 100 20+0.1Cb 20+0.1Cb 0.6 300 300 0.9 High speed max 400 kHz µs µs µs µs µs µs ns ns ns µs unit Refer to figure 10 Note Cb: Total capacitance of all BUS (unit: pF) Serial clock No.A0121-17/25 LC86F3G64A UART (Full Duplex) Operating Conditions at Ta = -30°C to +85°C, VSS = 0V (LC863G00 only) Parameter Transfer rate* Symbol UBR(1) UBR(2) Pin/Remarks P14, 15 Condition VDD[V] 0.844µs ≤ tCYC ≤ 400µs 4.5 to 5.5 min 16/6 Specification typ max 8192/6 unit tCYC * High speed mode: UBR= (n+1) × (8/6)tCYC Low speed mode: UBR= (n+1) × (32/6)tCYC Data length: 7/8/9 bits(LSB First) Stop bits: 1 bit Parity bits: None n=1 to 255 Example of Continuous 8-bit Data Transmission Mode Processing (First Transmit Data = 55H) Start bit Start of transmission Transmit data (LSB First) End of transmission Stop bit UBR Example of Continuous 8-bit Data Reception Mode Processing (First Receive Data = 55H) Start bit Start of reception Receive data (LSB First) Stop bit End of reception UBR No.A0121-18/25 LC86F3G64A Pulse Input Conditions at Ta = -30°C to +85°C, VSS = 0V Parameter High/low level pulse width Symbol tPIH(1) tPIL(1) tPIH(2) tPIL(2) tPIH(3) tPIL(3) tPIH(4) tPIL(4) tPIL(5) tPIH(6) tPIL(6) •INT0, INT1 •INT2/T0IN INT3/T0IN (The noise rejection clock is selected to 1tCYC.) INT3/T0IN (The noise rejection clock is selected to 16tCYC.) INT3/T0IN (The noise rejection clock is selected to 64tCYC.) RES HS, VS Reset acceptable •Display position controllable •The active edge of HS and VS must be apart at least 1 tCYC. •Refer to figure 6. Rising/falling time External OSD clock input tTHL tTLH tOSCK OSDCK (P16) Refer to figure 7. 4.5 to 5.5 10 ns HS Refer to figure 6. 4.5 to 5.5 500 ns 4.5 to 5.5 3 4.5 to 5.5 200 •Interrupt acceptable •Timer0-countable 4.5 to 5.5 128 •Interrupt acceptable •Timer0-countable 4.5 to 5.5 32 tCYC Pins Conditions VDD[V] •Interrupt acceptable •Timer0-countable •Interrupt acceptable •Timer0-countable 4.5 to 5.5 2 4.5 to 5.5 min 1 Specification typ max unit µs AD Converter Characteristics at Ta = -30°C to +85°C, VSS = 0V Parameter Resolution Absolute precision Conversion time tCAD ADCR2=0 (Note 4) ADCR2=1 (Note 4) Analog input voltage range Analog port input current IAINH IAINL VAIN AN4 - AN7 (LC863300: AN3-AN7) VAIN=VDD VAIN=VSS -1 4.5 to 5.5 VSS 16 32 VDD 1 V Symbol N ET (Note 3) Pins Conditions VDD[V] min typ 8 ±1.5 Limits max unit bit LSB tCYC µA Note 3: Absolute precision does not include quantizing error (1/2LSB). Note 4: Conversion time is the time till the complete digital conversion value for analog input value is set to a register after the instruction to start conversion is sent. No.A0121-19/25 LC86F3G64A Sample Current Dissipation Characteristics at Ta = -30°C to +85°C, VSS = 0V The sample current dissipation characteristics is the measurement result of Sanyo provided evaluation board when the recommended circuit parameters shown in the sample oscillation circuit characteristics are used externally. The currents through the output transistors and the pull-up MOS transistors are ignored. Parameter Current dissipation during basic operation (Note 3) IDDOP(2) Symbol IDDOP(1) Pins VDD Conditions VDD[V] •FmX’tal=32.768kHz X’tal oscillation •System clock: VCO for system •VCO for OSD operating •Internal RC oscillation stops •FmX’tal=32.768kHz X’tal oscillation •System clock: X'tal (Instruction cycle time: 366.2µs) •VCO for system, VCO for OSD, Internal RC oscillation stop •Data slicer, AD converters stop Current dissipation in HALT mode (Note 3) IDDHALT(1) •HALT mode •FmX’tal=32.768kHz X’tal oscillation •VCO for system stops •System clock: VCO for system • Internal RC stops IDDHALT(2) •HALT mode •FmX’tal=32.768kHz X’tal oscillation •VCO for system stops •VCO for OSD stops •System clock: Internal RC IDDHALT(3) •HALT mode •FmX’tal=32.768kHz X’tal oscillation •VCO for system stops •VCO for OSD stops •System clock: X’tal (Instruction cycle time: 366.2µs) Current dissipation in HOLD mode (Note 3) IDDHOLD •HOLD mode •All oscillation stops. 4.5 to 5.5 0.05 20 µA 4.5 to 5.5 40 200 µA 4.5 to 5.5 350 1000 4.5 to 5.5 3 9 mA 4.5 to 5.5 60 300 µA 4.5 to 5.5 12 24 mA min Specification typ max unit Note 3: The currents of the output transistors and the pull-up MOS transistors are ignored. No.A0121-20/25 LC86F3G64A Recommended Oscillation Circuit and Sample Characteristics The sample oscillation circuit characteristics in the table below is based on the following conditions: Recommended circuit parameters are verified by an oscillator manufacturer using a Sanyo provided oscillation evaluation board. Sample characteristics are the result of the evaluation with the recommended circuit parameters connected externally. Recommended oscillation circuit and sample characteristics (Ta = -30°C to +85°C) Frequency 32.768kHz Manufacturer SEIKO EPSON Oscillator C1 C-002RX 18pF Recommended circuit parameters C2 18pF Rf OPEN Rd 680kΩ Operating supply voltage range 4.5 to 5.5V Oscillation stabilizing time typ 1.0s max 1.5s Notes Notes: The oscillation stabilizing time period is the time until the VCO oscillation for the internal system becomes stable after the following conditions. (Refer to Figure 2.) 1. The VDD becomes higher than the minimum operating voltage after the power is supplied. 2. The HOLD mode is released. The sample oscillation circuit characteristics may differ applications. For further assistance, please contact with oscillator manufacturer with the following notes in your mind. • Since the oscillation frequency precision is affected by wiring capacity of the application board, etc., adjust the oscillation frequency on the production board. • The above oscillation frequency and the operating supply voltage range are based on the operating temperature of -30°C to +85°C. For the use with the temperature outside of the range herein, or in the applications requiring high reliability such as car products, please consult with oscillator manufacturer. • When using the oscillator which is not shown in the sample oscillation circuit characteristics, please consult with Sanyo sales personnel. Since the oscillation circuit characteristics are affected by the noise or wiring capacity because the circuit is designed with low gain in order to reduce the power dissipation, refer to the following notices. • The distance between the clock I/O terminal (XT1 terminal XT2 terminal) and external parts should be as short as possible. • The capacitors’ VSS should be allocated close to the microcontroller’s GND terminal and be away from other GND. • The signal lines with rapid state changes or with large current should be allocated away from the oscillation circuit. XT1 Rf XT2 Rd C1 X’tal C2 Figure 1 Recommended Oscillation Circuit No.A0121-21/25 LC86F3G64A Power supply VDD VDD limit 0V Reset time RES Internal RC resonator oscillation XT1,XT2 tmsVCO VCO for system stable Operation mode Unfixed Reset Instruction execution mode Reset Time and Oscillation Stabilizing Time HOLD release signal Valid Internal RC resonator oscillation XT1, XT2 tmsVCO VCO for system stable Operation mode HOLD Instruction execution mode Hold release signal and oscillation stabilizing time. Figure 2 Oscillation Stabilizing Time No.A0121-22/25 LC86F3G64A VDD RRES RES CRES (Note) Determine the CRES, RRES value to get more than 200µs reset time. Figure 3 Reset Circuit 0.5VDD < AC timing measurement point > tCKCY tCKL SCK0 tICK SI0 tCKO SO0 SB0 50pF tCKI tCKH VDD < Timing > Figure 4 Serial Input/Output Test Condition < Test load > tPIL tPIH Figure 5 Pulse Input Timing Condition-1 No.A0121-23/25 LC86F3G64A tPIL(6) HS 0.75VDD 0.25VDD tTLH VS tPIL(6) Figure 6 Pulse Input Timing Condition - 2 HS OSDCK tOSCK tOSCK Note: tOSCK must be saving constant Figure 7 Pulse Input Timing Condition - 3 LC86F3G64A 10kΩ HS HS C536 Figure 8 Recommended Interface Circuit Noise filter 1µF C-Video 200Ω 1000pF Coupling capacitor CVIN Output impedance of C-Video before Noise filter should be less then 100Ω. Figure 9 CVIN Recommended Circuit No.A0121-24/25 LC86F3G64A 100Ω FILT + 33000pF 2.2µF 1MΩ Figure 10 FILT Recommended Circuit Note: Place FILT parts on board as close to the microcontroller as possible. P S Sr P SDA tBUF tHD;STA tR tF tHD;STA tsp SCL tLOW tHD;DAT tHIGH tSU;DAT tSU;STA tSU;STO S : start condition P : stop condition Sr : restart condition tsp : spike suppression Standard mode : not exist High speed mode : less than 50ns Figure 11 IIC Timing SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein. SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO Semiconductor Co.,Ltd. products described or contained herein are controlled under any of applicable local export control laws and regulations, such products may require the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written consent of SANYO Semiconductor Co.,Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO Semiconductor Co.,Ltd. product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. Upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third party. SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's intellctual property rights which has resulted from the use of the technical information and products mentioned above. T his catalog provides information as of November, 2006. Specifications and information herein are subject to change without notice. PS No.A0121-25/25