LC875148A

Ordering number : ENN*6715 CMOS IC LC875164A/48A/32A 8-Bit Single Chip Microcontroller with 64/48/32K-Byte ROM and 1024-Byte RAM On Chip Preliminary Overview The LC875164A/48A/32A microcontroller is 8-bit single chip microcontroller with the following on-chip functional blocks: - CPU: Operable at a minimum bus cycle time of 100ns - 64K/48K/32K bytes ROM - 1024 byte RAM - two high performance 16 bit timer/counters (can be divided into 8 bit units) - two 8 bit timers with prescalers - timer for use as date/time clock - two synchronous serial I/O ports (with automatic block transmit/receive function) - one asynchronous/synchronous serial I/O port - 12-bit PWM × 2 - 8-channel × 8-bit AD converter - high speed 8-bit parallel interface - 19-source 10-vectored interrupt system All of the above functions are fabricated on a single chip. Features (1) Read Only Memory - 65536 × 8 bits (LC875164A) - 49151 × 8 bits (LC875148A) - 32512 × 8 bits (LC875132A) Ver.1.03 O3098 91400 RM (IM) HK / SY No.6715-1/25 LC875164A/48A/32A (2) Bus Cycle Time - 100ns (10MHz) Note: The bus cycle time indicates ROM read time. (3) Minimum Instruction Cycle Time : 300ns (10MHz) (4) Ports - Input/output ports Each bit data direction programmable Nibble data direction programmable - Input ports - PWM Output ports - Oscillator pins - Reset pin - Power supply 59 8 2 2 2 1 6 (P1n,P2n,P3n,P70 to P73,P8n,PAn,PBn,PCn,S2Pn) (P0n) (XT1,XT2) (PWM0,PWM1) (CF1,CF2) ( RES ) (VSS1 to 3,VDD1 to 3) (5) Timers - Timer0: 16 bit timer/counter with capture register Mode 0: 2 channel 8 bit timer with programmable 8 bit prescaler and 8 bit capture register Mode 1: 8 bit timer with 8 bit programmable prescaler and 8 bit capture register + 8 bit counter with 8 bit capture register Mode 2: 16 bit timer with 8 bit programmable prescaler and 16 bit capture register Mode 3: 16 bit counter with 16 bit capture register - Timer1: PWM/16 bit timer/counter (with toggle output) Mode 0: 8 bit timer (with toggle output) + 8 bit timer counter (with toggle output) Mode 1: 2 channel 8 bit PWM Mode 2: 16 bit timer/counter (with toggle output) Mode 3: 16 bit timer (with toggle output) Lower order 8 bits can be used as PWM output. - Timer4: 8-bit timer with 6-bit prescaler - Timer5: 8-bit timer with 6-bit prescaler - Base timer 1. The clock signal can be selected from any of the following: sub-clock (32.768kHz crystal oscillator), system clock, and prescaler output for timer 0. 2. Interrupts can be selected to occur at one of five different times. (6) SIO - SIO0: 8 bit synchronous serial interface 1. LSB first/MSB first function available 2. Internal 8-bit baud-rate generator (maximum transmit clock period 4/3 TCYC) 3. Continuous automatic data communications (1 - 256 bits) - SIO1: 8 bit asynchronous/synchronous serial interface Mode 0: Synchronous 8 bit serial IO (2-wire or 3-wire, transmit clock 2 - 512 T CYC) Mode 1: Asynchronous serial IO (half duplex, 8 data bits, 1 stop bit, baud rate 8 - 2048 TCYC) Mode 2: Bus mode 1 (start bit, 8 data bits, transmit clock 2 - 512 TCYC) Mode 3: Bus mode 2 (start detection, 8 data bits, stop detection) - SIO2: 8 bit synchronous serial interface 1. LSB-first 2. Built in 8-bit baud-rate generator (Maximum clock period 4/3 TCYC) 3. Continuous automatic data communication (1 - 32 bytes) (7) AD converter - 8-bits × 8-channels (8) PWM - 2 channel synchronous variable 12 bit PWM (9) Parallel interface - RS, RD , WR , CS0 - CS2 Outputs (reversible polarity) - read/write possible in 1 TCYC No.6715-2/25 LC875164A/48A/32A (10) Remote control receiver circuit (connected to P73/INT3/T0IN terminal) - Noise rejection function (noise rejection filter time constant can selected from 1/32/128 TCYC) (11) Watchdog timer - The watchdog timer period set by external RC. - Watchdog timer can be set to produce interrupt, system reset (12) Interrupts - 19-source, 10-vectored interrupts: 1. Three level (low, high and highest) multiple interrupts are supported. During interrupt handling, an equal or lower level interrupt request is refused. 2. If interrupt requests to two or more vector addresses occur at once, the higher level interrupt takes precedence. In the case of equal priority levels, the vector with the lowest address takes precedence. No. 1 2 3 4 5 6 7 8 9 10 Vector 00003H 0000BH 00013H 0001BH 00023H 0002BH 00033H 0003BH 00043H 0004BH Selectable Level X or L X or L H or L H or L H or L H or L H or L H or L H or L H or L Interrupt signal INT0 INT1 INT2/T0L/INT4 INT3/INT5/Base timer T0H T1L/T1H SIO0 SIO1/SIO2 ADC Port 0/T4/T5/PWM0, 1 • Priority Level : X > H > L • For equal priority levels, vector with lowest address takes precedence. (13) Subroutine stack levels - 512 levels max. Stack is located in RAM (14) Multiplication and division - 16 bit × 8 bit (executed in 5 cycles) - 24 bit × 16 bit (12 cycles ) - 16 bit ÷ 8 bit (8 cycles) - 24 bit ÷ 16 bit (12 cycles) (15) Oscillation circuits - On-chip RC oscillation circuit used for system clock - On-chip CF oscillation circuit used for system clock - On-chip Crystal oscillation circuit used for system clock and time-base clock (16) Standby function - HALT mode HALT mode is used to reduce power consumption. Program execution is stopped. Peripheral circuits still operate. 1. Oscillation circuits are not stopped automatically 2. Release on system reset - HOLD mode HOLD mode is used to reduce the power dissipation. Both program execution and peripheral circuits are stopped. 1. CF, RC and crystal oscillation circuits stop automatically 2. Release occurs on any of the following conditions •input to the reset pin goes low •a specified level is input to at least one of INT0, INT1, INT2, INT4, INT5 •an interrupt condition arises at port 0 No.6715-3/25 LC875164A/48A/32A - X’tal HOLD mode X’tal HOLD mode is used to reduce power consumption. Program execution is stopped. All peripheral circuits except the base timer are stopped. 1. CF and RC oscillation circuits stop automatically 2. Crystal oscillator is maintained in its state at HOLD mode inception. 3. Release occurs on any of the following conditions •input to the reset pin goes low •a specified level is input to at least one of INT0, INT1, INT2, INT4, INT5 •an interrupt condition arises at port 0 •an interrupt condition arises at the base-timer (17) Factory shipment - delivery form QIP80E - delivery form SQFP80 (18) Development Tools - Evaluation chip - Emulator : LC876099 : EVA87000 + ECB875100 (Evaluation chip board) + POD875100 (POD) No.6715-4/25 LC875164A/48A/32A Pin Assignment P27/INT5/T1IN P26/INT5/T1IN P25/INT5/T1IN P24/INT5/T1IN P23/INT4/T1IN P21/INT4/T1IN P20/INT4/T1IN P22/INT4/T1IN SI2P3/SCK20 PB5/D5 PB6/D6 PB7/D7 PWM0 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 PB4/D4 PB3/D3 PB2/D2 PB1/D1 PB0/D0 VSS3 VDD3 PC7/A7 PC6/A6 PC5/A5 PC4/A4 PC3/A3 PC2/A2 PC1/A1 PC0/A0 PA0/CS2# 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 1 PA1/CS1# 2 PA2/CS0# 3 PA3/WR# 4 PA4/RD# 5 PA5/RS 6 P70/INT0/T0LCP 7 P71/INT1/T0HCP 8 P72/INT2/T0IN 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 P73/INT3/T0IN CF1 XT1 XT2 CF2 P80/AN0 P81/AN1 P82/AN2 P83/AN3 P84/AN4 P85/AN5 P86/AN6 P87/AN7 VDD1 RES# VSS1 40 39 38 37 36 35 34 SI2P2/SCK2 SI2P1/S12/SB2 SI2P0/SO2 P17/T1PWMH/BUZ P16/T1PWML P15/SCK1 P14/SI1/SB1 P13/SO1 P12/SCK0 P11/SI0/SB0 P10/SO0 P34 P33 P32 P31 P30 LC875164A/48A/32A QIP80 PWM1 VDD2 VSS2 P07 P06 P05 P04 P03 P02 P01 P00 33 32 31 30 29 28 27 26 25 Package Dimension (unit : mm) 3174 SANYO : QIP-80E No.6715-5/25 LC875164A/48A/32A Pin Assignment P27/INT5/T1IN P26/INT5/T1IN P25/INT5/T1IN P24/INT5/T1IN P23/INT4/T1IN P22/INT4/T1IN P21/INT4/T1IN P20/INT4/T1IN PB7/D7 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 PB6/D6 PB5/D5 PB4/D4 PB3/D3 PB2/D2 PB1/D1 PB0/D0 VSS3 VDD3 PC7/A7 PC6/A6 PC5/A5 PC4/A4 PC3/A3 PC2/A2 PC1/A1 PC0/A0 PA0/CS2# PA1/CS1# PA2/CS0# 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 1 PA3/WR# 2 PA4/RD# 3 PA5/RS 4 P70/INT0/T0LCP 5 P71/INT1/T0HCP 6 P72/INT2/T0IN 7 P73/INT3/T0IN 8 RES# 9 10 11 12 13 14 15 16 17 18 19 20 VDD1 XT1 XT2 CF1 CF2 P80/AN0 P81/AN1 P82/AN2 P83/AN3 P84/AN4 P85/AN5 VSS1 40 39 38 37 36 35 34 33 32 PWM1 SI2P3/SCK20 SI2P2/SCK2 SI2P1/SI2/SB2 SI2P0/SO2 P17/T1PWMH/BUZ P16/T1PWML P15/SCK1 P14/SI1/SB1 P13/SO1 P12/SCK0 P11/SI0/SB0 P10/SO0 P34 P33 P32 P31 P30 P87/AN7 P86/AN6 LC875164A/48A/32A SQFP80 PWM0 31 30 29 28 27 26 25 24 23 22 21 Package Dimension (unit : mm) 3220 VDD2 VSS2 P07 P06 P05 P04 P03 P02 P01 P00 SANYO : SQFP-80 No.6715-6/25 LC875164A/48A/32A QIP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 NAME PA1/ CS1 PA2/ CS0 PA3/ WR PA4/ RD PA5/RS P70/INT0/T0LCP P71/INT1/T0HCP P72/INT2/T0IN P73/INT3/T0IN RES XT1 XT2 VSS1 CF1 CF2 VDD1 P80/AN0 P81/AN1 P82/AN2 P83/AN3 P84/AN4 P85/AN5 P86/AN6 P87/AN7 P30 P31 P32 P33 P34 P10/SO0 P11/SI0/SB0 P12/SCK0 P13/SO1 P14/SI1/SB1 P15/SCK1 P16/T1PWML P17/T1PWMH/BUZ SI2P0/SO2 SI2P1/SI2/SB2 SI2P2/SCK2 SQFP 79 80 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 QIP 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 NAME SI2P3/SCK20 PWM1 PWM0 VDD2 VSS2 P00 P01 P02 P03 P04 P05 P06 P07 P20/INT4/T1IN P21/INT4/T1IN P22/INT4/T1IN P23/INT4/T1IN P24/INT5/T1IN P25/INT5/T1IN P26/INT5/T1IN P27/INT5/T1IN PB7/D7 PB6/D6 PB5/D5 PB4/D4 PB3/D3 PB2/D2 PB1/D1 PB0/D0 VSS3 VDD3 PC7/A7 PC6/A6 PC5/A5 PC4/A4 PC3/A3 PC2/A2 PC1/A1 PC0/A0 PA0/ CS2 SQFP 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 No.6715-7/25 LC875164A/48A/32A System Block Diagram Interrupt control IR PLA ROM Standby control Clock Generator CF RC Xtal PC SIO0 Bus Interface ACC SIO1 Port 0 B Register SIO2 Port 1 C Register Timer 0 Port 3 ALU Timer 1 Port 7 Timer 4 Port 8 PSW Timer 5 ADC RAR INT0-3 Noise Rejection Filter Port 2 INT4,,5 Stack Pointer PWM0 RAM PWM1 Base Timer Parallel interface Port A Port B Port C Watch Dog Timer No.6715-8/25 LC875164A/48A/32A Pin Assignment Pin Name VSS1 VSS2 VSS3 VDD1 VDD2 VDD3 Port 0 P00 - P07 I/O Pin Function Negative power supply Option No - Positive power supply No I/O Port 1 P10 - P17 I/O Port 2 P20 - P27 I/O •8-bit Input/output port •Data direction can be specified in nibble units •Use of pull-up resistor can be specified in nibble units •HOLD-release input •Input for port 0 interrupt •8-bit Input/output port •Data direction can be specified for each bit •Use of pull-up resistor can be specified for each bit •Other functions P10: SIO0 data output P11: SIO0 data input/bus input/output P12: SIO0 clock input/output P13: SIO1 data output P14: SIO1 data input/bus input/output P15: SIO1 clock input/output P16: Timer 1 PWML output P17: Timer 1 PWMH output/Buzzer output •8-bit Input/output port •Data direction can be specified for each bit •Use of pull-up resistor can be specified for each bit •Other functions P20-P23: INT4 input/HOLD release input/timer 1 event input /Timer 0L capture input/Timer 0H capture input P24-P27: INT5 input/HOLD release input/timer 1 event input /Timer 0L capture input /Timer 0H capture input Interrupt receiver format Rising Falling Rising/ H level falling INT4 Yes Yes Yes No INT5 Yes Yes Yes No •5-bit Input/output port •Data direction can be specified for each bit •Use of pull-up resistor can be specified for each bit •4-bit Input/output port •Data direction can be specified for each bit •Use of pull-up resistor can be specified for each bit •Other functions P70: INT0 input/HOLD release input/Timer0L capture input /Output for watchdog timer P71: INT1 input/HOLD release input/Timer0H capture input P72: INT2 input/HOLD release input/timer 0 event input /Timer0L capture input P73: INT3 input(noise rejection filter attached input) /timer 0 event input/Timer0H capture input Interrupt receiver format Rising Falling Rising/ H level falling Yes No Yes Yes INT0 Yes No Yes Yes INT1 No Yes Yes Yes INT2 No Yes Yes Yes INT3 Yes Yes Yes L level No No Yes Port 3 P30 - P34 Port 7 P70 - P73 I/O I/O No L level Yes Yes No No (Continued) No.6715-9/25 LC875164A/48A/32A Name Port 8 P80 - P87 I/O I/O Function description •8-bit Input/output port •Data direction can be specified for each bit •Other functions P80-P87: AD input port •6-bit Input/output port •Data direction can be specified for each bit •Use of pull-up resistor can be specified for each bit •Other functions PA0: Parallel interface output CS2 PA1: Parallel interface output CS1 PA2: Parallel interface output CS0 PA3: Parallel interface output WR PA4: Parallel interface output RD PA5: Parallel interface output RS •8-bit Input/output port •Data direction can be specified for each bit •Use of pull-up resistor can be specified for each bit •Other functions PB0-PB7: Parallel interface data input/output; address output •8-bit Input/output port •Data direction can be specified for each bit •Use of pull-up resistor can be specified for each bit •Other functions PC0-PC7: Parallel interface address output •4-bit Input/output port •Data direction can be specified for each bit •Other functions SI2P0: SIO2 data output SI2P1: SIO2 data output/bus input/output SI2P2: SIO2 clock input/output SI2P3: SIO2 clock output PWM0 output port PWM1 output port Reset terminal •Input for 32.768kHz crystal oscillation •Other function Input port When not in use, connect to VDD1. •Output for 32.768kHz crystal oscillation •Other function General purpose input port When not in use, set to oscillation mode and leave open circuit Input terminal for ceramic oscillator Output terminal for ceramic oscillator Option No Port A PA0 - PA5 I/O Yes Port B PB0 - PB7 I/O Yes Port C PC0 - PC7 I/O Yes SIO2 Port SI2P0 - SI2P3 I/O No PWM0 PWM1 RES O O I I No No No No XT1 XT2 I/O No CF1 CF2 I O No No No.6715-10/25 LC875164A/48A/32A Port Output Configuration Output configuration and pull-up resistor options are shown in the following table. Input is possible even when port is set to output mode. Terminal P00-P07 P10-P17 P20-P27 P30-P34 PA0-PA5 PB0-PB7(*) PC0-PC7 P70 P71-P73 P80-P87 SI2P0, SI2P2 SI2P3 PWM0, PWM1 SI2P1 XT1 XT2 Option applies to: 1 bit units each bit Option 1 2 1 2 1 2 None None None None CMOS Nch-open drain CMOS Nch-open drain CMOS Nch-open drain Nch-open drain CMOS Nch-open drain CMOS Output Format Pull-up resistor Programmable (Note 1) None Programmable Programmable Programmable Programmable Programmable Programmable None None each bit - - None None None CMOS (When used as standard port) Nch-open drain (When used for SIO2 data) Input only Output for 32.768kHz crystal oscillation None None None Note 1 Programmable pull-up resisters of Port 0 can be attatched in nibble units (P00-03, P04-07). (*) When in parallel interface mode, PB0-PB7 output format is CMOS, regardless of any selected option. Note: Connect as follows to reduce noise on VDD and increase the back-up time. VSS1, VSS2 and VSS3 must be connected together and grounded. The voltage of Port 7 should be fixed. Example 1 : In hold mode, during backup, port output ‘H’ level is supplied from the back-up capacitor. LSI Power Supply Back-up capacitor VDD1 VDD2 VDD3 VSS1 VSS2 VSS3 Example 2 : During backup in hold mode output is not held high and its value in unsettled. LSI Power Supply Back-up capacitor VDD1 VDD2 VDD3 VSS1 VSS2 VSS3 No.6715-11/25 LC875164A/48A/32A 1. Absolute Maximum Ratings at Ta=25°C, VSS1=VSS2=VSS3=0V Parameter Supply voltage Input voltage Output voltage Input/output voltage Symbol VDDMAX VI(1) VO(1) VIO(1) Pins VDD1, VDD2, VDD3 XT1, XT2, CF1 PWM0, PWM1 Ports 0, 1, 2 Ports 3, 7, 8 Ports A, B, C SI2P00-SI2P03 PWM0, PWM1 Ports 0, 1, 2, 3 Ports A, B, C SI2P00-SI2P03 PWM0, PWM1 P71-P73 P71-P73 Port 1 PWM0, PWM1 Port 3 SI2P00-SI2P03 Ports 0, 2 Port B Ports A, C P02-P07 Ports 1, 2, 3 Ports A, B, C SI2P00-SI2P03 PWM0, PWM1 P00, P01 Ports 7, 8 Port 7 Port 8 Port 1 PWM0, PWM1 Port 3 SI2P00-SI2P03 Ports 0, 2 Port B Ports A, C QIP80E SQFP80 Conditions VDD1=VDD2 =VDD3 Ratings typ. unit V VDD[V] min. -0.3 -0.3 -0.3 -0.3 max. +7.0 VDD+0.3 VDD+0.3 VDD+0.3 High level output current Peak output current IOPH(1) •CMOS output •For each pin. -10 mA Total output current IOPH(2) ΣIOAH(1) ΣIOAH(2) For each pin. The total of all pins. The total of all pins. -5 -5 -30 Low level output current Peak output current ΣIOAH(3) ΣIOAH(4) ΣIOAH(5) IOPL(1) The total of all pins. The total of all pins. The total of all pins. For each pin. -20 -20 -20 20 Total output current IOPL(2) IOPL(3) ΣIOAL(1) ΣIOAL(2) ΣIOAL(3) For each pin. For each pin. The total of all pins. The total of all pins. The total of all pins. 30 5 15 15 50 Maximun power dissipation Operating temperature range Storage temperature range ΣIOAL(4) ΣIOAL(5) ΣIOAL(6) Pdmax Topg The total of all pins. The total of all pins. The total of all pins. Ta=-30 to +70°C -30 70 40 40 350 70 mW °C Tstg -55 125 No.6715-12/25 LC875164A/48A/32A 2. Recommended Operating Range at Ta=-30°C to +70°C, VSS1=VSS2=VSS3=0V Parameter Operating supply voltage range HOLD voltage Symbol VDD(1) Pins VDD1=VDD2 =VDD3 Conditions 0.294µs ≤ tCYC ≤ 200µs 0.588µs ≤ tCYC ≤ 200µs RAM and the register data are kept in HOLD mode. 2.5 - 6.0 Ratings typ. unit V VDD[V] min. 4.5 2.5 2.0 max. 6.0 6.0 6.0 VHD VDD1=VDD2 =VDD3 •Ports 1, 2 •P71-P73 •P70 port input /interrupt •Ports 0, 8 •Ports A, B, C Port 70 Watchdog timer input XT1, XT2, CF1, RES •Ports 1, 2 •P71-P73 •P70 port input /interrupt •Ports 0, 8 •Ports A, B, C Port 70 Watchdog timer input XT1, XT2, CF1, RES Input high voltage VIH(1) 0.3VDD +0.7 VDD VIH(2) VIH(3) VIH(4) Input low voltage VIL(1) 2.5 - 6.0 0.3VDD +0.7 VDD VDD VDD 0.1VDD +0.4 2.5 - 6.0 0.9VDD 2.5 - 6.0 0.75VDD 2.5 - 6.0 VSS VIL(2) VIL(5) VIL(6) Operation cycle time External system clock frequency tCYC FEXCF(1) 2.5 - 6.0 2.5 - 6.0 2.5 - 6.0 4.5 - 6.0 2.5 - 6.0 4.5 - 6.0 2.5 - 6.0 4.5 - 6.0 2.5 - 6.0 VSS VSS VSS 0.294 0.588 0.1 0.15VDD +0.4 0.8VDD -1.0 0.25VDD CF1 •CF2 open circuit •system clock divider set to 1/1 •external clock DUTY=50±5% •CF2 open circuit •system clock divider set to 1/2 200 200 10 µs MHz 0.2 20.4 (Note 1) The oscillation constant is shown in Tables 1 and 2. No.6715-13/25 LC875164A/48A/32A 3. Electrical Characteristics at Ta=-30°C to +70°C, VSS1=VSS2=VSS3=0V Parameter Input high current Symbol IIH(1) Pins •Ports 0, 1, 2 •Ports 3, 7, 8 •Ports A, B, C •SI2P00-SI2P03 • RES •PWM0, PWM1 XT1, XT2 Conditions •Output disable •Pull-up resistor off •VIN=VDD (including off state leak current of output Tr.) When specified as an input port. VIN=VDD VIN=VDD •Output disable •Pull-up resistor off •VIN=VSS (including off state leak current of output Tr.) When specified as an input port VIN=VSS VIN=VSS IOH=-2.0mA IOH=-0.1mA IOH=-5.0mA IOH=-1.0mA IOH=-1.0mA IOL=10mA IOL=1.6mA IOL=1.0mA IOL=30mA IOL=1mA IOL=0.5mA IOL=15mA IOL=2mA VOH=0.9VDD Ratings typ. unit µA VDD[V] 2.5 - 6.0 min. max. 1 IIH(2) 2.5 - 6.0 1 IIH(3) Input low current IIL(1) CF1 •Ports 0, 1, 2 •Ports 3, 7, 8 •Ports A, B, C •SI2P00-SI2P03 • RES •PWM0, PWM1 XT1, XT2 2.5 - 6.0 2.5 - 6.0 -1 15 IIL(2) 2.5 - 6.0 -1 IIL(3) Output high current VOH(1) VOH(2) VOH(3) VOH(4) VOH(5) VOL(1) VOL(2) VOL(3) VOL(4) VOL(5) VOL(6) VOL(7) VOL(8) Rpu CF1 •Ports 0, 1, 2, 3 •Ports B, C •SI2P00-SI2P03 •PWM0, PWM1 Port A Port 7 •Ports 0, 1, 2, 3 •Ports B, C •SI2P00-SI2P03 •PWM0, PWM1 P00, P01 Ports 7, 8 Port A •Ports 0, 1, 2, 3 •Port 7 •Ports A, B, C RES All pins 2.5 - 6.0 4.5 - 6.0 -15 VDD-1 V 2.5 - 6.0 VDD-0.5 4.5 - 6.0 VDD-1 2.5 - 6.0 VDD-0.5 2.5 - 6.0 VDD-1 4.5 - 6.0 2.5 - 6.0 2.5 - 6.0 4.5 - 6.0 4.5 - 6.0 2.5 - 6.0 4.5 - 6.0 2.5 - 6.0 4.5 - 5.5 Output low current 1.5 0.4 0.4 1.5 0.4 1.5 0.4 70 V Pull-up resistor Hysteresis voltage Pin capacitance 15 40 kΩ VHIS CP 4.5 - 5.5 •Every other terminal connected to VSS. •f=1MHz •Ta=25°C 4.5 - 5.5 0.1VDD 10 V pF No.6715-14/25 LC875164A/48A/32A 4. Serial Input/Output Characteristics at Ta=-30°C to +70°C, VSS1=VSS2=VSS3=0V Parameter Cycle Low level pulse width Symbol tSCK(1) tSCKL(1) tSCKLA(1) Input clock High level pulse width tSCKH(1) tSCKHA(1) Cycle Low level pulse width High level pulse width Cycle Low level pulse width tSCK(2) tSCKL(2) tSCKH(2) tSCK(3) tSCKL(3) tSCKLA(2) SCK0(P12), SI2P2 SI2P3 •Use pull-up resistor (1kΩ) when output is open drain. •Refer to figure 6 SCK0(P12) SIO0 SI2P2, SI2P3 SIO2 2.5 - 6.0 SCK1(P15) Refer to figure 6 2.5 - 6.0 Pins SCK0(P12), SI2P2 Conditions Refer to figure 6 Ratings typ. unit tCYC VDD[V] 2.5 - 6.0 min. 2 1 1 1 3(SIO0) 2 1 1 4/3 max. Serial clock 1/2 3/4 1 1/2 tSCK Output clock High level pulse width tSCKH(3) tSCKHA(2) SCK0(P12) SIO0 SI2P2, SI2P3 SIO2 •CMOS output option •Refer to figure 6 2 7/4 2.5 - 6.0 2 1/2 1/2 tCYC tSCK Cycle Low level pulse width High level pulse width Data set-up time Data hold time Output delay time tSCK(4) tSCKL(4) tSCKH(4) tsDI SCK1(P15) Serial input thDI SB0(P11), SB1(P14), SI2P1 SI0 SI1 SO0(P10), SO1(P13), SB0(O11), SB1(P14), SI2P0, SI2P1 •Data set-up to SI0CLK •Refer to figure 6 4.5 - 6.0 2.5 - 6.0 4.5 - 6.0 2.5 - 6.0 0.03 µs 0.03 tdD0 •Data set-up to SI0CLK •When port is open drain: Time delay from SI0CLK trailing edge to the SO data change. •Refer to figure 6 4.5 - 6.0 1/3tCYC +0.05 1/3tCYC +0.05 Serial output 2.5 - 6.0 No.6715-15/25 LC875164A/48A/32A 5. Parallel Input/Output Characteristics at Ta=-30°C to +70°C, VSS1=VSS2=VSS3=0V Note: Port A terminals used as RS, WR , RD and CS should be set to CMOS format. Please refer to figures 8 and 9 for parallel output timing waveforms. Parameter Symbol Pins Conditions Ratings typ. 1 unit tCYC tCYC & ns Write cycle, Read tC(1) cycle Address set-up tsA(1) time tsA(2) Address hold time thA(1) thA(2) RS set-up tie tsRS(1) VDD[V] 2.5 - 6.0 2.5 - 6.0 2.5 - 6.0 2.5 - 6.0 2.5 - 6.0 2.5 - 6.0 min. max. • WR (PA3), PB0-PB7 • RD (PA4), PC0-PC7 RD (PA4), PC0-PC7 RD (PA4), PC0-PC7 WR (PA3), PC0-PC7 WR (PA3), RS(PA5), From address set-up until control signal changes 1/3tCYC -30ns 2/3tCYC -30ns 1/6tCYC 5 1/6tCYC -15ns 1/6tCYC -15ns 1/3tCYC -15ns 1/3tCYC -15ns 2/3tCYC -15ns 0 1/6tCYC 0 1/6tCYC 0 1/6tCYC -5ns 2/3tCYC -5ns 1/6tCYC -5ns 1/3tCYC -5ns 1/6 tCYC 2/3 tCYC 1/6 tCYC 1/3 tCYC From change of RD until address change From change of WR until address change From change of RS, CS until change in WR from change of RS until change in RD ns tCYC & ns CS (PAX) tsRS(2) tsRS(3) CS set-up time RD (PA4), RS(PA5) RD (PA4), RS(PA5) 2.5 - 6.0 2.5 - 6.0 2.5 - 6.0 2.5 - 6.0 2.5 - 6.0 2.5 - 6.0 2.5 - 6.0 2.5 - 6.0 2.5 - 6.0 2.5 - 6.0 2.5 - 6.0 2.5 - 6.0 2.5 - 6.0 tsCS(1) tsCS(2) RD (PA4), CS (PAX) From change in CS until change in RD WR CS (PAX) (PA3), From change in CS until change in WR From change in WR until change in RS From change in RD until change in RS, CS RS hold time thRS(1) thRS(2) thRS(3) thCS(1) thCS(2) tWRH(1) tWRH(2) tWRL(1) tWRL(2) WR (PA3), RS(PA5) ns tCYC & ns ns tCYC & ns ns tCYC & ns RD (PA4), RS(PA5), CS (PAX) RD (PA4), RS(PA5), CS (PAX) RD (PA4), RS(PA5) WR (PA3), RS(PA5) CS hold time From change in RD until change in CS From change in WR until change in CS WR ’H’ pulse width WR (PA3) WR (PA3) WR (PA3) WR (PA3) WR ’L’ pulse width (Continued) No.6715-16/25 LC875164A/48A/32A Parameter RD ’H’ pulse width Symbol tRDH(1) tRDH(2) Pins RD (PA4) RD (PA4) RD (PA4) RD (PA4) RD (PA4), PB0-PB7 RD (PA4), PB0-PB7 Conditions VDD[V] 2.5 - 6.0 2.5 - 6.0 2.5 - 6.0 2.5 - 6.0 RD ’L’ pulse width Data write permission delay tRDL(1) tRDL(2) tdDT(1) tdDT(2) min. 1/6tCYC -5ns 1/3tCYC -5ns 1/3tCYC -5ns 1/2tCYC -5ns Ratings typ. 1/6 tCYC 1/3 tCYC 1/3 tCYC 1/2 tCYC max. unit tCYC & ns Input data set-up time tsDTR(1) RD (PA4), PB0-PB7 Time for permission, from RD leading edge until input data set-up (Note 1) From input data setup to RD leading edge. (Note 2) From RD leading edge until input data hold From output data setup until WR leading edge From WR leading edge until output data hold 2.5 - 6.0 2.5 - 6.0 1/6tCYC -15ns 1/3tCYC -15ns 40 ns 2.5 - 6.0 Input data hold time Output data set-up time Output data set-up time Output data hold time thDTR(1) RD (PA4), PB0-PB7 2.5 - 6.0 0 ns tsDTW(1) tsDTW(2) thDTW(1) thDTW(2) RD (PA4), PB0-PB7 RD (PA4), PB0-PB7 RD (PA4), PB0-PB7 2.5 - 6.0 2.5 - 6.0 2.5 - 6.0 2.5 - 6.0 1/3tCYC -30ns 1/3tCYC -30ns 0 0 tCYC & ns ns Note 1 : Time until incorrect data of Low is disappeared. Note 2 : Incorrect data of Low is not output in the period between tRDL(1) - tdDT(1). 6. Pulse input Conditions at Ta=-30°C to +70°C, VSS1=VSS2=VSS3=0V Parameter High/low level pulse width Symbol tPIH(1) tPIL(1) Pins INT0(P70), INT1(P71), INT2(P72) INT4(P20-P23) INT5(P24-P27) INT3(P73) (The noise rejection clock select to 1/1.) INT3(P73) (The noise rejection clock select to 1/32.) INT3(P73) (The noise rejection clock select to 1/128.) RES Conditions •Interrupt acceptable •Events to timer 0 and 1 can be input. •Interrupt acceptable •Events to timer 0 can be input. •Interrupt acceptable •Events to timer 0 can be input. •Interrupt acceptable •Events to timer 0 can be input. Reset acceptable VDD[V] 2.5 - 6.0 min. 1 Ratings typ. max. unit tCYC tPIH(2) tPIL(2) 2.5 - 6.0 2 tPIH(3) tPIL(3) 2.5 - 6.0 64 tPIH(4) tPIL(4) 2.5 - 6.0 256 tPIL(5) 2.5 - 6.0 200 µs No.6715-17/25 LC875164A/48A/32A 7. AD Converter Characteristics at Ta=-30°C to +70°C, VSS1=VSS2=VSS3=0V Parameter Resolution Absolute precision Conversion time Symbol N ET TCAD Pins AN0(P80) - AN7(P87) Conditions Ratings typ. 8 unit bit LSB µs (Note 2) AD conversion time =32 × tCYC (ADCR2=0) (Note 3) AD conversion time =64 × tCYC (ADCR2=1) (Note 3) VDD[V] 3.0 - 6.0 3.0 - 6.0 3.0 - 6.0 min. max. ±1.5 15.10 (tCYC= 0.588µs) 97.92 (tCYC= 3.06µs) 3.0 - 6.0 15.10 (tCYC= 0.294µs) 97.92 (tCYC= 1.53µs) Analog input voltage range Analog port input current VAIN IAINH IAINL VAIN=VDD VAIN=VSS 3.0 - 6.0 3.0 - 6.0 3.0 - 6.0 VSS VDD 1 V µA -1 (Note 2) Absolute precision not including quantizing error (±1/2 LSB). (Note 3) Conversion time means time from executing AD conversion instruction to loading complete digital value to register. 8. Current Dissipation Characteristics at Ta=-30°C to +70°C, VSS1=VSS2=VSS3=0V Parameter Current flow during basic operation (Note 4) Symbol IDDOP(1) Pins VDD Conditions •FmCF=10MHz for Ceramic resonator oscillation •FsX’tal=32.768kHz for crystal oscillation •System clock: CF oscillation •Internal RC oscillation stopped. •FmCF=5MHz for Ceramic resonator oscillation •FsX’tal=32.768kHz for crystal oscillation •System clock: CF oscillation •Internal RC oscillation stopped. •FmCF=0Hz (oscillation stops) •FsX’tal=32.768kHz for crystal oscillation •System clock: Internal RC oscillation •FmCF=0Hz (oscillation stops) •FsX’tal=32.768kHz for crystal oscillation •System clock: X’tal oscillation •Internal RC oscillation stopped. Ratings typ. 16 unit mA VDD[V] 4.5 - 6.0 min. max. 29 IDDOP(2) IDDOP(3) 4.5 - 6.0 2.5 - 4.5 7 3 12 8 IDDOP(4) IDDOP(5) 4.5 - 6.0 2.5 - 4.5 1 0.5 3.0 2 IDDOP(6) 4.5 - 6.0 40 80 µA IDDOP(7) 2.5 - 4.5 15 46 (Continued) No.6715-18/25 LC875164A/48A/32A Ratings typ. 6 Parameter Symbol Pins Conditions •HALT mode •FmCF=10MHz for ceramic resonator oscillation •FsX’tal=32.768kHz for crystal oscillation •System clock: CF oscillation •Internal RC oscillation stopped. •HALT mode •FmCF=5MHz for Ceramic resonator oscillation •FsX’tal=32.768kHz for crystal oscillation •System clock: CF oscillation •Internal RC oscillation stopped. •HALT mode •FmCF=0Hz (oscillation stops) •FsX’tal=32.768kHz for crystal oscillation •System clock: Internal RC oscillation •HALT mode •FmCF=0Hz (oscillation stops) •FsX’tal=32.768kHz for crystal oscillation •System clock: X’tal oscillation •Internal RC oscillation stopped. HOLD mode Current flow: IDDHALT(1) VDD HALT mode (Note 4) VDD[V] 4.5 - 6.0 min. max. 13 unit mA IDDHALT(2) IDDHALT(3) 4.5 - 6.0 2.5 - 4.5 3 1.2 5 3 IDDHALT(4) IDDHALT(5) 4.5 - 6.0 2.5 - 4.5 500 300 1500 1000 µA IDDHALT(6) IDDHALT(7) 4.5 - 6.0 2.5 - 4.5 25 8 70 30 Current flow: IDDHOLD(1) VDD1 HOLD mode IDDHOLD(2) (Note 4) IDDHOLD(2) VDD1 Current flow: Date/time clock HOLD mode 4.5 - 6.0 2.5 - 4.5 4.5 - 6.0 2.5 - 4.5 0.01 0.01 45 6 30 30 100 36 µA µA Date/time clock HOLD mode •CF1=VDD or open circuit (when using external clock) •FmX’tal=32.768kHz for crystal oscillation (Note 4) The currents of output transistors and pull-up MOS transistors are ignored. No.6715-19/25 LC875164A/48A/32A Main system clock oscillation circuit characteristics The characteristics in the table bellow is based on the following conditions: 1. Use the standard evaluation board SANYO has provided. 2. Use the peripheral parts with indicated value externally. 3. The peripheral parts value is a recommended value of oscillator manufacturer. Table 1. Main system clock oscillation circuit characteristics using ceramic resonator Circuit Parameters Frequency Manufacturer Murata Kyocera 5MHz Murata Oscillator C1 C2 Rd1 0Ω 0Ω 0Ω 0Ω 0Ω Operating supply voltage range 4.5 - 6.0V 4.5 - 6.0V 4.5 - 6.0V 4.5 - 6.0V 4.5 - 6.0V 4.5 - 6.0V 4.5 - 6.0V 4.5 - 6.0V Oscillation stabilizing time typ 0.05ms 0.05ms 0.05ms 0.05ms 0.05ms 0.05ms 0.05ms 0.05ms max 0.50ms 0.50ms 0.50ms 0.50ms 0.50ms 0.50ms 0.50ms 0.50ms Notes 10MHz CSA10.0MTZ 33pF 33pF CST10.0MTW (30pF) (30pF) KBR-10.0M 33pF 33pF CSA5.00MG 33pF 33pF CST5.00MGW (30pF) (30pF) Built in C1,C2 Built in C1,C2 4MHz Murata Kyocera CSA4.00MG 33pF 33pF 0Ω CST4.00MGW (30pF) (30pF) 0Ω KBR-4.0MSA 33pF 33pF 0Ω Built in C1,C2 *The oscillation stabilizing time is a period until the oscillation becomes stable after VDD becomes higher than minimum operating voltage. (Refer to Figure4) Subsystem clock oscillation circuit characteristics The characteristics in the table bellow is based on the following conditions: 1. Use the standard evaluation board SANYO has provided. 2. Use the peripheral parts with indicated value externally. 3. The peripheral parts value is a recommended value of oscillator manufacturer. Table 2. Subsystem clock oscillation circuit characteristics using crystal oscillator Frequency 32.768kHz Manufacturer Seiko EPSON Oscillator C-002Rx Circuit Parameters Operating supply voltage range C3 C4 Rf Rd2 12pF 15pF OPEN 300kΩ 4.5 - 6.0V Oscillation stabilizing time typ max 1.0S 3.0S Notes *The oscillation stabilizing time is a period until the oscillation becomes stable after executing the instruction which starts the sub-clock oscillation or after releasing the HOLD mode. (Refer to Figure4) (Notes) •Since the circuit pattern affects the oscillation frequency, place the oscillation-related parts as close to the oscillation pins as possible with the shortest possible pattern length. CF1 CF2 Rd1 XT1 XT2 Rf Rd2 C1 CF C2 C3 X’tal C4 Figure 1 Ceramic oscillation circuit Figure 2 Crystal oscillation circuit 0.5VDD Figure 3 AC timing measurement point No.6715-20/25 LC875164A/48A/32A VDD Power Supply VDD limit GND Reset time RES# Internal RC Resonator oscillation tmsCF CF1,CF2 tmsXtal XT1,XT2 Operation mode Unfixed Reset Instruction execution mode Reset time and oscillation stable time HOLD release signal Without HOLD Release signal HOLD release signal VALID Internal RC Resonator oscillation tmsCF CF1,CF2 tmsXtal XT1,XT2 Operation mode HOLD HALT HOLD release signal and oscillation stable time Figure 4 Oscillation stabilizing time No.6715-21/25 LC875164A/48A/32A VDD RRES (Note) RES CRES Set CRES, RRES values such that reset time exceeds 200µs. Figure 5 Reset circuit SI0CLK: DATAIN: DI0 DI1 DI2 DI3 DI4 DI5 DI6 DI7 DI8 DATAOUT: DO0 DO1 DO2 DO3 DO4 DO5 DO6 DO7 Data RAM transmission period (only SIO0,2) DO8 tSCK tSCKL SI0CLK: tsDI DATAIN: tdDO DATAOUT: Data RAM transmission period (only SIO0,2) tSCKH thDI tSCKLA SI0CLK: tsDI DATAIN: tdDO DATAOUT: thDI tSCKHA Figure 6 Serial input/output test condition tPIL tPIH Figure 7 Pulse input timing condition No.6715-22/25 LC875164A/48A/32A • Parallel Input/Output timing waveform : Indirect Setting, Read Mode tC(1) read cycle ADR/DATA: addr tsA(1) CS#: tsRS(1) RS: tWRH(1) WR#: tRDH(1) RD#: tdDT(1) DATAin: H thDTR(1) data tsDTR(1) tWRL(1) tsRS(2) tRDL(1) thRS(2) thRS(1) Note: Port A terminals used as RS, WR , RD and CS should be set to CMOS format. • Parallel Input/Output timing waveform : Indirect Setting, Write Mode tC(1) write cycle ADR/DATA: tsA(1) CS#: tsRS(1) RS: tWRH(1) WR#: tWRL(2) RD#: tWRL(1) tsRS(3) tsDTW(1) thRS(1) thRS(3) addr data thDTW(1) DATAin: Note: Port A terminals used as RS, WR , RD and CS should be set to CMOS format. Figure 8 Indirect mode: Parallel Timing Waveforms No.6715-23/25 LC875164A/48A/32A • Parallel Input/Output timing waveform : Direct Setting, Read Mode tC(1) read cycle ADR: tsA(1) CS#: tsCS(1) DATA: tRDL(2) WR#: tRDH(2) RD#: tdDT(2) DATAin: H thDTR(1) data tsDTR(1) thCS(1) addr thA(1) Note: Port A terminals used as RS, WR , RD and CS should be set to CMOS format. • Parallel Input/Output timing waveform : Direct Setting, Write Mode tC(1) write cycle ADR: tsA(2) CS#: tsCS(2) DATA: data tsDTW(2) WR#: tWRH(2) RD#: tWRL(2) thDTW(2) thCS(2) addr thA(2) DATAin: Note: Port A terminals used as RS, WR , RD and CS should be set to CMOS format. Figure 9 Direct Mode: Parallel Input/Output Timing Diagrams No.6715-24/25 LC875164A/48A/32A memo: PS No.6715-25/25