LC875G08A

Ordering number : EN8299B LC875G32A LC875G24A LC875G16A LC875G08A Overview CMOS IC ROM 32K/24K/16K/8K byte, RAM 1024 byte on-chip 8-bit 1-chip Microcontroller The SANYO LC875G32A/24A/16A/08A are 8-bit microcomputer that, centered around a CPU running at a minimum bus cycle time of 100ns, integrates on a single chip a number of hardware features such as 32K/24K/16K/8K-byte ROM, 1024-byte RAM, sophisticated 16-bit timers/counters (may be divided into 8-bit timers), a 16-bit timer/counter (may be divided into 8-bit timers/counters or 8-bit PWMs), four 8-bit timers with a prescaler, a base timer serving as a time-ofday clock, a high-speed clock counter, a synchronous SIO interface (with automatic block transmission/reception capabilities), an asynchronous/synchronous SIO interface, a UART interface (full duplex), a 12-bit/8-bit 12-channel AD converter, two 12-bit PWM channels, a system clock frequency divider, and a 22-source 10-vector interrupt feature. Features ROM • 32768 × 8 bits (LC875G32A) • 24576 × 8 bits (LC875G24A) • 16384 × 8 bits (LC875G16A) • 8192 × 8 bits (LC875G08A) RAM • 1024 × 9 bits (LC875G32A/24A/16A/08A) Minimum Bus Cycle • 100ns (10MHz) Note: The bus cycle time here refers to the ROM read speed. Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment (home appliances, AV equipment, communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee thereof. If you should intend to use our products for applications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our customer shall be solely responsible for the use. Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer' s products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer' s products or equipment. Ver.3.00 52307HKIM 20070123-S00015 No.8299-1/23 LC875G32A/24A/16A/08A Minimum Instruction Cycle Time • 300ns (10MHz) Ports • Normal withstand voltage I/O ports Ports whose I/O direction can be designated in 1-bit units 30 (P1n,P2n,P30 to P36,P70 to P73,PWM0,PWM1,XT2) Ports whose I/O direction can be designated in 4-bit units 8 (P0n) • Normal withstand voltage input port 1 (XT1) • Dedicated oscillator ports 2 (CF1, CF2) • Reset pins 1 (RES) • Power pins 6 (VSS1 to 3, VDD1 to 3) Timers • Timer 0: 16-bit timer/counter with a capture register. Mode 0: 8-bit timer with an 8-bit programmable prescaler (with an 8-bit capture register) × 2-channels Mode 1: 8-bit timer with an 8-bit programmable prescaler (with an 8-bit capture register) + 8-bit counter (with an 8-bit capture register) Mode 2: 16-bit timer with an 8-bit programmable prescaler (with a 16-bit capture register) Mode 3: 16-bit counter (with a 16-bit capture register) • Timer 1 : 16-bit timer/counter that supports PWM/toggle outputs Mode 0: 8-bit timer with an 8-bit prescaler (with toggle outputs) + with an 8-bit prescaler 8-bit timer/counter (with toggle outputs) Mode 1: 8-bit PWM with an 8-bit prescaler × 2-channels Mode 2: 16-bit timer/counter with an 8-bit prescaler (with toggle outputs) (toggle outputs also possible from the lower-order 8-bits) Mode 3: 16-bit timer with an 8-bit prescaler (with toggle outputs) (the lower-order 8-bits can be used as PWM.) • Timer 4: 8-bit timer with a 6-bit prescaler • Timer 5: 8-bit timer with a 6-bit prescaler • Timer 6: 8-bit timer with a 6-bit prescaler (with toggle outputs) • Timer 7: 8-bit timer with a 6-bit prescaler (with toggle outputs) • Base timer 1) The clock is selectable from the subclock (32.768kHz crystal oscillation), system clock, and timer 0 prescaler output. 2) Interrupts programmable in 5 different time-schemes High-speed Clock Counter 1) Can count clocks with a maximum clock rate of 20MHz (at a main clock of 10MHz). 2) Can generate output real time. SIO • SIO 0: 8-bit synchronous serial interface 1) LSB first/MSB first mode selectable 2) Built-in 8-bit baudrate generator (maximum transfer clock cycle 4/3 tCYC) 3) Automatic continuous data transmission (1 to 256 bits, specifiable in 1-bit units, suspension and resumption of data transmission possible in 1 byte units) • SIO 1: 8-bit asynchronous/synchronous serial interface Mode 0: Synchronous 8-bit serial I/O (2- or 3-wire configuration, 2 to 512 tCYC transfer clocks) Mode 1: Asynchronous serial I/O (half-duplex, 8 data bits, 1 stop bit, 8 to 2048 tCYC baudrates) Mode 2: Bus mode 1 (start bit, 8 data bits, 2 to 512 tCYC transfer clocks) Mode 3: Bus mode 2 (start detect, 8 data bits, stop detect) UART • Full duplex • 7/8/9 bit data bits selectable • 1stop bit (2-bit in continuous data transmission) • Built-in baudrate generator No.8299-2/23 LC875G32A/24A/16A/08A AD Converter : 12-bits/8-bits×12-channels • 12-bits/8-bits AD converter selectable • Automatic reference voltage generation controllable PWM : Multifrequency 12-bit PWM×2-channels Remote Control Receiver Circuit (sharing pins with P73, INT3, and T0IN) • Noise rejection function (noise filter time constant selectable from 1 tCYC, 32 tCYC, and 128 tCYC) Watchdog Timer • External RC watchdog timer • Interrupt and reset signals selectable Interrupts • 22 sources, 10 vector addresses 1) Provides three levels (low (L), high (H), and highest (X)) of multiplex interrupt control. Any interrupt requests of the level equal to or lower than the current interrupt are not accepted. 2) When interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest level takes precedence over the other interrupts. For interrupts of the same level, the interrupt into the smallest vector address takes precedence. No. 1 2 3 4 5 6 7 8 9 10 Vector Address 00003H 0000BH 00013H 0001BH 00023H 0002BH 00033H 0003BH 00043H 0004BH Level X or L X or L H or L H or L H or L H or L H or L H or L H or L H or L INT0 INT1 INT2/T0L/INT4 INT3/INT5/base timer T0H T1L/T1H SIO0/UART1 receive SIO1/UART1 transmit ADC/T6/T7 Port 0/T4/T5/PWM0, PWM1 Interrupt Source • Priority Level: X > H > L • Of interrupts of the same level, the one with the smallest vector address takes precedence. Subroutine Stack Levels: 512 levels (the stack is allocated in RAM.) High-speed Multiplication/Division Instructions • 16-bits×8-bits (5 tCYC execution time) • 24-bits×16-bits (12 tCYC execution time) • 16-bits÷8-bits (8 tCYC execution time) • 24-bits÷16-bits (12 tCYC execution time) Oscillation Circuits • RC oscillation circuit (internal): • CF oscillation circuit: • Crystal oscillation circuit: • Frequency variable RC oscillation circuit (internal): For system clock For system clock, with internal Rf For low-speed system clock, with internal Rf For system clock System Clock Divider Function • Can run on low current. • The minimum instruction cycle selectable from 300ns, 600ns, 1.2µs, 2.4µs, 4.8µs, 9.6µs, 19.2µs, 38.4µs, and 76.8µs (at a main clock rate of 10MHz). No.8299-3/23 LC875G32A/24A/16A/08A Standby Function • HALT mode: Halts instruction execution while allowing the peripheral circuits to continue operation. 1) Oscillation is not halted automatically. 2) Canceled by a system reset or occurrence of an interrupt. • HOLD mode : Suspends instruction execution and the operation of the peripheral circuits. 1) The CF, RC, and crystal oscillators automatically stop operation. 2) There are three ways of resetting the HOLD mode. (1) Setting the reset pin to the lower level. (2) Setting at least one of the INT0, INT1, INT2, INT4, and INT5 pins to the specified level. (3) Having an interrupt source established at port 0. • X'tal HOLD mode : Suspends instruction execution and the operation of the peripheral circuits except the base timer. 1) The CF and RC oscillators automatically stop operation. 2) The state of crystal oscillation established when the X'tal HOLD mode is entered is retained. 3) There are four ways of resetting the X'tal HOLD mode. (1) Setting the reset pin to the low level. (2) Setting at least one of the INT0, INT1, INT2, INT4, and INT5 pins to the specified level. (3) Having an interrupt source established at port. (4) Having an interrupt source established in the base timer circuit. Package Form • QIP48E(14×14): “Lead-free type” • SQFP48(7×7): “Lead-free type” Development Tools • Evaluation chip: LC87EV690 • Emulator: EVA62S+ECB876600D+SUB875G00+POD48QFP ICE-B877300+SUB875G00+POD48QFP • Onchip debugger: TCB87 TypeA+LC87F5G32A TCB87 TypeB+LC87F5G32A Flash ROM Version • LC87F5G32A No.8299-4/23 LC875G32A/24A/16A/08A Package Dimensions unit : mm (typ) 3156A 17.2 0.8 14.0 36 37 25 24 7.0 9.0 Package Dimensions unit : mm (typ) 3163B 9.0 7.0 36 37 25 24 14.0 17.2 48 13 1 0.5 12 0.18 0.15 48 1 1.0 (1.5) 0.35 12 13 (0.75) 0.15 1.7max (1.5) (2.7) 3.0max 0.1 SANYO : SQFP48(7X7) 0.1 SANYO : QIP48E(14X14) Pin Assignment P27/INT5/T1IN P26/INT5/T1IN P25/INT5/T1IN P24/INT5/T1IN P23/INT4/T1IN P22/INT4/T1IN P21/URX/INT4/T1IN P20/UTX/INT4/T1IN P07/T7O/AN7 P06/T6O/AN6 P05/CKO/AN5 P04/AN4 P36 P35 VDD3 VSS3 P34 P33 P32 P31 P30 P70/INT0/T0LCP/AN8 P71/INT1/T0HCP/AN9 P72/INT2/T0IN 37 38 39 40 41 42 43 44 45 46 47 48 36 35 34 33 32 31 30 29 28 27 26 25 LC875G32A LC875G24A LC875G16A LC875G08A 24 23 22 21 20 19 18 17 16 15 14 13 P03/AN3 P02/AN2 P01/AN1 P00/AN0 VSS2 VDD2 PWM0 PWM1 P17/T1PWMH/BUZ P16/T1PWML P15/SCK1 P14/SI1/SB1 P73/INT3/T0IN RES XT1/AN10 XT2/AN11 VSS1 CF1 CF2 VDD1 P10/SO0 P11/SI0/SB0 P12/SCK0 P13/SO1 1 2 3 4 5 6 7 8 9 10 11 12 Top view SANYO: QIP48E(14×14) "Lead-free Type" SANYO: SQFP48(7×7) "Lead-free Type" No.8299-5/23 0.5 LC875G32A/24A/16A/08A SQFP/QIP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 NAME P73/INT3/T0IN RES XT1/AN10 XT2/AN11 VSS1 CF1 CF2 VDD1 P10/SO0 P11/SI0/SB0 P12/SCK0 P13/SO1 P14/SI1/SB1 P15/SCK1 P16/T1PWML P17/T1PWMH/BUZ PWM1 PWM0 VDD2 VSS2 P00/AN0 P01/AN1 P02/AN2 P03/AN3 SQFP/QIP 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 NAME P04/AN4 P05/CKO/AN5 P06/T6O/AN6 P07/T7O/AN7 P20/UTX/INT4/T1IN P21/URX/INT4/T1IN P22/INT4/T1IN P23/INT4/T1IN P24/INT5/T1IN P25/INT5/T1IN P26/INT5/T1IN P27/INT5/T1IN P36 P35 VDD3 VSS3 P34 P33 P32 P31 P30 P70/INT0/T0LCP/AN8 P71/INT1/T0HCP/AN9 P72/INT2/T0IN No.8299-6/23 LC875G32A/24A/16A/08A System Block Diagram Interrupt control IR PLA Standby control ROM CF RC X’tal MRC Clock generator PC SIO0 Bus interface ACC SIO1 Port 0 B register Timer 0 Port 1 C register Timer 1 Port 3 ALU Timer 4 Port 7 Timer 5 ADC PSW Timer 6 INT0-2, INT4,5 INT3(Noise filter) RAR Timer 7 Port 2 RAM Base timer UART1 Stack pointer PWM0 Watchdog timer PWM1 No.8299-7/23 LC875G32A/24A/16A/08A Pin Description Pin Name VSS1 VSS2 VSS3 VDD1 VDD2 VDD3 Port 0 P00 to P07 I/O • 8-bit I/O port • I/O specifiable in 4-bit units • Pull-up resistors can be turned on and off in 4-bit units • HOLD reset input • Port 0 interrupt input • Shared pins P05: System clock output P06: Timer 6 toggle output P07: Timer 7 toggle output AD converter input port: AN0 (P00) to AN7 (P07) Port 1 P10 to P17 I/O • 8-bit I/O port • I/O specifiable in 1-bit units • Pull-up resistors can be turned on and off in 1-bit units • Pin functions P10: SIO0 data output P11: SIO0 data input/bus I/O P12: SIO0 clock I/O P13: SIO1 data output P14: SIO1 data input/bus I/O P15: SIO1 clock I/O P16: Timer 1PWML output P17: Timer 1PWMH output/beeper output Port 2 P20 to P27 I/O • 8-bit I/O port • I/O specifiable in 1-bit units • Pull-up resistors can be turned on and off in 1-bit units • Pin functions P20: UART transmit P21: UART receive P20 to P23: INT4 input/HOLD reset input/timer 1 event input/ timer 0L capture input/timer 0H capture input P24 to P27: INT5 input/HOLD reset input/timer 1 event input/ timer 0L capture input/timer 0H capture input Interrupt acknowledge type Rising INT4 INT5 enable enable Falling enable enable Rising & Falling enable enable H level disable disable L level disable disable Yes Yes Yes + Power supply pin No I/O - Power supply pin Description Option No Continued on next page. No.8299-8/23 LC875G32A/24A/16A/08A Continued from preceding page. Pin Name Port 3 P30 to P36 Port 7 P70 to P73 I/O I/O I/O • 7-bit I/O port • I/O specifiable in 1-bit units • Pull-up resistors can be turned on and off in 1-bit units • 4-bit I/O port • I/O specifiable in 1-bit units • Pull-up resistors can be turned on and off in 1-bit units • Shared pins AD converter input port : AN8 (P70), AN9 (P71) P70: INT0 input/HOLD reset input/timer 0L capture input/watchdog timer output P71: INT1 input/HOLD reset input/timer 0H capture input P72: INT2 input/HOLD reset input/timer 0 event input/timer 0L capture input P73: INT3 input (with noise filter)/timer 0 event input/timer 0H capture input Interrupt acknowledge type Rising INT0 INT1 INT2 INT3 enable enable enable enable Falling enable enable enable enable Rising & Falling disable disable enable enable H level enable enable disable disable L level enable enable disable disable No Description Option Yes PWM0, PWM1 RES XT1 I/O Input Input • PWM0 and PWM1 output ports • General-purpose I/O available Reset pin • 32.768kHz crystal oscillator input pin • Shared pins General-purpose input port AD converter input port: AN10 Must be connected to VDD1 if not to be used No No No XT2 I/O • 32.768kHz crystal oscillator output pin • Shared pins General-purpose I/O port AD converter input port: AN11 Must be set for oscillation and kept open if not to be used No CF1 CF2 Input Output Ceramic resonator input pin Ceramic resonator output pin No No No.8299-9/23 LC875G32A/24A/16A/08A Port Output Types The table below lists the types of port outputs and the presence/absence of a pull-up resistor. Data can be read into any input port even if it is in the output mode. Port Name P00 to P07 Option Selected in Units of 1-bit Option Type 1 2 P10 to P17 1-bit 1 2 P20 to P27 1-bit 1 2 P30 to P36 1-bit 1 2 P70 P71 to P73 PWM0, PWM1 XT1 XT2 No No No No No CMOS Nch-open drain CMOS Nch-open drain CMOS Nch-open drain CMOS Nch-open drain Nch-open drain CMOS CMOS Output for 32.768kHz crystal oscillator (Input only) Input for 32.768kHz crystal oscillator (Nch-open drain when in general-purpose output mode) No Output Type Pull-up Resistor Programmable (Note 1) No Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable No No Note 1: Programmable pull-up resistor of Port 0 is specified in nibble units (P00 to P03, P04 to P07). Note: To reduce VDD signal noise and to increase the duration of the backup battery supply, VSS1, VSS2, and VSS3 should connect to each other and they should also be grounded. Example 1: During backup in hold mode, port output ‘H’ level is supplied from the back-up capacitor. Back-up capacitor Power Supply LSI VDD1 VDD2 VDD3 VSS1 VSS2 VSS3 Example 2: During backup in hold mode, output is not held high and its value in unsettled. Back-up capacitor Power Supply LSI VDD1 VDD2 VDD3 VSS1 VSS2 VSS3 No.8299-10/23 LC875G32A/24A/16A/08A Absolute Maximum Ratings at Ta = 25°C, VSS1 = VSS2 = VSS3 = 0V Parameter Maximum supply voltage Input voltage Input/output voltage Peak output current IOPH(2) IOPH(3) Mean output High level output current current (Note 1-1) IOMH(2) IOMH(3) Total output current ΣIOAH(1) ΣIOAH(2) ΣIOAH(3) ΣIOAH(4) ΣIOAH(5) ΣIOAH(6) ΣIOAH(7) Peak output current IOPL(2) IOPL(3) Mean output current Low level output current (Note 1-1) IOML(2) IOML(3) Total output current ΣIOAL(1) ΣIOAL(2) ΣIOAL(3) ΣIOAL(4) ΣIOAL(5) ΣIOAL(6) ΣIOAL(7) Power dissipation Pd max IOML(1) IOPL(1) PWM0, PWM1 Ports P71 to P73 Ports P71 to P73 Port 0 Port 1, PWM0, PWM1 Ports 0, 1 PWM0, PWM1 Ports 2, P35, P36 Ports P30 to P34 Ports 2, 3 Ports P02 to P07 Ports 1, 2, 3 PWM0, PWM1 Ports P00, P01 Port 7, XT2 Ports P02 to P07 Ports 1, 2, 3 PWM0, PWM1 Ports P00, P01 Port 7, XT2 Port 7, XT2 Port 0 Port 1, PWM0, PWM1 Ports 0, 1 PWM0, PWM1 Ports 2, P35, P36 Ports P30 to P34 Ports 2, 3 SQFP48(7×7) QIP48E(14×14) Operating ambient temperature Storage ambient temperature Tstg Topr -30 -55 Total of all applicable pins Total of all applicable pins Total of all applicable pins Ta= -30 to +70°C Total of all applicable pins Per 1 applicable pin Per 1 applicable pin Total of all applicable pins Total of all applicable pins Total of all applicable pins 20 7.5 15 45 45 80 45 45 60 190 390 +70 °C +125 mW Per 1 applicable pin Per 1 applicable pin Per 1 applicable pin 15 30 10 Total of all applicable pins Total of all applicable pins Total of all applicable pins Per 1 applicable pin 20 Total of all applicable pins IOMH(1) PWM0, PWM1 Ports P71 to P73 Ports 0, 1, 2, 3 IOPH(1) VI VIO Symbol VDD max Pin/Remarks VDD1, VDD2, VDD3 XT1, CF1 Ports 0, 1, 2, Port 3, 7, PWM0, PWM1, XT2 Ports 0, 1, 2, 3 CMOS output select Per 1 applicable pin CMOS output select Per 1 applicable pin Per 1 applicable pin CMOS output select Per 1 applicable pin CMOS output select Per 1 applicable pin Per 1 applicable pin Total of all applicable pins Total of all applicable pins Total of all applicable pins -10 -20 -5 -7.5 -15 -3 -10 -25 -25 -45 -25 -25 -45 mA -0.3 VDD+0.3 Conditions VDD[V] VDD1=VDD2=VDD3 min -0.3 -0.3 Specification typ max +6.5 VDD+0.3 V unit Note 1-1: The mean output current is a mean value measured over 100ms. No.8299-11/23 LC875G32A/24A/16A/08A Allowable Operating Conditions at Ta = -30°C to +70°C, VSS1 = VSS2 = VSS3 = 0V Parameter Operating supply voltage Symbol VDD(1) VDD(2) VDD(3) Memory sustaining supply voltage High level input voltage VIH(1) Ports 1, 2, 3 P71 to P73 P70 port input/ interrupt side PWM0, PWM1 VIH(2) VIH(3) VIH(4) Low level input voltage VIL(1) Port 0 Port 70 watchdog timer side XT1, XT2, CF1, RES Ports 1, 2, 3 P71 to P73 P70 port input/ interrupt side PWM0, PWM1 VIL(2) Port 0 4.0 to 5.5 2.5 to 4.0 VIL(3) VIL(4) Instruction cycle time tCYC (Note 2-1) Port 70 watchdog timer side XT1, XT2, CF1, RES 2.5 to 5.5 2.5 to 5.5 4.0 to 5.5 3.0 to 5.5 2.5 to 5.5 External system clock frequency FEXCF CF1 • CF2 pin open • System clock frequency division ratio=1/1 • External system clock duty =50±5% • CF2 pin open • System clock frequency division ratio=1/2 Oscillation frequency range (Note 2-2) FmCF(3) FmRC FmMRC FsX’tal XT1, XT2 CF1, CF2 FmCF(2) CF1, CF2 FmCF(1) CF1, CF2 10MHz ceramic oscillation See Fig 1. 8MHz ceramic oscillation See Fig 1. 5MHz ceramic oscillation See Fig 1. Internal RC oscillation Frequency variable RC oscillation source oscillation 32.768kHz crystal oscillation See Fig 2. 2.5 to 5.5 4.0 to 5.5 3.0 to 5.5 2.5 to 5.5 2.5 to 5.5 2.5 to 5.5 2.5 to 5.5 0.3 0.2 10 8 5 1.0 16 32.768 kHz 2.0 10 MHz 2.5 to 5.5 4.5 to 5.5 0.1 0.2 5 20.4 4.5 to 5.5 0.1 10 2.5 to 4.0 VSS VSS VSS VSS VSS 0.294 0.367 0.588 0.2VDD 0.15VDD +0.4 0.2VDD 0.8VDD -1.0 0.25VDD 200 200 200 µs 4.0 to 5.5 VSS 2.5 to 5.5 2.5 to 5.5 2.5 to 5.5 0.3VDD +0.7 0.9VDD 0.75VDD VDD VDD VDD 0.1VDD +0.4 2.5 to 5.5 0.3VDD +0.7 VDD VHD VDD1=VDD2=VDD3 Pin/Remarks VDD1=VDD2=VDD3 Conditions VDD[V] 0.294µs ≤ tCYC ≤ 200µs 0.367µs ≤ tCYC ≤ 200µs 0.588µs ≤ tCYC ≤ 200µs RAM and register contents sustained in HOLD mode. 2.0 5.5 min 4.0 3.0 2.5 Specification typ max 5.5 5.5 5.5 unit V Note 2-1: Relationship between tCYC and oscillation frequency is 3/FmCF at a division ratio of 1/1 and 6/FmCF at a division ratio of 1/2. Note 2-2: See Tables 1 and 2 for the oscillation constants. No.8299-12/23 LC875G32A/24A/16A/08A Electrical Characteristics at Ta = -30°C to +70°C, VSS1 = VSS2 = VSS3 = 0V Parameter High level input current Symbol IIH(1) Pin/Remarks Ports 0, 1, 2, 3 Port 7 RES PWM0, PWM1 IIH(2) IIH(3) Low level input current IIL(1) XT1, XT2 Conditions VDD[V] Output disabled Pull-up resistor off VIN=VDD (Including output Tr's off leakage current) For input port specification VIN=VDD CF1 Ports 0, 1, 2, 3 Port 7 RES PWM0, PWM1 IIL(2) IIL(3) High level output voltage VOH(1) VOH(2) VOH(3) VOH(4) VOH(5) VOH(6) Low level output voltage VOL(1) VOL(2) VOL(3) VOL(4) VOL(5) Pull-up resistance Rpu(1) Rpu(2) Hysteresis voltage Pin capacitance VHYS CP P71 to P73 PWM0, PWM1, P05 (System clock output function used) Ports 0, 1, 2, 3 PWM0, PWM1, XT2 P00, P01 Port 7 Ports 0, 1, 2, 3 Port 7 Ports 0, 1, 2, 3 Port 7 RES Ports 1, 2, 7 All pins For pins other than that under test: VIN=VSS f=1MHz Ta=25°C 2.5 to 5.5 10 pF VOH=0.9VDD XT1, XT2 VIN=VDD Output disabled Pull-up resistor off VIN=VSS (Including output Tr's off leakage current) For input port specification VIN=VSS CF1 Ports 0, 1, 2, 3 VIN=VSS IOH= -1mA IOH= -0.1mA IOH= -0.4mA IOH= -6mA IOH= -1.6mA IOH= -1mA IOL=10mA IOL=1.6mA IOL=1mA IOL=30mA IOL=1mA VOH=0.9VDD 2.5 to 5.5 2.5 to 5.5 4.5 to 5.5 2.5 to 5.5 4.5 to 5.5 4.5 to 5.5 4.5 to 5.5 2.5 to 5.5 4.5 to 5.5 4.5 to 5.5 2.5 to 5.5 4.5 to 5.5 2.5 to 5.5 4.5 to 5.5 2.5 to 4.5 2.5 to 5.5 15 18 35 50 0.1VDD -1 -15 VDD-1 VDD-0.5 VDD-1 VDD-1 VDD-0.4 VDD-0.4 1.5 0.4 0.4 1.5 0.4 80 kΩ 150 V V 2.5 to 5.5 -1 2.5 to 5.5 2.5 to 5.5 1 15 µA 2.5 to 5.5 1 min Specification typ max unit No.8299-13/23 LC875G32A/24A/16A/08A Serial Input/Output Characteristics at Ta = -30°C to +70°C, VSS1 = VSS2 = VSS3 = 0V 1. SIO0 Serial I/O Characteristics (Note 4-1-1) Parameter Frequency Low level Input clock pulse width High level pulse width tSCKH(1) tSCKHA(1) • Continuous data transmission/reception mode Serial clock • See Fig. 6. • (Note 4-1-2) Frequency Low level Output clock pulse width High level pulse width tSCKHA(2) • Continuous data transmission/reception mode • CMOS output selected • See Fig. 6. Data setup time Serial input tsDI(1) SB0(P11), SI0(P11) Data hold time thDI(1) • Must be specified with respect to rising edge of SIOCLK. • See Fig. 6. 2.5 to 5.5 Output delay Input clock time tdD0(2) tdD0(1) SO0(P10), SB0(P11) • Continuous data transmission/reception mode • (Note 4-1-3) • Synchronous 8-bit mode • (Note 4-1-3) tdD0(3) (Note 4-1-3) 2.5 to 5.5 (1/3)tCYC +0.05 2.5 to 5.5 2.5 to 5.5 0.03 2.5 to 5.5 0.03 tSCKH(2) +2tCYC tSCKH(2) 2.5 to 5.5 tSCK(2) tSCKL(2) SCK0(P12) • CMOS output selected • See Fig. 6. 4/3 1/2 tSCK 1/2 tSCKH(2) +(10/3) tCYC tCYC 4 2.5 to 5.5 Symbol tSCK(1) tSCKL(1) Pin/Remarks SCK0(P12) Conditions VDD[V] See Fig. 6. min 2 1 1 tCYC Specification typ max unit (1/3)tCYC +0.05 1tCYC +0.05 µs Serial output Note 4-1-1: These specifications are theoretical values. Add margin depending on its use. Note 4-1-2: To use serial-clock-input in continuous trans/rec mode, a time from SI0RUN being set when serial clock is "H" to the first negative edge of the serial clock must be longer than tSCKHA. Note 4-1-3: Must be specified with respect to falling edge of SIOCLK. Must be specified as the time to the beginning of output state change in open drain output mode. See Fig. 6. Output clock No.8299-14/23 LC875G32A/24A/16A/08A 2. SIO1 Serial I/O Characteristics (Note 4-2-1) Parameter Frequency Input clock Low level pulse width High level pulse width Frequency Output clock Low level pulse width High level pulse width Data setup time Serial input tsDI(2) SB1(P14), SI1(P14) Data hold time thDI(2) • Must be specified with respect to rising edge of SIOCLK. • See Fig. 6. 2.5 to 5.5 Output delay time Serial output tdD0(4) SO1(P13), SB1(P14) • Must be specified with respect to falling edge of SIOCLK. • Must be specified as the time to the beginning of output state change in open drain output mode. • See Fig. 6. 2.5 to 5.5 (1/3)tCYC +0.05 0.03 2.5 to 5.5 0.03 tSCKH(4) tSCK(4) tSCKL(4) SCK1(P15) • CMOS output selected • See Fig. 6. 2.5 to 5.5 tSCKH(3) Symbol tSCK(3) tSCKL(3) Pin/Remarks SCK1(P15) Conditions VDD[V] See Fig. 6. min 2 2.5 to 5.5 1 tCYC 1 2 1/2 tSCK 1/2 Specification typ max unit Serial clock µs Note 4-2-1: These specifications are theoretical values. Add margin depending on its use. No.8299-15/23 LC875G32A/24A/16A/08A Pulse Input Conditions at Ta = -30°C to +70°C, VSS1 = VSS2 = VSS3 = 0V Parameter High/low level pulse width Symbol tPIH(1) tPIL(1) Pin/Remarks INT0(P70), INT1(P71), INT2(P72), INT4(P20 to P23), INT5(P24 to P27) tPIH(2) tPIL(2) tPIH(3) tPIL(3) tPIH(4) tPIL(4) tPIL(5) INT3(P73) when noise filter time constant is 1/1 INT3(P73) when noise filter time constant is 1/32 INT3(P73) when noise filter time constant is 1/128 RES • Interrupt source flag can be set. • Event inputs for timer 0 are enabled. • Interrupt source flag can be set. • Event inputs for timer 0 are enabled. • Interrupt source flag can be set. • Event inputs for timer 0 are enabled. Resetting is enabled. 2.5 to 5.5 200 µs 2.5 to 5.5 256 2.5 to 5.5 64 2.5 to 5.5 2 tCYC Conditions VDD[V] • Interrupt source flag can be set. • Event inputs for timer 0 or 1 are enabled. 2.5 to 5.5 1 min Specification typ max unit AD Converter Characteristics at VSS1 = VSS2 = VSS3 = 0V Parameter Resolution Absolute accuracy Conversion time Symbol N ET TCAD Pin/Remarks AN0(P00) to AN7(P07) AN8(P70) AN9(P71) AN10(XT1) Analog input voltage range Analog port input current IAINH IAINL VAIN=VDD VAIN=VSS VAIN AN11(XT2) 4.75 to 5.25 4.75 to 5.25 4.75 to 5.25 -1 VSS VDD 1 V µA (Note 6-1) See conversion time calculation formulas. (Note 6-2) 4.75 to 5.25 38.5 90 µs Conditions VDD[V] 4.75 to 5.25 4.75 to 5.25 min Specification typ 12 T.B.D max unit bit LSB Parameter Resolution Absolute accuracy Conversion time Symbol N ET TCAD Pin/Remarks AN0(P00) to AN7(P07) AN8(P70) AN9(P71) AN10(XT1) Analog input voltage range Analog port input current IAINH IAINL VAIN=VDD VAIN=VSS VAIN AN11(XT2) (Note 6-1) See conversion time calculation formulas. (Note 6-2) 3.0 to 5.5 3.0 to 5.5 3.0 to 5.5 3.0 to 5.5 -1 45 VSS 90 VDD 1 Conditions VDD[V] 3.0 to 5.5 3.0 to 5.5 4.5 to 5.5 22.5 min Specification typ 8 ±1.5 90 µs max unit bit LSB V µA Conversion time calculation formulas: 12-bits AD Converter Mode: TCAD (Conversion time) = ((52/(division ratio))+2) × (1/3) × tCYC 8-bits AD Converter Mode: TCAD (Conversion time) = ((32/(division ratio))+2) × (1/3) × tCYC Note 6-1: The quantization error (±1/2LSB) must be excluded from the absolute accuracy. The absolute accuracy must be measured in the microcontroller's state in which no I/O operations occur at the pins adjacent to the analog input channel. Note 6-2: The conversion time refers to the period from the time an instruction for starting a conversion process till the time the conversion results register(s) are loaded with a complete digital conversion value corresponding to the analog input value. The conversion time is 2 times the normal-time conversion time when : • The first AD conversion is performed in the 12-bit AD conversion mode after a system reset. • The first AD conversion is performed after the AD conversion mode is switched from 8-bit to 12-bit conversion mode. No.8299-16/23 LC875G32A/24A/16A/08A Consumption Current Characteristics at Ta = -30°C to +70°C, VSS1 = VSS2 = VSS3 = 0V Parameter Normal mode consumption current (Note 7-1) Symbol IDDOP(1) Pin/Remarks VDD1 =VDD2 =VDD3 Conditions VDD[V] • FmCF=10MHz ceramic oscillation mode • FsX’tal=32.768kHz crystal oscillation mode • System clock set to 10MHz side • Internal RC oscillation stopped • Frequency variable RC oscillation stopped • 1/1 frequency division ratio IDDOP(2) • CF1=20MHz external clock • FsX’tal=32.768kHz crystal oscillation mode • System clock set to CF1 side • Internal RC oscillation stopped • Frequency variable RC oscillation stopped • 1/2 frequency division ratio IDDOP(3) • FmCF=5MHz ceramic oscillation mode • FsX’tal=32.768kHz crystal oscillation mode • System clock set to 5MHz side IDDOP(4) • Internal RC oscillation stopped • Frequency variable RC oscillation stopped • 1/1 frequency division ratio IDDOP(5) • FmCF=0Hz (oscillation stopped) • FsX’tal=32.768kHz crystal oscillation mode • System clock set to internal RC IDDOP(6) oscillation • Frequency variable RC oscillation stopped • 1/2 frequency division ratio IDDOP(7) • FmCF=0Hz (oscillation stopped) • FsX’tal=32.768kHz crystal oscillation mode • Internal RC oscillation stopped IDDOP(8) • System clock set to 1MHz with frequency variable RC oscillation • 1/2 frequency division ratio IDDOP(9) • FmCF=0Hz (oscillation stopped) • FsX’tal=32.768kHz crystal oscillation mode • System clock set to 32.768kHz side IDDOP(10) • Internal RC oscillation stopped • Frequency variable RC oscillation stopped • 1/2 frequency division ratio 2.5 to 4.5 11 65 4.5 to 5.5 26 85 µA 2.5 to 4.5 0.7 3.2 4.5 to 5.5 1.3 4.2 2.5 to 4.5 0.3 1.4 4.5 to 5.5 0.6 1.9 2.5 to 4.5 1.9 5.2 4.5 to 5.5 3.7 6.8 mA 4.0 to 5.5 8 15 4.0 to 5.5 7 12.5 min Specification typ max unit Note 7-1: The consumption current value includes none of the currents that flow into the output Tr and internal pull-up resistors. Continued on next page. No.8299-17/23 LC875G32A/24A/16A/08A Continued from preceding page. Parameter HALT mode consumption current (Note 7-1) Symbol IDDHALT(1) Pin/ Remarks VDD1 =VDD2 =VDD3 • HALT mode • FmCF=10MHz ceramic oscillation mode • FsX’tal=32.768kHz crystal oscillation mode • System clock set to 10MHz side • Internal RC oscillation stopped • Frequency variable RC oscillation stopped • 1/1 frequency division ratio IDDHALT(2) • HALT mode • CF1=20MHz external clock • FsX’tal=32.768kHz crystal oscillation mode • System clock set to CF1 side • Internal RC oscillation stopped • Frequency variable RC oscillation stopped • 1/2 frequency division ratio IDDHALT(3) • HALT mode • FmCF=5MHz ceramic oscillation mode • FsX’tal=32.768kHz crystal oscillation mode • System clock set to 5MHz side IDDHALT(4) • Internal RC oscillation stopped • Frequency variable RC oscillation stopped • 1/1 frequency division ratio IDDHALT(5) • HALT mode • FmCF=0Hz (oscillation stopped) • FsX’tal=32.768kHz crystal oscillation mode IDDHALT(6) • System clock set to internal RC oscillation • Frequency variable RC oscillation stopped • 1/2 frequency division ratio IDDHALT(7) • HALT mode • FmCF=0Hz (oscillation stopped) • FsX’tal=32.768kHz crystal oscillation mode • Internal RC oscillation stopped IDDHALT(8) • System clock set to 1MHz with frequency variable RC oscillation • 1/2 frequency division ratio IDDHALT(9) • HALT mode • FmCF=0Hz (oscillation stopped) • FsX’tal=32.768kHz crystal oscillation mode • System clock set to 32.768kHz side IDDHALT(10) • Internal RC oscillation stopped • Frequency variable RC oscillation stopped • 1/2 frequency division ratio HOLD mode consumption current Timer HOLD mode consumption current IDDHOLD(4) IDDHOLD(1) IDDHOLD(2) IDDHOLD(3) VDD1 VDD1 HOLD mode • CF1=VDD or open (External clock mode) Timer HOLD mode • CF1=VDD or open (External clock mode) • FsX’tal=32.768kHz crystal oscillation mode 2.5 to 4.5 4.5 to 5.5 2.5 to 4.5 0.01 16 10 12 55 36 4.5 to 5.5 0.015 17 2.5 to 4.5 7 40 µA 4.5 to 5.5 18 60 2.5 to 4.5 0.6 2.7 4.5 to 5.5 1.1 3.6 2.5 to 4.5 0.15 0.8 4.5 to 5.5 0.3 1.1 2.5 to 4.5 0.7 2.2 4.5 to 5.5 1.5 3.1 mA 4.0 to 5.5 3.4 7.7 4.0 to 5.5 2.4 4.9 Conditions VDD[V] min Specification typ max unit Note 7-1: The consumption current value includes none of the currents that flow into the output Tr and internal pull-up resistors. No.8299-18/23 LC875G32A/24A/16A/08A UART (Full duplex) Operating Conditions at Ta = -30°C to +70°C, VSS1 = VSS2 = VSS3 = 0V Parameter Transfer rate Symbol UBR Pin/Remarks P20, P21 Conditions VDD[V] 2.5 to 5.5 min 16/3 Specification typ max 8192/3 unit tCYC Data length: 7, 8, and 9 bits (LSB first) Stop bits: 1-bit (2-bit in continuous data transmission) Parity bits: None Example of Continuous 8-bit Data Transmission Mode Processing (first transmit data=55H) Start bit Start of transmission Stop bit Transmit data (LSB first) End of transmission UBR Example of Continuous 8-bit Data Reception Mode Processing (first receive data=55H) Stop bit Receive data (LSB first) End of reception Start bit Start of reception UBR No.8299-19/23 LC875G32A/24A/16A/08A Characteristics of a Sample Main System Clock Oscillation Circuit Given below are the characteristics of a sample main system clock oscillation circuit that are measured using a SANYO-designated oscillation characteristics evaluation board and external components with circuit constant values with which the oscillator vendor confirmed normal and stable oscillation. Table 1 Characteristics of a Sample Main System Clock Oscillator Circuit with a Ceramic Oscillator Nominal Frequency Circuit Constant Vendor Name Oscillator Name C1 [pF] 10MHz MURATA CSTCE10M0G52-R0 CSTCE10M0G52-B0 8MHz MURATA CSTCE8M00G52-R0 CSTCE8M00G52-B0 5MHz MURATA CSTCR5M00G53-R0 CSTCR5M00G53-B0 (10) (10) (10) (10) (15) (15) C2 [pF] (10) (10) (10) (10) (15) (15) Rf [Ω] Open Open Open Open Open Open Rd1 [Ω] 680 680 1.0k 1.0k 2.2k 2.2k Operating Voltage Range [V] 4.0 to 5.5 4.0 to 5.5 3.0 to 5.5 3.0 to 5.5 2.5 to 5.5 2.5 to 5.5 typ [ms] 0.1 0.1 0.1 0.1 0.2 0.2 Oscillation Stabilization Time max [ms] 0.5 0.5 0.5 0.5 0.6 0.6 Internal C1, C2 (SMD type) Internal C1, C2 (SMD type) Internal C1, C2 (SMD type) Remarks The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized after VDD goes above the operating voltage lower limit (see Figure 4). It is recommended to insert feedback resister (Rf: 1MΩ) when power supply voltage is used around 2.5V. Characteristics of a Sample Subsystem Clock Oscillator Circuit Given below are the characteristics of a sample subsystem clock oscillation circuit that are measured using a SANYOdesignated oscillation characteristics evaluation board and external components with circuit constant values with which the oscillator vendor confirmed normal and stable oscillation. Table 2 Characteristics of a Sample Subsystem Clock Oscillator Circuit with a Crystal Oscillator Nominal Frequency Circuit Constant Vendor Name Oscillator Name C3 [pF] 32.768kHz EPSON TOYOCOM MC-306 18 C4 [pF] 18 Rf [Ω] Open Rd2 [Ω] 510k Operating Voltage Range [V] 2.5 to 5.5 typ [s] 1.1 Oscillation Stabilization Time max [s] 3.0 Applicable CL value=12.5pF Remarks The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized after the instruction for starting the subclock oscillation circuit is executed and to the time interval that is required for the oscillation to get stabilized after the HOLD mode is reset (see Figure 4). Note: The components that are involved in oscillation should be placed as close to the IC and to one another as possible because they are vulnerable to the influences of the circuit pattern. CF1 CF2 XT1 XT2 Rf Rf Rd1 C3 X’tal Rd2 C1 CF C2 C4 Figure 1 CF Oscillator Circuit Figure 2 XT Oscillator Circuit 0.5VDD Figure 3 AC Timing Measurement Point No.8299-20/23 LC875G32A/24A/16A/08A Power Supply VDD Operating VDD lower limit 0V Reset time RES Internal RC oscillation tmsCF CF1, CF2 tmsX’tal XT1, XT2 Operating mode Unpredictable Reset Instruction execution Reset Time and Oscillation Stabilization Time HOLD reset signal HOLD reset signal absent HOLD release signal VALID Internal RC oscillation tmsCF CF1, CF2 tmsX’tal XT1, XT2 State HOLD HALT HOLD Reset Signal and Oscillation Stabilization Time Figure 4 Oscillation Stabilization Times No.8299-21/23 LC875G32A/24A/16A/08A VDD RRES RES CRES (Note) Determine the value of CRES and RRES so that the reset signal is present for a period of 200µs after the supply voltage goes beyond the lower limit of the IC's operating voltage. Figure 5 Reset Circuit SIOCLK : DATAIN : DI0 DI1 DI2 DI3 DI4 DI5 DI6 DI7 DI8 DATAOUT : DO0 DO1 DO2 DO3 DO4 DO5 DO6 DO7 Data RAM transfer period (SIO0 only) DO8 tSCK tSCKL SIOCLK : tsDI DATAIN : tdDO DATAOUT : Data RAM transfer period (SIO0 only) tSCKL SIOCLK : tsDI DATAIN : tdDO DATAOUT : thDI tSCKHA thDI tSCKH Figure 6 Serial I/O Output Waveforms tPIL tPIH Figure 7 Pulse Input Timing Signal Waveform No.8299-22/23 LC875G32A/24A/16A/08A SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein. SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO Semiconductor Co.,Ltd. products described or contained herein are controlled under any of applicable local export control laws and regulations, such products may require the export license from the authorities concerned in accordance with the above law. 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SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's intellctual property rights which has resulted from the use of the technical information and products mentioned above. This catalog provides information as of January, 2007. Specifications and information herein are subject to change without notice. PS No.8299-23/23