LC877G16A

Ordering number : ENA2006 LC877G16A Overview CMOS IC 16K-byte ROM and 512-byte RAM 8-bit 1-chip Microcontroller The LC877G16A is an 8-bit microcontroller that, centered around a CPU running at a minimum bus cycle time of 200ns, integrates on a single chip a number of hardware features such as 16K-byte ROM, 512-byte RAM, an LCD controller/driver, a sophisticated 16-bit timer/counter (may be divided into 8-bit timers), two 8-bit timers with a prescaler, a 16-bit timer with a prescaler (may be divided into 8-bit timers), a UART interface (full duplex), infrared remote control receive function, and general-purpose I/O circuits. Features ROM • 16384 × 8 bits RAM • 512 × 9 bits Minimum Bus Cycle Time • 200ns (5MHz) VDD=2.7 to 5.5V Note: The bus cycle time here refers to ROM read speed. Minimum Instruction Cycle Time (tCYC) • 600ns (5MHz) VDD=2.7 to 5.5V Operating Temperature Range • -40°C to +85°C Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment. The products mentioned herein shall not be intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee thereof. If you should intend to use our products for new introduction or other application different from current conditions on the usage of automotive device, communication device, office equipment, industrial equipment etc. , please consult with us about usage condition (temperature, operation time etc.) prior to the intended use. If there is no consultation or inquiry before the intended use, our customer shall be solely responsible for the use. Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer ' s products or equipment. Ver.1.00 30712HKIM 20120119-S00007 No.A2006-1/17 LC877G16A Ports • Normal withstand voltage I/O ports Ports whose I/O direction can be designated in 1-bit units: • Normal withstand voltage input port • LCD ports Segment output: Common output: Bias power supply for LCD driving: Multiplexed pin functions Input/output ports: • Dedicated oscillator ports • Reset pin • Power pins LCD Controller (1) Display duty: 1/3duty, 1/4duty (2) Display bias: 1/2bias, 1/3bias UART • Full duplex • 7/8/9 bits data bit selectable • 1 stop bit (2-bit in continuous data transmission) • Built-in baudrate generator • Maximum transfer rate: 200kbps (5MHz) Timers • Timer 0: 16-bit timer/counter with a capture register Mode 0: 8-bit timer with an 8-bit programmable prescaler (with an 8-bit capture register) × 2 channels Mode 1: 8-bit timer with an 8-bit programmable prescaler (with an 8-bit capture register) + 8-bit counter (with an 8-bit capture registers) Mode 2: 16-bit timer with an 8-bit programmable prescaler (with a 16-bit capture register) Mode 3: 16-bit counter (with a 16-bit capture register) • Timer 4: 8-bit timer with a 6-bit prescaler • Timer 5: 8-bit timer with a 6-bit prescaler • Timer 8: 16-bit timer Mode 0: 8-bit timer with an 8-bit prescaler × 2 channels Mode 1: 16-bit timer with an 8-bit prescaler • Base Timer 1) The clock can be selected from the system clock and timer 0 prescaler output. 2) An interrupt can be generated at five different time intervals. 13 (2 for UART, 1 for remote control, and 10 for key-scan signal I/O) 1 (XT1) 74 (S00 to S73) 4 (COM0 to COM3) 3 (V1 to V3) 8 (P1n) 2 (CF1, CF2) 1 (RES) 2 (VDD1, VSS1) No.A2006-2/17 LC877G16A Infrared Remote Control Receiver Circuit 1 1) Noise rejection function 2) Supports receive formats with a guide-pulse of half-clock/clock/none. 3) Determines an end of receive by detecting a no-signal period (no carrier). (Supports same receive format with a different bit length.) High-speed Multiplication/Division Instructions • 16 bits × 8 bits (5 tCYC execution time) • 24 bits × 16 bits (12 tCYC execution time) • 16 bits ÷ 8 bits (8 tCYC execution time) • 24 bits ÷ 16 bits (12 tCYC execution time) Interrupts • 14 sources, 8 vectors 1) Provides three levels (low (L), high (H), and highest (X)) of multiplex interrupt control. Any interrupt request of the level equal to or lower than the current interrupt is not accepted. 2) When interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest level takes precedence over the other interrupts. For interrupts of the same level, an interrupt into the smallest vector address is given priority. No. 1 2 3 4 5 6 7 8 9 10 0004BH H or L Port 0/T4/T5 00033H 0003BH H or L H or L UART receive/T8L/T8H UART transmit Vector Address 00003H 0000BH 00013H 0001BH 00023H Level X or L X or L H or L H or L H or L INT0 INT1 T0L/remote control receiver1 INT3/base timer T0H Interrupt Source • Priority levels: X > H > L • When interrupts of the same level occur at the same time, an interrupt with the smallest vector address is given priority. Subroutine Stack Levels • Up to 256 levels mum (stack is allocated in RAM) Oscillator Circuits • RC oscillator circuit (internal): For system clock • CF oscillator circuit: For system clock, with internal Rf, and external Rd  System Clock Divider Function • Can run on low current. • The minimum instruction cycle can be selected from among 600ns, 1.2μs, 2.4μs, 4.8μs, 9.6μs, 19.2μs, 38.4μs, and 76.8μs (at a main clock rate of 5MHz). No.A2006-3/17 LC877G16A Standby Function • HALT mode: HALT mode is used to minimize power dissipation of the IC. Halts instruction execution while allowing the peripheral circuits to continue operation. (Some serial transfer functions are suspended.) 1) Oscillators do not stop automatically. 2) Released by a system reset or occurrence of an interrupt. • HOLD mode: HOLD mode is used to minimize power dissipation of the IC. Suspends instruction execution and operation of the peripheral circuits. 1) The CF and RC oscillators automatically stop operation. 2) There are three ways of releasing HOLD mode. (1) Setting the reset pin to a low level (2) Setting at least one of the INT0, INT1, and INT3 pins to the specified level (3) Establishing an interrupt source at port 0 Package Form • ΤQFP100 (14×14) “Lead-free and halogen-free product” Development Tools • On-chip debugger: TCB87-Type B + LC87D7G16A TCB87-Type C (3-wire cable) + LC87D7G16A No.A2006-4/17 LC877G16A Package Dimensions unit : mm (typ) 3274 16.0 14.0 75 76 51 50 100 1 (1.0) (1.0) 26 0.5 0.2 25 0.125 1.2max 0.1 SANYO : TQFP100(14X14) Pin Assignment S68 S67 S66 S65 S64 S63 S62 S61 S60 S59 S58 S57 S56 S55 S54 S53 S52 S51 S50 S49 S48 S47 S46 S45 S44 S69 S70 S71 S72 S73 COM0 COM1 COM2 COM3 V3 V2 V1 P70/INT0/T0LCP P71/INT1/T0HCP P00 P01 P02 P03 P04 P05 P06 P07 RMIN/P73/INT3/T0IN UTX/P34 URX/P35 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 14.0 16.0 0.5 LC877G16A S43 S42 S41 S40 S39 S38 S37 S36 S35 S34 S33 S32 S31 S30 S29 S28 S27 S26 S25 S24 S23 S22 S21 S20 S19 RES XT1 VSS1 CF1 CF2 VDD1 S0/P10 S1/P11 S2/P12 S3/P13 S4/P14 S5/P15 S6/P16 S7/P17 S8 S9 S10 S11 S12 S13 S14 S15 S16 S17 S18 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Top view SANYO: ΤQFP100 (14×14) “Lead-free and halogen-free product” No.A2006-5/17 LC877G16A PIN No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 NAME RES XT1 VSS1 CF1 CF2 VDD1 S0/P10 S1/P11 S2/P12 S3/P13 S4/P14 S5/P15 S6/P16 S7/P17 S8 S9 S10 S11 S12 S13 S14 S15 S16 S17 S18 S19 S20 S21 S22 S23 S24 S25 S26 S27 S28 S29 S30 S31 S32 S33 S34 S35 S36 S37 S38 S39 S40 S41 S42 S43 PIN No. 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 NAME S44 S45 S46 S47 S48 S49 S50 S51 S52 S53 S54 S55 S56 S57 S58 S59 S60 S61 S62 S63 S64 S65 S66 S67 S68 S69 S70 S71 S72 S73 COM0 COM1 COM2 COM3 V3 V2 V1 P70/INT0/T0LCP P71/INT1/T0HCP PO0 P01 P02 P03 P04 P05 P06 P07 RMIN/P73/INT3/T0IN UTX/P34 URX/P35 No.A2006-6/17 LC877G16A System Block Diagram Interrupt control Standby control ROM RC generator CF Clock PC RES Reset control ACC B Register C Register Bus interface ALU PSW Base timer Port 0 RAR Timer 0 INT Noise filter LCD controller Port 1/Segment Port 3/UART Port 7 RAM Stack pointer Timer 4 Remote control receiver circuit Timer 8 Timer 5 No.A2006-7/17 LC877G16A Pin Description Pin Name VSS1 VDD1 Port 0 P00 to P07 I/O I/O - power supply + power supply • 8-bit I/O port • I/O can be specified in 1-bit units. • Pull-up resistors can be turned on and off in 1-bit units. • HOLD release input • Port 0 interrupt input Port 3 P34, P35 I/O • 2-bit I/O port • I/O can be specified in 1-bit units. • Pull-up resistors can be turned on and off in 1-bit units. • Multiplexed pin function UTX: UART transmit data output URX: UART receive data input XT1 Port 7 P70, P71, P73 I I/O • Test pin • 1-bit input port • 3-bit I/O port • I/O can be specified in 1-bit units. • Pull-up resistors can be turned on and off in 1-bit units. • Multiplexed pin function P70: INT0 input/HOLD release input/timer 0L capture input/watchdog timer output P71: INT1 input/HOLD release input/timer 0H capture input P73: INT3 input (with noise filter input/timer 0 event input/timer 0H capture input/infrared remote control receive input Interrupt acknowledge type Rising INT0 INT1 INT3 Enable Enable Enable Falling Enable Enable Enable Rising & Falling Disable Disable Enable H level Enable Enable Disable L level Enable Enable Disable No No Yes Function Option No No Yes S0/P10 to S7/P17 S8 to S73 COM0 to COM3 V1 to V3 RES CF1 CF2 I/O O O I/O I I O • LCD display segment output • Can be used as a general-purpose I/O port (P1). • LCD segment output • LCD common output • LCD bias • Reset pin • Ceramic resonator input pin • Ceramic resonator output pin No No No No No No No Port Output Types The table below lists the types of port outputs and the presence/absence of a pull-up resistor. Data can be read into any input port even if it is in the output mode. Port Name P00 to P07 Option Selected in Units of 1 bit Option Type 1 2 P34 to P35 1 bit 1 2 P70 P71, P73 S0/P10 to S7/P17 S8 to S73 COM0 to COM3 V1 to V3 XT1 No No No No No No No CMOS N-channel open drain CMOS N-channel open drain N-channel open drain CMOS CMOS Dedicated LCD output Dedicated LCD output Dedicated LCD input Input only Output Type Pull-up Resistor Programmable Programmable Programmable Programmable Programmable Programmable Programmable No No No No No.A2006-8/17 LC877G16A Absolute Maximum Ratings at Ta = 25°C, VSS1 = 0V Parameter Maximum supply voltage LCD supply voltage Input voltage Input/output voltage Peak output current High level output current IOPH(2) IOPH(3) Mean output current (Note 1-1) IOMH(2) IOMH(3) Total output current Peak output Low level output current current IOPL(1) IOPL(2) IOPL(3) Mean output current (Note 1-1) Total output current Allowable power dissipation Operating ambient temperature Storage ambient temperature Tstg Topr -40 -55 Pd max TQFP100(14×14) Ta=-40 to +85°C IOML(1) IOML(2) IOML(3) ΣIOAL(1) Ports 0, 34, 35 Port 7 Port 1 Ports 0, 34, 35 Ports 7 Port 1 Ports 0,1,34, 35, 7 • Each pin used • Each pin used • Each pin used • Each pin used • Each pin used • Each pin used Total of all pins ΣIOAH(1) Ports 71, 73 Port 1 Ports 0,1,34, 35, 7 IOMH(1) Ports 71, 73 Port 1 Ports 0, 34, 35 VLCD VI(1) VIO(1) IOPH(1) Symbol VDD max Pin/Remarks VDD1 Conditions VDD[V] min -0.3 -0.3 -0.3 -0.3 • CMOS output selected • Each pin used • Each pin used • Each pin used • CMOS output selected • Each pin used • Each pin used • Each pin used Total of all pins -10 -5 -5 -7.5 -3 -3 -45 20 10 10 15 7.5 7.5 80 231 +85 °C +125 mW mA Specification typ max +6.5 VDD VDD+0.3 VDD+0.3 unit V1, V2, V3 XT1, CF1, RES Ports 0, 1, 3, 7 Ports 0, 34, 35 V Note 1-1: The mean output current is a mean value measured over 100ms. No.A2006-9/17 LC877G16A Allowable Operating Conditions at Ta = -40°C to +85°C, VSS1 = 0V Parameter Operating supply voltage range (Note 2-1) Memory retention supply voltage High level input voltage VIH(2) VIH(3) Low level input voltage VIL(1) P71 interrupt side XT1, CF1, RES Ports 0, 1 Output disabled VIH(1) Ports 0, 1, 3, 7 • Output disabled • When INT1VTSL=0 (P71 only) • Output disabled • When INT1VTSL=1 2.7 to 5.5 2.7 to 5.5 4.0 to 5.5 2.7 to 4.0 VIL(2) Ports 34, 35, 7 • Output disabled • When INT1VTSL=0 (P71 only) VIL(3) P71 interrupt side • Output disabled • When INT1VTSL=1 VIL(4) VIL(5) Instruction cycle time (Note 2-2) External system clock frequency FEXCF(1) CF1 • CF2 pin open • System clock frequency division ration=1/1 • External system clock duty=50 ± 5% • CF2 pin open • System clock frequency division ratio = 1/2 Oscillation frequency range (Note 2-3) FmRC FmCF (1) CF1, CF2 5MHz ceramic resonator oscillation See Fig. 1. Internal RC oscillation 2.7 to 5.5 0.3 1.0 2.0 2.7 to 5.5 5 2.7 to 5.5 0.2 10 MHz 2.7 to 5.5 0.1 5 tCYC 2.7 to 5.5 0.588 30 μs XT1 CF1, RES 2.7 to 5.5 2.7 to 5.5 2.7 to 5.5 VSS VSS VSS 0.45VDD 0.2VDD 0.25VDD 4.0 to 5.5 2.7 to 4.0 2.7 to 5.5 0.3VDD +0.7 0.85VDD 0.75VDD VSS VSS VSS VSS VDD VHD VDD1 Keep RAM and register data in HOLD mode. 2.0 5.5 Symbol VDD(1) Pin/Remarks VDD1 Conditions VDD[V] 0.588μs≤tCYC≤30μs 2.7 5.5 min Specification typ max unit VDD VDD 0.15VDD +0.4 0.2VDD 0.1VDD +0.4 0.2VDD V Note 2-1: VDD must be held greater than or equal to 3.0V in the flash ROM onboard programming mode. Note 2-2: Relationship between tCYC and oscillation frequency is 3/FmCF at a division ratio of 1/1 and 6/FmCF at a division ratio of 1/2. Note 2-3: See Tables 1 and 2 for the oscillation constants. No.A2006-10/17 LC877G16A Electrical Characteristics at Ta = -40°C to +85°C, VSS1 = 0V Parameter High level input current Symbol IIH(1) Pin/Remarks Ports 0, 1, 3, 7 Conditions VDD[V] • Output disabled • Pull-up resistor off • VIN=VDD (Including output Tr off-leakage current) IIH(2) IIH(3) IIH(4) Low level input current IIL(1) RES VIN=VDD • Input port specification • VIN=VDD CF1 Ports 0, 1, 3, 7 VIN=VDD • Output disabled • Pull-up resistor off • VIN=VSS (Including output Tr off-leakage current) IIL(2) IIL(3) IIL(4) High level output voltage VOH(1) VOH(2) VOH(3) VOH(4) VOH(5) VOH(6) VOH(7) Low level output voltage VOL(1) VOL(2) VOL(3) VOL(4) VOL(5) VOL(6) VOL(7) LCD output voltage VODLS S0 to S73 Port 1 Port 7 Ports 0, 1, 34, 35 Port 1 Ports 71 to 73 RES XT1 CF1 CMOS output ports 0, 34, 35 VIN=VSS • Input port specification • VIN=VSS VIN=VSS IOH=-1mA IOH=-0.4mA IOH=-0.2mA IOH=-0.4mA IOH=-0.2mA IOH=-0.4mA IOH=-0.2mA IOL=10mA IOL=1.6mA IOL=1mA IOL=1.6mA IOL=1mA IOL=1.6mA IOL=1mA • IO=0mA • VLCD, 2/3VLCD 1/3VLCD level output • See Fig. 6. VODLC COM0 to COM3 • IO=0mA • VLCD, 2/3VLCD 1/2VLCD, 1/3VLCD level output • See Fig. 6. LCD bias resistor RLCD(2) RLCD(1) Resistance per one bias resistor • Resistance per one bias resistor • Resistor division 1/2 mode Pull-up MOS Tr. resistor Hysteresis voltage Pin capacitance CP Rpu(1) Rpu(2) VHYS(1) • Port 7 • RES All pins • For pins other than that under test: VIN=VSS • f=1MHz • Ta=25°C 2.7 to 5.5 10 pF 2.7 to 5.5 0.1VDD V • Ports 0, 1, 3, 7 VOH=0.9VDD 4.5 to 5.5 2.7 to 4.5 15 18 35 50 80 150 See Fig. 6. 2.7 to 5.5 30 kΩ See Fig. 6. 2.7 to 5.5 60 2.7 to 5.5 0 ±0.2 2.2 to 5.5 2.2 to 5.5 2.2 to 5.5 4.5 to 5.5 3.0 to 5.5 2.7 to 5.5 3.0 to 5.5 2.7 to 5.5 3.0 to 5.5 2.7 to 5.5 4.5 to 5.5 3.0 to 5.5 2.7 to 5.5 3.0 to 5.5 2.7 to 5.5 3.0 to 5.5 2.7 to 5.5 -1 -1 -15 VDD-1 VDD-0.4 VDD-0.4 VDD-0.4 VDD-0.4 VDD-0.4 VDD-0.4 1.5 0.4 0.4 0.4 0.4 0.4 0.4 V 2.2 to 5.5 -1 2.7 to 5.5 1 2.7 to 5.5 1 min Specification typ max unit XT1 2.7 to 5.5 2.7 to 5.5 1 15 μA 2.7 to 5.5 0 ±0.2 No.A2006-11/17 LC877G16A Pulse Input Conditions at Ta = -40°C to +85°C, VSS1 = 0V Parameter High/low level pulse width tPIH(2) tPIL(2) tPIH(3) tPIL(3) tPIH(4) tPIL(4) tPIH(5) tPIL(5) tPIL(5) RES INT3(P73) (Noise rejection ratio is 1/1.) INT3(P73) (Noise rejection ratio is 1/32.) INT3(P73) (Noise rejection ratio is 1/128.) RMIN(P73) Recognized as a signal by infrared remote control receiver circuit Resetting is enabled. 2.7 to 5.5 2.7 to 5.5 4 200 RMCK (Note4-1) μs • Interrupt source flag can be set. • Event input for timer 0 is enabled. 2.7 to 5.5 256 • Interrupt source flag can be set. • Event input for timer 0 is enabled. 2.7 to 5.5 64 • Interrupt source flag can be set. • Event input for timer 0 is enabled. 2.7 to 5.5 2 tCYC Symbol tPIH(1) tPIL(1) Pin/Remarks INT0(P70), INT1(P71) Conditions VDD[V] • Interrupt source flag can be set. • Event input for timer 0 is enabled. 2.7 to 5.5 1 min Specification typ max unit Note 4-1: RMCK denotes the reference frequency of the remote control receiver circuit (40tCYC/50tCYC). Consumption Current Characteristics at Ta = -40°C to +85°C, VSS1 = 0V Parameter Normal mode consumption current (Note 5-1) IDDOP(3) IDDOP(4) HALT mode consumption current (Note 5-1) IDDHALT(1) IDDOP(2) Symbol IDDOP(1) Pins/ Remarks VDD1 Conditions VDD[V] • FmCF=5MHz ceramic resonator oscillation • System clock set to CF 5MHz side • Internal RC oscillation stopped • 1/1 frequency division ratio • FmCF=0Hz (oscillation stopped) • System clock set to internal RC oscillation • 1/2 frequency division ratio HALT mode • FmCF=5MHz ceramic resonator oscillation • System clock set to CF 5MHz side IDDHALT(2) IDDHALT(3) IDDHALT(4) HOLD mode consumption current IDDHOLD(2) IDDHOLD(1) • Internal RC oscillation stopped • 1/1 frequency division ratio HALT mode • FmCF=0Hz (oscillation stopped) • System clock set to internal RC oscillation • 1/2 frequency division ratio HOLD mode • CF1=VDD or open (When using external clock) 2.7 to 3.6 0.03 10 2.7 to 3.6 4.5 to 5.5 2.7 to 3.6 4.5 to 5.5 0.5 0.3 0.2 0.14 1.5 0.8 0.3 14 4.5 to 5.5 1.1 3.2 2.7 to 3.6 0.2 0.6 mA 4.5 to 5.5 2.7 to 3.6 4.5 to 5.5 min Specification typ 2.9 1.6 0.4 max 7.2 3.9 1.3 unit μA Note 5-1: The consumption current value do not include current that flows into the output transistors and internal pullup resistors. No.A2006-12/17 LC877G16A UART (Full Duplex) Operating Conditions at Ta = -40°C to +85°C, VSS1 = 0V Parameter Transfer rate Symbol UBR Pin/Remarks UTX(P34), URX(P35) Conditions VDD[V] 2.7 to 5.5 min 16/3 Specification typ max 8192/3 unit tCYC Data length: 7/8/9 bits (LSB first) Stop bits: 1 bit (2-bit in continuous data transmission) Parity bits: None Example of 8-bit Data Transmission Mode Processing (Transmit Data=55H) Start bit Start of transmission Transmit data (LSB first) Stop bit End of transmission UBR Example of 8-bit Data Reception Mode Processing (Receive Data=55H) Stop bit Receive data (LSB first) End of reception Start bit Start of reception UBR No.A2006-13/17 LC877G16A Main System Clock Oscillator Circuit Characteristics Given below are the characteristics of a sample main system clock oscillator circuit that are measured using a SANYO-designated oscillation characteristics evaluation board and external components with circuit constant values with which the oscillator vendor confirmed normal and stable oscillation. Table 1 Characteristics of a sample main system clock oscillator circuit with a ceramic resonator Oscillation Circuit Parameters Frequency Manufacturer Resonator Name C1 [pF] CSTCR5M00G53-R0 5MHz Murata CSTLS5M00G53-B0 (15) (15) Open 2.2k 2.7 to 5.5 0.05 0.15 (15) C2 [pF] (15) Rf1 [Ω] Open Rd1 [Ω] 2.2k 2.7 to 5.5 Operating Voltage Range[V] typ [ms] 0.05 Stabilization Time max [ms] Values shown in 0.15 parentheses are capacitance included in the resonator Notes The oscillation stabilization time is a period until the oscillation becomes stable after VDD becomes higher than minimum operating voltage. (See Fig. 3) Notes: Since the circuit pattern affects the oscillation frequency, place the oscillation-related parts as close to the oscillation pins as possible with the shortest possible pattern length. CF1 CF2 Rf1 Rd1 C2 CF C1 Figure 1 Ceramic Oscillator Circuit 0.5VDD Figure 2 AC Timing Measurement Point No.A2006-14/17 LC877G16A VDD Power supply VDD lower limit 0V Reset time RES Internal RC oscillation tmsCF CF1, CF2 Operating mode Undefined Reset Instruction execution Reset Time and Oscillation Stabilization Time HOLD release signal Without HOLD release signal HOLD release signal valid Internal RC oscillation tmsCF CF1, CF2 Operation mode HOLD HALT HOLD Release Signal and Oscillation Stabilization Time Figure 3 Oscillation Stabilization Time No.A2006-15/17 LC877G16A VDD RRES Note: Select CRES and RRES value to assure that at least 200μs reset time is generated after the VDD becomes higher than the minimum operating voltage. RES CRES Figure 4 Reset Circuit tPIL tPIH Figure 5 Pulse Input Timing Signal Waveform VDD SW : ON/OFF (programmable) RLCD RLCD RLCD RLCD VLCD RLCD RLCD 2/3VLCD RLCD 1/2VLCD RLCD 1/3VLCD RLCD RLCD GND SW: ON (VLCD=VDD) Figure 6 LCD Bias Resistor No.A2006-16/17 LC877G16A SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein. SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all semiconductor products fail or malfunction with some probability. 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SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's intellctual property rights which has resulted from the use of the technical information and products mentioned above. This catalog provides information as of January, 2012. Specifications and information herein are subject to change without notice. PS No.A2006-17/17