LC87F0808A

Ordering number : ENA1828 LC87F0808A Overview CMOS IC 8K-byte FROM and 256-byte RAM integrated 8-bit 1-chip Microcontroller The SANYO LC87F0808A is an 8-bit microcomputer that, centered around a CPU running at a minimum bus cycle time of 50.0ns, integrates on a single chip a number of hardware features such as 8K-byte flash ROM (On-boardprogrammable), 256-byte RAM, an On-chip-debugger, sophisticated 16-bit timers/counters (may be divided into 8-bit timers), a 16-bit timer/counter (may be divided into 8-bit timers/counters or 8-bit PWMs), two 8-bit timers with a prescaler, a base timer serving as a time-of-day clock, a high-speed clock counter, a synchronous SIO interface, an asynchronous/synchronous SIO interface, a UART interface (full duplex), motor control PWM , a 10/8-bit 10-channel AD converter, a system clock frequency divider, an internal reset and a 21-source 10-vector interrupt feature. This microcomputer is suitable for small motor control equipment. Features Flash ROM • Capable of On-board-programming with wide range (3.3 to 5.5V) of voltage source. • Block-erasable in 128 byte units • Writable in 2-byte units • 8192 × 8 bits RAM • 256 × 9 bits Minimum Bus Cycle • 50.0ns (20MHz at VDD=3.3V to 5.5V) Note: The bus cycle time here refers to the ROM read speed. * This product is licensed from Silicon Storage Technology, Inc. (USA), and manufactured and sold by SANYO Semiconductor Co., Ltd. Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment (home appliances, AV equipment, communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee thereof. If you should intend to use our products for applications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our customer shall be solely responsible for the use. Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer' s products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer' s products or equipment. Ver.1.00 91510HKIM 20100823-S00001 No.A1828-1/25 LC87F0808A Ports • Normal withstand voltage I/O ports Ports I/O direction can be designated in 1-bit units Ports I/O direction can be designated in 4-bit units • Dedicated oscillator ports/input ports • Reset pin • On-chip Debugger pin • Power pins 20 (P1n, P20, P21, P30 to P35, P70 to P73) 8 (P0n) 2 (CF1/XT1, CF2/XT2) 1 (RES) 1 (OWP0) 4 (VSS1, VSS2, VDD1, VDD2) Timers • Timer 0: 16-bit timer/counter with a capture register. Mode 0: 8-bit timer with an 8-bit programmable prescaler (with an 8-bit capture register) × 2 channels Mode 1: 8-bit timer with an 8-bit programmable prescaler (with an 8-bit capture register) + 8-bit counter (with an 8-bit capture register) Mode 2: 16-bit timer with an 8-bit programmable prescaler (with a 16-bit capture register) Mode 3: 16-bit counter (with a 16-bit capture register) • Timer 1: 16-bit timer/counter that supports PWM/toggle outputs Mode 0: 8-bit timer with an 8-bit prescaler (with toggle outputs) + 8-bit timer/ counter with an 8-bit prescaler (with toggle outputs) Mode 1: 8-bit PWM with an 8-bit prescaler × 2 channels Mode 2: 16-bit timer/counter with an 8-bit prescaler (with toggle outputs) (toggle outputs also possible from the lower-order 8 bits) Mode 3: 16-bit timer with an 8-bit prescaler (with toggle outputs) (The lower-order 8 bits can be used as PWM) • Timer 6: 8-bit timer with a 6-bit prescaler (with toggle outputs) • Timer 7: 8-bit timer with a 6-bit prescaler (with toggle outputs) • Base timer 1) The clock is selectable from the subclock (32.768kHz crystal oscillation), system clock, and timer 0 prescaler output. 2) Interrupts are programmable in 5 different time schemes 3) The base timer is unavailable when the CF oscillator circuit is selected SIO • SIO0: 8-bit Synchronous serial interface 1) LSB first/MSB first mode selectable 2) Built-in 8-bit baudrate generator (maximum transfer clock cycle=4/3tCYC) • SIO1: 8-bit asynchronous/synchronous serial interface Mode 0: Synchronous 8-bit serial I/O (2- or 3-wire configuration, 2 to 512 tCYC transfer clocks) Mode 1: Asynchronous serial I/O (half-duplex, 8 data bits, 1 stop bit, 8 to 2048 tCYC baudrates) Mode 2: Bus mode 1 (start bit, 8 data bits, 2 to 512 tCYC transfer clocks) Mode 3: Bus mode 2 (start detect, 8 data bits, stop detect) UART • Full Duplex • 7/8/9 bit data bits selectable • 1 Stop bit (2 bits in continuous data transmission) • Built-in baudrate generator AD Converter: 10 bits/8 bits × 10 channels (internal: 2 channels) • 10/8 bits AD converter resolution selectable • Auto start function (It links an interrupt factor of MCPWM) No.A1828-2/25 LC87F0808A Remote Control Receiver Circuit (sharing pins with P73, INT3, and T0IN) • Noise rejection function (noise filter time constant selectable from 1 tCYC/32 tCYC/128 tCYC) Clock Output Function • Can generate clock outputs with a frequency of 1/1, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64 of the source clock selected as the system clock. • Can generate the source clock for the subclock Analog Comparator / Amplifier × 2 channels • Analog comparator / amplifier selectable (each channel) • Analog comparator Interrupt MCPWM: Motor Control 12-bit PWM × 6 channels • Dead time is programmable. • Forced stop is possible by the output of the analog comparator and the INT terminals. • Edge-aligned / center-aligned selectable Watchdog Timer • Can generate the internal reset signal on a timer overflow monitored by the WDT-dedicated low-speed RC oscillation clock (30kHz). • Allows selection of continue, stop, or hold mode operation of the counter on entry into the HALT/HOLD mode. Interrupts • 21 sources, 10 vector addresses 1) Provides three levels (low (L), high (H), and highest (X)) of multiplex interrupt control. Any interrupt requests of the level equal to or lower than the current interrupt are not accepted. 2) When interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest level takes precedence over the other interrupts. For interrupts of the same level, the interrupt into the smallest vector address takes precedence. No. 1 2 3 4 5 6 7 8 9 10 Vector Address 00003H 0000BH 00013H 0001BH 00023H 0002BH 00033H 0003BH 00043H 0004BH Level X or L X or L H or L H or L H or L H or L H or L H or L H or L H or L INT0 INT1 INT2/T0L/INT4 INT3/Base timer T0H T1L/T1H SIO0/UART1 receive SIO1/UART1 transmit/MCPWM ADC/T6/T7 Port 0/CMP1/CMP2 Interrupt Source • Priority levels X > H > L • Of interrupts of the same level, the one with the smallest vector address takes precedence. Subroutine Stack Levels: 128levels (The stack is allocated in RAM.) High-speed Multiplication/Division Instructions • 16 bits × 8 bits (5 tCYC execution time) • 24 bits × 16 bits (12 tCYC execution time) • 16 bits ÷ 8 bits (8 tCYC execution time) • 24 bits ÷ 16 bits (12 tCYC execution time) No.A1828-3/25 LC87F0808A Oscillation Circuits • Internal oscillation circuits Medium-speed RC oscillation circuit: For system clock (1MHz) High-speed RC oscillation circuit: For system clock (20MHz) Low-speed RC oscillation circuit: For watch dog timer (30kHz) • External oscillation circuits Hi-speed CF oscillation circuit: For system clock, with internal Rf Low speed crystal oscillation circuit: For low-speed system clock, with internal Rf 1) The CF and crystal oscillation circuits share the same pins. The active circuit is selected under program control. 2) The CF and the crystal oscillation circuits stop operating in the system reset state and start oscillating when the oscillation is enabled with an instruction. System Clock Divider Function • Can run on low current. • The minimum instruction cycle selectable from 150ns, 300ns, 600ns, 1.2μs, 2.4μs, 4.8μs, 9.6μs, 19.2μs and 38.4μs (at a main clock rate of 20MHz). Internal Reset Function • Power-on reset (POR) function 1) POR reset is generated only at power-on time. 2) The POR release level can be selected from 8 levels (1.67V, 1.97V, 2.07V, 2.37V, 2.57V, 2.87V, 3.86V and 4.35V) through option configuration. • Low-voltage detection reset (LVD) function 1) LVD and POR functions are combined to generate resets when power is turned on and when power voltage falls below a certain level. 2) The use/disuse of the LVD function and the low voltage threshold level (7 levels: 1.91V, 2.01V, 2.31V, 2.51V, 2.81V, 3.79V, 4.28V). Standby Function • HALT mode: Halts instruction execution while allowing the peripheral circuits to continue operation. 1) Oscillation is not halted automatically. 2) There are three ways of resetting the HALT mode. (1) Setting the reset pin to the low level (2) System resetting by watchdog timer or low-voltage detection (3) Occurrence of an interrupt • HOLD mode: Suspends instruction execution and the operation of the peripheral circuits. 1) The CF, RC and crystal oscillators automatically stop operation. 2) There are four ways of resetting the HOLD mode. (1) Setting the reset pin to the lower level. (2) System resetting by watchdog timer or low-voltage detection (3) Having an interrupt source established at either INT0, INT1, INT2 or INT4 * INT0 and INT1 HOLD mode reset is available only when level detection is set. (4) Having an interrupt source established at port 0. • X'tal HOLD mode: Suspends instruction execution and the operation of the peripheral circuits except the base timer. 1) The CF and RC oscillator automatically stop operation. 2) The state of crystal oscillation established when the X'tal HOLD mode is entered is retained. 3) There are five ways of resetting the X'tal HOLD mode. (1) Setting the reset pin to the low level. (2) System resetting by watchdog timer or low-voltage detection. (3) Having an interrupt source established at either INT0, INT1, INT2 or INT4 * INT0 and INT1 HOLD mode reset is available only when level detection is set. (4) Having an interrupt source established at port 0. (5) Having an interrupt source established in the base timer circuit. Note: Available only when X’tal oscillation is selected. No.A1828-4/25 LC87F0808A On-chip Debugger • Supports software debugging with the IC mounted on the target board. Data Security Function (flash versions only) • Protects the program data stored in flash memory from unauthorized read or copy. Note: This data security function does not necessarily provide absolute data security. Package Form • QFP36 (7×7): Lead-/Halogen-free type Development Tools • On-chip debugger: TCB87 type C + LC87F0808A Programming Boards Package QFP36(7×7) Programming boards W87F24Q Flash ROM Programmer Maker Single Programmer Flash Support Group, Inc. (FSG) Gang Programmer Single/Gang Programmer Gang Sanyo Programmer In-circuit/Gang Programmer Model AF9709/AF9709B/AF9709C (Including Ando Electric Co., Ltd. models) AF9723/AF9723B(Main body) (Including Ando Electric Co., Ltd. models) AF9833(Unit) (Including Ando Electric Co., Ltd. models) SKK/SKK Type B (SanyoFWS) SKK-4G (SanyoFWS) SKK-DBG Type C (SanyoFWS) Supported Version Rev 03.28 or later Application Version 1.06 or later Chip Data Version 2.26 or later Application Version 1.06 or later Chip Data Version 2.31 or later LC87F0808 Device 87f008SU (3B247) - For information about AF-Series: Flash Support Group, Inc. TEL: +81-53-459-1050 E-mail: sales@j-fsg.co.jp No.A1828-5/25 LC87F0808A Package Dimensions unit : mm (typ) 3162C 9.0 7.0 27 28 19 18 36 1 0.65 (0.9) 1.7max 10 9 0.3 0.15 0.1 (1.5) SANYO : QFP36(7X7) P04/AN4 P05/AN5/CKO P06/AN6/T6O P07/AN7/T7O P20/INT4 P21/INT4/BUZ P70/INT0/T0LCP P71/INT1/T0HCP P72/INT2/T0LCP/T0IN 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 P03/AN3 P02/AN2 P01/AN1 P00/AN0 VSS2 VDD2 P17/T1PWMH/URX/CMP2O P16/T1PWML/UTX/CMP2IA P15/SCK1/CMP2IB Pin Assignment 7.0 9.0 0.5 28 29 30 31 32 33 34 35 36 LC87F0808A P14/SI1/SB1/CMP1O P13/SO1/CMP1IA P12/SCK0/CMP1IB P11/SI0/SB0 P10/SO0 P35/PULSG2 P34/PULSG2 P33/PULSG1 P32/PULSG1 P73/INT3/T0HCP/T0IN RES OWP0 VSS1 CF1/XT1 CF2/XT2 VDD1 P30/PULSG0 P31/PULSG0 1 2 3 4 5 6 7 8 9 Top view SANYO: QFP36 (7×7) “Lead-/Halogen-free Type” No.A1828-6/25 LC87F0808A QFP36 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 NAME P73/INT3/T0HCP/T0IN RES OWP0 VSS1 CF1/XT1 CF2/XT2 VDD1 P30/PULSG0 P31/PULSG0 P32/PULSG1 P33/PULSG1 P34/PULSG2 P35/PULSG2 P10/SO0 P11/SI0/SB0 P12/SCK0/CMP1IB(+) P13/SO1/CMP1IA(-) P14/SI1/SB1/CMP1O QFP36 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 NAME P15/SCK1/CMP2IB(+) P16/T1PWML/UTX/CMP2IA(-) P17/T1PWMH/URX/CMP2O VDD2 VSS2 P00/AN0 P01/AN1 P02/AN2 P03/AN3 P04/AN4 P05/AN5/CKO P06/AN6/T6O P07/AN7/T7O P20/INT4 P21/INT4/BUZ P70/INT0/T0LCP P71/INT1/T0HCP P72/INT2/T0LCP/T0IN No.A1828-7/25 LC87F0808A System Block Diagram Interrupt control IR PLA Standby control Flash ROM RC MRC Clock generator CF/ X'tal PC RES Reset control ACC WDT Reset circuit (LVD/POR) B register C register SIO0 Bus interface ALU SIO1 Port 0 Timer 0 Port 1 PSW Timer 1 Port 2/INT4 RAR Timer 6 Port 3 RAM Timer 7 Port 7 Stack pointer Base timer ADC On-chip debugger MCPWM INT0-2 INT3 (Noise filter) UART1 No.A1828-8/25 LC87F0808A Pin Description Pin Name VSS1,VSS2 VDD1, VDD2 Port 0 P00 to P07 I/O I/O - Power supply pins + Power supply pins • 8-bit I/O port • I/O specifiable in 4-bit units • Pull-up resistors can be turned on and off in 4-bit units. • HOLD reset input • Port 0 interrupt input • Pin functions P05: System clock output P06: Timer 6 toggle output P07: Timer 7 toggle output P00 (AN0) to P07 (AN7): AD converter input Port 1 P10 to P17 I/O • 8-bit I/O port • I/O specifiable in 1-bit units • Pull-up resistors can be turned on and off in 1-bit units. • Pin functions P10: SIO0 data output P11: SIO0 data input/bus I/O P12: SIO0 clock I/O P13: SIO1 data output P14: SIO1 data input / bus I/O P15: SIO1 clock I/O P16: Timer 1 PWML output / UART transmit P17: Timer 1 PWMH output / UART receive Yes Yes Description Option No No P12 to P17: analog comparator / amplifier I/O pins P12: CMP1(+) input / AMP1(+) input P13: CMP1(-) input / AMP1(-) input P14: CMP1 output / AMP1 output P15: CMP2(+) input / AMP2(+) input P16: CMP2(-) input / AMP2(-) input P17: CMP2 output / AMP2 output Port 2 P20 to P21 I/O • 2-bit I/O port • I/O specifiable in 1-bit units • Pull-up resistors can be turned on and off in 1-bit units. • Pin functions P21: Beeper output P20 to P21: INT4 input/HOLD reset input/timer 1 event input/timer 0L capture input/ timer 0H capture input Interrupt acknowledge types Rising INT4 • 6-bit I/O port • I/O specifiable in 1-bit units • Pull-up resistors can be turned on and off in 1-bit units. • Pin functions P30 to p35 : motor control PWM output pins P30: PULSG0 output P31: PULSG0 output P32: PULSG1 output P33: PULSG1 output P34: PULSG2 output P35: PULSG2 output Yes enable Falling enable Rising & Falling enable H level disable L level disable Yes Port 3 P30 to P35 I/O Continued on next page. No.A1828-9/25 LC87F0808A Continued from preceding page. Pin Name Port 7 P70 to P73 I/O I/O • 4-bit I/O port • I/O specifiable in 1-bit units • Pull-up resistors can be turned on and off in 1-bit units. • Pin functions P70: INT0 input/HOLD reset input/timer 0L capture input P71: INT1 input/HOLD reset input/timer 0H capture input P72: INT2 input/HOLD reset input/timer 0 event input / timer 0L capture input P73: INT3 input (with noise filter)/ timer 0 event input/timer 0H capture input Interrupt acknowledge types Rising INT0 INT1 INT2 INT3 OWP0 RES CF1/XT1 enable enable enable enable Falling enable enable enable enable Rising & Falling disable disable enable enable H level enable enable disable disable L level enable enable disable disable No Description Option I/O I/O I On-chip debugger (exclusive pin) External reset input/internal reset output • Ceramic resonator or 32.768kHz crystal oscillator input pin • Pin function General-purpose input port No No No CF2/XT2 I/O • Ceramic resonator or 32.768kHz crystal oscillator output pin • Pin function General-purpose input port No Port Output Types The table below lists the types of port outputs and the presence/absence of a pull-up resistor. Data can be read into any input port even if it is in the output mode. Port Name P00 to P07 Option selected in units of 1 bit Option type 1 2 P10 to P17 1 bit 1 2 P20 to P21 1 bit 1 2 P30 to P35 1 bit 1 2 P70 to P73 No CMOS Nch-open drain CMOS Nch-open drain CMOS Nch-open drain CMOS Nch-open drain CMOS Output type Pull-up resistor Programmable (Note 1) No Programmable Programmable Programmable Programmable Programmable Programmable Programmable Note 1: The control of the presence or absence of the programmable pull-up resistors for port 0 and the switching between low-and high-impedance pull-up connection is exercised in nibble (4-bit) units (P00 to 03 or P04 to 07). No.A1828-10/25 LC87F0808A User Option Table Option name Port output type Option to be applied on P00 to P07 Flash-rom version Option selected in units of 1 bit CMOS Nch-open drain P10 to P17 1 bit CMOS Nch-open drain P20 to P21 1 bit CMOS Nch-open drain P30 to P35 1 bit CMOS Nch-open drain Program start address Protect area (Note 1) Low-voltage detection reset function Power-on reset function Detect level Power-On reset level Detect function 00000h 01E00h 00000h to 01BFFh 01C00h to 01EFFh Enable: Use Disable: Not Used 7-level 8-level Option selection (Note 1) This option selects the area to be write protected at the time of the On-board writing. Recommended Unused Pin Connections Recommended unused pin connections Port Name Board P00 to P07 P10 to P17 P20 to P21 P30 to P35 P70 to P73 CF1/XT1 CF2/XT2 Open Open Open Open Open Pulled low with a 100kΩ resistor or less Pulled low with a 100kΩ resistor or less Software Output low Output low Output low Output low Output low General-purpose input port General-purpose input port On-chip Debugger Pin Connection Requirements OWP0 of the On-chip-debugger terminal must add pull-down resistor of 100kΩ. The connection with TCB87 Type C are OWP0/VDD/VSS Note: Be sure to electrically short-circuit between the VSS1 and VSS2 pins and between the VDD1 and VDD2 pins. No.A1828-11/25 LC87F0808A Absolute Maximum Ratings at Ta = 25°C, VSS1 = VSS2 = 0V Parameter Maximum supply voltage Input voltage Input/output voltage Peak output High level output current current IOPH(2) Mean output current (Note 1-1) Total output current Peak output current Low level output current IOPL(2) IOPL(3) Mean output current (Note 1-1) IOML(2) IOML(3) Total output current Power Dissipation Pd max(2) ΣIOAL(1) ΣIOAL(2) Pd max(1) IOML(1) IOMH(2) ΣIOAH(1) ΣIOAH(2) IOPL(1) Port7 Ports 0, 2, 7 Ports 1, 3 P02 to P07 Ports 1, 2, 3 P00, P01 Port 7 P02 to P07 Ports 1, 2, 3 P00, P01 Port 7 Ports 0, 2, 7 Ports 1, 3 QFP36(7×7) Per 1 applicable pin Per 1 applicable pin Total of all applicable pins Total of all applicable pins Ta=-40 to +85°C Package only Ta=-40 to +85°C Package with thermal resistance board (Note 1-2) Operating ambient Temperature Storage ambient temperature Tstg Topr -40 -55 +85 °C +125 244 Per 1 applicable pin Per 1 applicable pin Per 1 applicable pin IOMH(1) Port7 Ports 0, 1, 2, 3 IOPH(1) VI VIO CF1 CF2 Ports 0, 1, 2, 3 Port 7 Ports 0, 1, 2, 3 CMOS output select Per 1 applicable pin Per 1 applicable pin CMOS output select Per 1 applicable pin Per 1 applicable pin Total of all applicable pins Total of all applicable pins Per 1 applicable pin -10 -5 -7.5 -3 -25 -25 20 30 10 15 20 7.5 45 45 115 mW mA -0.3 VDD+0.3 Symbol VDD max Pin/Remarks VDD1 Conditions VDD[V] min -0.3 -0.3 Specification typ max +6.5 VDD+0.3 V unit Note 1-1: The mean output current is a mean value measured over 100ms. Note 1-2: SEMI standards thermal resistance board (size: 76.1×114.3×1.6tmm, glass epoxy) is used. No.A1828-12/25 LC87F0808A Allowable Operating Conditions at Ta = -40°C to +85°C, VSS1 = VSS2 = 0V Parameter Operating supply voltage Memory sustaining supply voltage High level input voltage VIH(1) VIH(2) VIH(3) Low level input voltage VIL(2) Ports 0 VIL(1) Ports 1, 2, 3, 7 Ports 0 CF1, CF2, RES Ports 1, 2, 3, 7 3.3 to 5.5 3.3 to 5.5 3.3 to 5.5 4.0 to 5.5 3.3 to 4.0 4.0 to 5.5 3.3 to 4.0 VIL(3) Instruction cycle time (Note 2-1) External system clock frequency Oscillation frequency range (Note 2-2) FmCF(3) FmMRC CF1, CF2 FmCF(2) CF1, CF2 FmCF(1) CF1, CF2 FEXCF CF1 • CF2 pin open • System clock frequency division ratio=1/1 • External system clock duty=50±5% 20MHz ceramic oscillation See Fig. 1. 10MHz ceramic oscillation See Fig. 1. 4MHz ceramic oscillation See Fig. 1. Internal High-speed RC oscillation. 1/2 frequency division ration. (RCCTD=0) FmRC FmSRC FsX’tal XT1, XT2 (Note 2-3) 3.3 to 5.5 3.3 to 5.5 3.3 to 5.5 0.5 15 1.0 30 32.768 2.0 60 kHz Internal medium-speed RC oscillation Internal low-speed RC oscillation 32.768kHz crystal oscillation See Fig. 1. 3.3 to 5.5 19.0 20.0 21.0 3.3 to 5.5 3.3 to 5.5 3.3 to 5.5 20 10 4 MHz 3.3 to 5.5 0.1 20 tCYC 3.3 to 5.5 0.142 200 μs CF1, CF2, RES 3.3 to 5.5 0.3VDD+0.7 0.3VDD+0.7 0.75VDD VSS VSS VSS VSS VSS VDD VDD VDD 0.1VDD+0.4 0.2VDD 0.15VDD+0.4 0.2VDD 0.25VDD V VHD VDD1, VDD2 RAM and register contents sustained in HOLD mode. 2.0 Symbol VDD Pin/Remarks VDD1, VDD2 Conditions VDD[V] 0.142μs ≤ tCYC ≤ 200μs min 3.3 Specification typ max 5.5 unit Note 2-1: Relationship between tCYC and oscillation frequency is 3/FmCF at a division ratio of 1/1 and 6/FmCF at a division ratio of 1/2. Note 2-2: See Tables 1 and 2 for the oscillation constants. Note 2-3: When switching the system clock, allow an oscillation stabilization time of 100μs or longer after the high-speed RC oscillator circuit transmits from the "oscillation stopped" to "oscillation enabled" state. No.A1828-13/25 LC87F0808A Electrical Characteristics at Ta = -40°C to +85°C, VSS1 = VSS2 = 0V Parameter High level input current Symbol IIH(1) Pin/Remarks Ports 0, 1, 2, 3 Port 7 RES Conditions VDD[V] Output disabled Pull-up resistor off VIN=VDD (Including output Tr's off leakage current) IIH(2) Low level input current IIL(1) CF1, CF2 Ports 0, 1, 2, 3 Port 7 RES VIN=VDD Output disabled Pull-up resistor off VIN=VSS (Including output Tr's off leakage current) IIL(2) High level output voltage VOH(1) VOH(2) VOH(3) VOH(4) Low level output voltage VOL(1) VOL(2) VOL(3) VOL(4) VOL(5) Pull-up resistance Rpu(1) Ports 0, 1, 2, 3 Port 7 Rpu(2) Port 0 Port 7 P00, P01 Ports 0, 1, 2, 3 Port 3 CF1, CF2 Ports 0, 1, 2, 7 VIN=VSS IOH=-1mA IOH=-0.35mA IOH=-6mA IOH=-1.4mA IOL=10mA IOL=1.4mA IOL=1.4mA IOL=25mA IOL=4mA VOH=0.9VDD When Port 0 selected low-impedance pull-up. VOH=0.9VDD When Port 0 selected high-impedance pull-up. Hysteresis voltage Pin capacitance VHYS CP Ports 1, 2, 3, 7 RES All pins For pins other than that under test: VIN=VSS f=1MHz Ta=25°C 3.3 to 5.5 10 pF When Port 2 selected INT4. 3.3 to 5.5 0.1VDD V 3.3 to 5.5 100 210 400 3.3 to 5.5 4.5 to 5.5 3.3 to 5.5 4.5 to 5.5 3.3 to 5.5 4.5 to 5.5 3.3 to 5.5 3.3 to 5.5 4.5 to 5.5 3.3 to 5.5 4.5 to 5.5 15 35 -15 VDD-1 VDD-0.4 VDD-1 VDD-0.4 1.5 0.4 0.4 1.5 0.4 80 kΩ V 3.3 to 5.5 -1 3.3 to 5.5 15 μA 3.3 to 5.5 1 min Specification typ max unit No.A1828-14/25 LC87F0808A Serial I/O Characteristics at Ta = -40°C to +85°C, VSS1 = VSS2 = 0V SIO0 Serial I/O Characteristics (Note 4-1-1) Parameter Frequency Input clock Low level pulse width High level pulse width Output clock Frequency Low level pulse width High level pulse width Serial input Data setup time tsDI(1) SB0(P11), SI0(P11) Data hold time Output delay Input clock time tdD0(2) tdD0(3) thDI(1) tdD0(1) SO0(P10), SB0(P11) • Must be specified with respect to rising edge of SIOCLK. • See Fig. 5. • Continuous data transmission/reception mode (Note 4-1-2) • Synchronous 8-bit mode (Note 4-1-2) Output clock (Note 4-1-2) 3.3 to 5.5 3.3 to 5.5 0.05 (1/3)tCYC +0.08 μs 1tCYC +0.08 0.05 tSCKH(2) tSCK(2) tSCKL(2) SCK0(P12) • CMOS output selected • See Fig. 5. 3.3 to 5.5 1/2 tSCK 1/2 tSCKH(1) Symbol tSCK(1) tSCKL(1) 3.3 to 5.5 Pin/ Remarks SCK0(P12) Conditions VDD[V] • See Fig. 5. min 2 1 tCYC 1 4/3 Specification typ max unit Serial output Serial clock (1/3)tCYC +0.08 Note 4-1-1: These specifications are theoretical values. Add margin depending on its use. Note 4-1-2: Must be specified with respect to falling edge of SIOCLK. Must be specified as the time to the beginning of output state change in open drain output mode. See Fig. 5. SIO1 Serial I/O Characteristics (Note 4-2-1) Parameter Frequency Input clock Low level pulse width High level pulse width Frequency Output clock Low level pulse width High level pulse width Data setup time Serial input tsDI(2) SB1(P14), SI1(P14) Data hold time thDI(2) • Must be specified with respect to rising edge of SIOCLK. • See Fig. 5. 3.3 to 5.5 0.05 Output delay time Serial output tdD0(4) SO1(P13), SB1(P14) • Must be specified with respect to falling edge of SIOCLK. • Must be specified as the time to the beginning of output state change in open drain output mode. • See Fig. 5. 3.3 to 5.5 (1/3)tCYC +0.08 μs 0.05 tSCKH(4) tSCK(4) tSCKL(4) SCK1(P15) • CMOS output selected • See Fig. 5. 3.3 to 5.5 tSCKH(3) Symbol tSCK(3) tSCKL(3) Pin/ Remarks SCK1(P15) See Fig. 5. Conditions VDD[V] min 2 3.3 to 5.5 1 tCYC 1 2 1/2 tSCK 1/2 Specification typ max unit Note 4-2-1: These specifications are theoretical values. Add margin depending on its use. Serial clock No.A1828-15/25 LC87F0808A Pulse Input Conditions at Ta = -40°C to +85°C, VSS1 = VSS2 = 0V Parameter High/low level pulse width Symbol tPIH(1) tPIL(1) Pin/Remarks INT0(P70), INT1(P71), INT2(P72), INT4(P20 to P21) tPIH(2) tPIL(2) tPIH(3) tPIL(3) tPIH(4) tPIL(4) tPIL(5) INT3(P73) when noise filter time constant is 1/1 INT3(P73) when noise filter time constant is 1/32 INT3(P73) when noise filter time constant is 1/128 RES • Interrupt source flag can be set. • Event inputs for timer 0 are enabled. • Interrupt source flag can be set. • Event inputs for timer 0 are nabled. • Interrupt source flag can be set. • Event inputs for timer 0 are enabled. • Resetting is enabled. 3.3 to 5.5 200 μs 3.3 to 5.5 256 3.3 to 5.5 64 3.3 to 5.5 2 tCYC Conditions VDD[V] • Interrupt source flag can be set. • Event inputs for timer 0 or 1 are enabled. 3.3 to 5.5 1 min Specification typ max unit AD Converter Characteristics at VSS1 = VSS2 = 0V 10bits AD Converter Mode/Ta = -40°C to +85°C Parameter Resolution Absolute accuracy Conversion time Analog input voltage range Analog port input current IAINH IAINL VAIN=VDD VAIN=VSS TCAD VAIN Symbol N ET Pin/Remarks AN0(P00) to AN7(P07) AN8(AMP1O) AN9(AMP2O) • See Conversion time calculation formulas. (Note 6-2) (Note 6-1) Conditions VDD[V] 3.3 to 5.5 3.3 to 5.5 3.3 to 5.5 3.3 to 5.5 3.3 to 5.5 3.3 to 5.5 -1 8.5 VSS min Specification typ 10 max unit bit ±16 59.5 VDD 1 LSB μs V μA 8bits AD Converter Mode/Ta = -40°C to +85°C Parameter Resolution Absolute accuracy Conversion time Analog input voltage range Analog port input current IAINH IAINL VAIN=VDD VAIN=VSS TCAD VAIN Symbol N ET Pin/Remarks AN0(P00) to AN7(P07) AN8(AMP1O) AN9(AMP2O) • See Conversion time calculation formulas. (Note 6-2) (Note 6-1) Conditions VDD[V] 3.3 to 5.5 3.3 to 5.5 3.3 to 5.5 3.3 to 5.5 3.3 to 5.5 3.3 to 5.5 -1 2.9 VSS min Specification typ 8 ±1.5 20 VDD 1 max unit bit LSB μs V μA Conversion time calculation formulas: 10bits AD Converter Mode: TCAD (Conversion time) = ((42/(AD division ratio))+2)×(1/3)×tCYC 8bits AD Converter Mode: TCAD (Conversion time) = ((28/(AD division ratio))+2)× (1/3)×tCYC No.A1828-16/25 LC87F0808A External oscillation (FmCF) CF-20MHz CF-10MHz CF-4MHz Operating supply voltage range (VDD) 3.3V to 5.5V 3.3V to 5.5V 3.3V to 5.5V System division ratio (SYSDIV) 1/1 1/1 1/1 Cycle time (tCYC) 150ns 300ns 750ns AD division ratio (ADDIV) 10bit AD 1/4 1/4 1/4 8bit AD 1/2 1/2 1/2 8.5μs 17μs 42.5μs AD conversion time (TCAD) 10bit AD 8bit AD 2.9μs 5.8μs 14.5μs Note 6-1: The quantization error (±1/2LSB) must be excluded from the absolute accuracy. The absolute accuracy must be measured in the microcontroller's state in which no I/O operations occur at the pins adjacent to the analog input channel. Note 6-2: The conversion time refers to the period from the time an instruction for starting a conversion process till the time the conversion results register(s) are loaded with a complete digital conversion value corresponding to the analog input value. The conversion time is 2 times the normal-time conversion time when: • The first AD conversion is performed in the 10-bit AD conversion mode after a system reset. • The first AD conversion is performed after the AD conversion mode is switched from 8-bit to 10-bit conversion mode. Power-on Reset (POR) Characteristics at Ta = -40°C to +85°C, VSS1=VSS2=0V Specification Parameter POR release voltage Symbol PORRL Pin/Remarks Conditions • Select from option. (Note 7-1) Option selected voltage 1.67V 1.97V 2.07V 2.37V 2.57V 2.87V 3.86V 4.35V Detection voltage unknown state Power supply rise time PORIS • Power supply rise time from 0V to 1.6V. 100 ms POUKS • See Fig. 7. (Note 7-2) 0.7 0.95 min 1.55 1.85 1.95 2.25 2.45 2.75 3.73 4.21 typ 1.67 1.97 2.07 2.37 2.57 2.87 3.86 4.35 max 1.79 2.09 2.19 2.49 2.69 2.99 3.99 4.49 V unit Note7-1: The POR release level can be selected out of 8 levels only when the LVD reset function is disabled. Note7-2: POR is in an unknown state before transistors start operation. No.A1828-17/25 LC87F0808A Low Voltage Detection Reset (LVD) Characteristics at Ta = -40°C to +85°C, VSS1=VSS2=0V Specification Parameter LVD reset voltage (Note 8-2) Symbol LVDET Pin/Remarks Conditions • Select from option. (Note 8-1) (Note 8-3) • See Fig. 8. Option selected voltage 1.91V 2.01V 2.31V 2.51V 2.81V 3.79V 4.28V LVD hysteresys width LVHYS 1.91V 2.01V 2.31V 2.51V 2.81V 3.79V 4.28V Detection voltage unknown state Low voltage detection minimum width (Reply sensitivity) TLVDW LVUKS • See Fig. 8. (Note 8-4) • LVDET-0.5V • See Fig. 9. 0.2 ms 0.7 0.95 V min 1.81 1.91 2.21 2.41 2.71 3.69 4.18 typ 1.91 2.01 2.31 2.51 2.81 3.79 4.28 55 55 55 55 60 65 65 mV max 2.01 2.11 2.41 2.61 2.91 3.89 4.38 V unit Note8-1: The LVD reset level can be selected out of 7 levels only when the LVD reset function is enabled. Note8-2: LVD reset voltage specification values do not include hysteresis voltage. Note8-3: LVD reset voltage may exceed its specification values when port output state changes and/or when a large current flows through port. Note8-4: LVD is in an unknown state before transistors start operation. Comparator, Operational Amplifiers Characteristics at Ta=-40 to +85°C, VSS1=VSS2=0V Function CMP1, 2 Parameter Input commonmode voltage (Note9-1) Offset voltage CMP response speed AMP1, 2 AMP input voltage (Note9-1) Input offset voltage Slew rate Output current Sink IoSink SR Source VOPOFF CMP1IA, CMP1IB CMP2IA, CMP2IB CMP1O CMP2O IoSource CMP1IA,CMP1IB(+)=1V CMP2IA,CMP2IB(-)=0V CMP1O,CMP2O=VDD-1.5V CMP1IA,CMP1IB(+)=0V CMP2IA,CMP2IB(-)=1V CMP1O,CMP2O=VDD+0.5V 5.0 0.3 0.35 mA 5.0 2.5 3.5 mA Input common-mode voltage range 50pF VAMIN CMP1IA, CPM2IA VOFF(1) tCRT CMP1IA, CMP1IB CMP2IA, CMP2IB CMP1O CMP2O Input common-mode voltage range • Input common-mode voltage range • Input amplitude=100mV • Over drive=50mV 3.3 to 5.5 3.3 to 5.5 5.0 3 VSS VDD1.5V 20 V 3.3 to 5.5 200 ns Symbol VCMIN Pin/Remarks CMP1IA, CMP1IB CMP2IA, CMP2IB Conditions VDD[V] 3.3 to 5.5 3.3 to 5.5 min VSS Specification typ max VDD1.5V 20 unit V mV mV V/μs Note9-1: When VDD=5V, input voltage is effective from 0 to 3.5V. No.A1828-18/25 LC87F0808A Consumption Current Characteristics at Ta = -40°C to +85°C, VSS1 = VSS2 = 0V Parameter Normal mode consumption current (Note 10-1) (Note 10-2) IDDOP(2) Symbol IDDOP(1) Pin/ Remarks VDD1, VDD2 Conditions VDD[V] • FmCF=20MHz ceramic oscillation mode • System clock set to 20MHz side • All internal RC oscillation stopped. • 1/1 frequency division ratio • FmCF=4MHz ceramic oscillation mode • System clock set to 4MHz side • All internal RC oscillation stopped. • 1/1 frequency division ratio IDDOP(3) • FsX’tal=32.768kHz crystal oscillation mode • Internal medium speed RC oscillation stopped. • System clock set to internal high speed RC oscillation (20MHz). • 1/1 frequency division ratio IDDOP(4) • FsX’tal=32.768kHz crystal oscillation mode • Internal high speed RC oscillation stopped. • System clock set to internal medium speed RC oscillation. • 1/2 frequency division ratio IDDOP(5) • FsX’tal=32.768kHz crystal oscillation mode • System clock set to 32.768kHz crystal oscillation. • All internal RC oscillation stopped. • 1/1 frequency division ratio HALT mode consumption current (Note 10-1) (Note 10-2) IDDHALT(2) IDDHALT(1) VDD1, VDD2 • HALT mode • FmCF=20MHz ceramic oscillation mode • System clock set to 20MHz side • All internal RC oscillation stopped. • 1/1 frequency division ratio • HALT mode • FmCF=4MHz ceramic oscillation mode • System clock set to 4MHz side • All internal RC oscillation stopped. • 1/1 frequency division ratio IDDHALT(3) • HALT mode • FsX’tal=32.768kHz crystal oscillation mode • Internal medium speed RC oscillation stopped. • System clock set to internal high speed RC oscillation (20MHz). • 1/1 frequency division ratio IDDHALT(4) • HALT mode • FsX’tal=32.768kHz crystal oscillation mode • Internal high speed RC oscillation stopped. • System clock set to internal medium speed RC oscillation. • 1/2 frequency division ratio IDDHALT(5) • HALT mode • FsX’tal=32.768kHz crystal oscillation mode • System clock set to 32.768kHz crystal oscillation. • All internal RC oscillation stopped. • 1/1 frequency division ratio 3.3 to 5.5 16 60 μA 3.3 to 5.5 0.3 0.45 3.3 to 5.5 4 5 mA 3.3 to 5.5 1.5 2.3 3.3 to 5.5 4.7 5.8 3.3 to 5.5 32 74 μA 3.3 to 5.5 0.5 0.7 3.3 to 5.5 9.2 11 mA 3.3 to 5.5 3 4.1 3.3 to 5.5 10 12.5 min Specification typ max unit Note10-1: Values of the consumption current do not include current that flows into the output transistors and internal pull-up resistors. Note10-2: The consumption current values do not include operational current of LVD function if not specified. Continued on next page. No.A1828-19/25 LC87F0808A Continued from preceding page. Parameter HOLD mode consumption current (Note 10-1) (Note 10-2) (Note 10-3) IDDHOLD(2) Symbol IDDHOLD(1) Pin/ Remarks VDD1, VDD2 HOLD mode • CF1=VDD or open (External clock mode) HOLD mode • CF1=VDD or open (External clock mode) • LVD option selected 3.3 to 5.5 3 35 μA 3.3 to 5.5 0.03 32 Conditions VDD[V] min Specification typ max unit Note10-1: Values of the consumption current do not include current that flows into the output transistors and internal pull-up resistors. Note10-2: The consumption current values do not include operational current of LVD function if not specified. Note10-3: The amplifier / comparator circuit operates in the HOLD mode. F-ROM Programming Characteristics at Ta = -40°C to +85°C, VSS1 = VSS2 = 0V Parameter Onboard programming current Programming time tFW(1) tFW(2) • Erasing time • Programming time 3.3 to 5.5 20 40 30 60 ms μs Symbol IDDFW(1) Pin/Remarks VDD1, VDD2 Conditions VDD[V] • Only current of the flash block. 3.3 to 5.5 5 10 mA min Specification typ max unit UART (Full Duplex) Operating Conditions at Ta = -40°C to +85°C, VSS1 = VSS2 = 0V Parameter Transfer rate Symbol UBR Pin/Remarks UTX(P16) URX(P17) Conditions VDD[V] 3.3 to 5.5 min 16/3 Specification typ max 8192/3 unit tCYC Data length Stop bits Parity bits : 7/8/9 bits (LSB first) : 1 bit (2-bit in continuous data transmission) : None Example of Continuous 8-bit Data Transmission Mode Processing (First Transmit Data=55H) Start bit Stop bit Transmit data (LSB first) End of transmission Start of transmission UBR Example of Continuous 8-bit Data Reception Mode Processing (First Receive Data=55H) Start bit Start of reception Receive data (LSB first) Stop bit End of reception UBR No.A1828-20/25 LC87F0808A Characteristics of a Sample Main System Clock Oscillation Circuit Given below are the characteristics of a sample main system clock oscillation circuit that are measured using a SANYO-designated oscillation characteristics evaluation board and external components with circuit constant values with which the oscillator vendor confirmed normal and stable oscillation. Table 1 Characteristics of a Sample Main System Clock Oscillator Circuit with a Ceramic Oscillator MURATA Nominal Frequency Circuit Constant Type Oscillator Name C1 [pF] 20MHz SMD LEAD 10MHz SMD LEAD 4MHz SMD LEAD CSTCE20M0G51-R0 CSTLS20M0G52-B0 CSTCE10M0G52-R0 CSTLS10M0G53-B0 CSTCR4M00G53-R0 CSTLS4M00G53-B0 (5) (5) (10) (15) (15) (15) C2 [pF] (5) (5) (10) (15) (15) (15) Rf [Ω] Open Open Open Open Open Open Rd [Ω] 470 330 470 680 1.5k 1.5k Operating Voltage Range [V] 3.3 to 5.5 3.3 to 5.5 3.3 to 5.5 3.3 to 5.5 3.3 to 5.5 3.3 to 5.5 Oscillation Stabilization Time typ [ms] 0.02 0.06 0.02 0.02 0.04 0.03 Internal C1,C2 max [ms] Remarks The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized after VDD goes above the operating voltage lower limit (see Figure 3). Characteristics of a Sample Subsystem Clock Oscillator Circuit Given below are the characteristics of a sample subsystem clock oscillation circuit that are measured using a SANYOdesignated oscillation characteristics evaluation board and external components with circuit constant values with which the oscillator vendor confirmed normal and stable oscillation. Table 2 Characteristics of a Sample Subsystem Clock Oscillator Circuit with a Crystal Oscillator EPSON TOYOCOM Nominal Frequency Type Oscillator Name C1 [pF] 32.768kHz SMD MC-306 8 Circuit Constant C2 [pF] 8 Rf [Ω] Open Rd [Ω] 330k Operating Voltage Range [V] Oscillation Stabilization Time typ [s] 1.0 max [s] Applicable 3.3 to 5.5 4.0 CL value = 7.0pF Remarks The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized after the instruction for starting the subclock oscillation circuit is executed and to the time interval that is required for the oscillation to get stabilized after the HOLD mode is reset (see Figure 3). Note: The components that are involved in oscillation should be placed as close to the IC and to one another as possible because they are vulnerable to the influences of the circuit pattern. CF1/XT1 Rf CF2/XT2 Rd C1 CF/X’tal C2 0.5VDD Figure 1 CF and XT Oscillator Circuit Figure 2 AC Timing Measurement Point No.A1828-21/25 LC87F0808A Power supply Reset time RES VDD Operating VDD lower limit 0V Internal medium speed RC oscillation tmsCF/tmsX’tal CF1, CF2 Operating mode Unpredictable Reset Instruction execution Reset Time and Oscillation Stabilization Time HOLD reset signal HOLD reset signal absent HOLD reset signal valid Internal medium speed RC oscillation or low speed RC oscillation tmsCF/tmsX’tal CF1, CF2 (Note) State HOLD HALT HOLD Reset Signal and Oscillation Stabilization Time Note: External oscillation circuit is selected. Figure 3 Oscillation Stabilization Times No.A1828-22/25 LC87F0808A VDD RRES RES CRES Note: External circuits for reset may vary depending on the usage of POR and LVD. Please refer to the user’s manual for more information. Figure 4 Reset Circuit SIOCLK: DATAIN: DI0 DI1 DI2 DI3 DI4 DI5 DI6 DI7 DATAOUT: DO0 DO1 DO2 DO3 DO4 DO5 DO6 DO7 tSCK tSCKL SIOCLK: tsDI DATAIN: tdDO DATAOUT: thDI tSCKH Figure 5 Serial I/O Output Waveforms tPIL tPIH Figure 6 Pulse Input Timing Signal Waveform No.A1828-23/25 LC87F0808A POR release voltage (PORRL) (a) (b) VDD Reset period Unknown-state (POUKS) RES 100μs or longer Reset period Figure 7 Waveform observed when only POR is used (LVD not used) (RESET pin: Pull-up resistor RRES only) • The POR function generates a reset only when power is turned on starting at the VSS level. • No stable reset will be generated if power is turned on again when the power level does not go down to the VSS level as shown in (a). If such a case is anticipated, use the LVD function together with the POR function or implement an external reset circuit. • A reset is generated only when the power level goes down to the VSS level as shown in (b) and power is turned on again after this condition continues for 100μs or longer. LVD hysteresis width (LVHYS) LVD release voltage (LVDET+LVHYS) VDD LVD reset voltage (LVDET) Reset period Unknown-state (LVUKS) RES Reset period Reset period Figure 8 Waveform observed when both POR and LVD functions are used (RESET pin: Pull-up resistor RRES only) • Resets are generated both when power is turned on and when the power level lowers. • A hysteresis width (LVHYS) is provided to prevent the repetitions of reset release and entry cycles near the detection level. No.A1828-24/25 LC87F0808A VDD LVD release voltage LVD reset voltage TLVDW LVDET-0.5V VSS Figure 9 Low voltage detection minimum width (Example of momentary power loss/Voltage variation waveform) SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein. SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO Semiconductor Co.,Ltd. products described or contained herein are controlled under any of applicable local export control laws and regulations, such products may require the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written consent of SANYO Semiconductor Co.,Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO Semiconductor Co.,Ltd. product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. Upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third party. SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's intellectual property rights which has resulted from the use of the technical information and products mentioned above. This catalog provides information as of August, 2010. Specifications and information herein are subject to change without notice. PS No.A1828-25/25