LC87F1364A

Ordering number : ENA0137 LC87F1364A Overview CMOS IC FROM 64K byte, RAM 1K byte on-chip 8-bit 1-chip Microcontroller with Low-speed USB The SANYO LC87F1364A is an 8-bit microcomputer that, centered around a CPU running at a minimum bus cycle time of 166ns, integrates on a single chip a number of hardware features such as 64K-byte flash ROM (onboard programmable), 1024-byte RAM, an on-chip debugger, a sophisticated 16-bit timers/counters (may be divided into 8-bit timers), 16-bit timers (may be divided into 8-bit timers or 8-bit PWMs), four 8-bit timers with a prescaler, a base timer serving as a time-of-day clock, a high-speed clock counter, a synchronous SIO interface (with automatic block transmit/ receive function), an asynchronous/synchronous SIO interface, a UART interface (full duplex), a USB (Low-Speed) interface, two 12-bit PWM channels, an 8-bit 9-channel AD converter, and a 29-source 10-vector address interrupt feature. Features Flash ROM • Block-erasable in 128-byte units • 65536 × 8 bits Minimum Bus Cycle Time • 166ns (CF = 6MHz) Note: The bus cycle time here refers to the ROM read speed. Minimum Instruction Cycle Time (tCYC) • 500ns (CF = 6MHz) * This product is licensed from Silicon Storage Technology, Inc. (USA), and manufactured and sold by SANYO Semiconductor Co., Ltd. Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment (home appliances, AV equipment, communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee thereof. If you should intend to use our products for applications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our customer shall be solely responsible for the use. Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer' s products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer' s products or equipment. Ver.1.07 80807HKIM 20060405-S00011 No.A0137-1/22 LC87F1364A Ports • I/O ports Ports whose I/O direction can be designated in 1 bit units Ports whose I/O direction can be designated in 4 bit units • USB ports • Dedicated oscillator ports • Reset pins • Power pins 9 (P1n, P70) 8 (P0n) 2 (D+, D-) 2 (XT1, XT2) 1 (RES) 1 (VSS1, VDD1) Timers • Timer 0: 16-bit timer/counter with a capture register. Mode 0: 8-bit timer with an 8-bit programmable prescaler (with an 8-bit capture registers) × 2 channels Mode 1: 8-bit timer with an 8-bit programmable prescaler (with an 8-bit capture registers) + 8-bit counter (with an 8-bit capture register) Mode 2: 16-bit timer with an 8-bit programmable prescaler (with a 16-bit capture register) Mode 3: 16-bit counter (with a 16-bit capture register) • Timer 1: 16-bit timer that supports PWM/toggle output capabilities) Mode 0: 8-bit timer with an 8-bit prescaler (with toggle outputs) × 2 channels Mode 1: 8-bit PWM with an 8-bit prescaler × 2 channels Mode 2: 16-bit timer with an 8-bit prescaler (with toggle output) (The lower-order 8 bits can be used as a timer with toggle output.) Mode 3: 16-bit timer with an 8-bit prescaler (with toggle output) (The lower-order 8 bits can be used as PWM.) • Base timer 1) The clock is selectable from the subclock (32.768kHz crystal oscillation), system clock, and timer 0 prescaler output. 2) Interrupts programmable in 5 different time schemes • Timer 4: 8-bit timer with a 6-bit prescaler • Timer 5: 8-bit timer with a 6-bit prescaler • Timer 6: 8-bit timer with a 6-bit prescaler • Timer 7: 8-bit timer with a 6-bit prescaler SIO • SIO0: Synchronous serial interface 1) LSB first/MSB first mode selectable 2) Built-in 8-bit baudrate generator (maximum transfer clock cycle = 4/3tCYC) 3) Automatic continuous data transmission (1 to 256 bits) • SIO1: 8-bit asynchronous/synchronous serial interface Mode 0: Synchronous 8-bit serial I/O (2- or 3-wire configuration, 2 to 512 tCYC transfer clocks) Mode 1: Asynchronous serial I/O (half-duplex, 8 data bits, 1 stop bit, 8 to 2048 tCYC baudrates) Mode 2: Bus mode 1 (start bit, 8 data bits, 2 to 512 tCYC transfer clocks) Mode 3: Bus mode 2 (start detect, 8 data bits, stop detect) Full Duplex UART • UART1 1) Data length: 7/8/9 bits selectable 2) Stop bits: 1 bit (2 bits in continuous transmission mode) 3) Baud rate: 16/3 to 8192/3 tCYC AD Converter: 8 bits × 9 channels PWM: Multifrequency 12-bit PWM × 2 channels No.A0137-2/22 LC87F1364A USB Controller • USB Specification rev. 1.1 (Low-Speed) compatible • Supports a maximum of 2 user-defined endpoints. Endpoint Transfer Type Max. payload Control Interrupt EP0 enable 8 EP1 enable enable 8 EP2 enable 8 Watchdog Timer • External RC watchdog timer • Interrupt and reset signals selectable Interrupts • 29 sources, 10 vector addresses 1) Provides three levels (low (L), high (H), and highest (X)) of multiplex interrupt control. Any interrupt requests of the level equal to or lower than the current interrupt are not accepted. 2) When interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest level takes precedence over the other interrupts. For interrupts of the same level, the interrupt into the smallest vector address takes precedence. No. 1 2 3 4 5 6 7 8 9 10 Vector Address 00003H 0000BH 00013H 0001BH 00023H 0002BH 00033H 0003BH 00043H 0004BH Level X or L X or L H or L H or L H or L H or L H or L H or L H or L H or L INT0 INT1 INT2/T0L/USB bus active INT3/base timer T0H T1L/T1H SIO0/USB bus reset/USB suspend/UART1 receive SIO1/USBERR/USBPOV/USBENP/USBNAK/ USBSTL/UART1 transmit ADC/T6/T7 Port 0/PWM0/PWM1/T4/T5 Interrupt Source • Priority levels X > H > L • Of interrupts of the same level, the one with the smallest vector address takes precedence. Subroutine Stack Levels: 512 levels (the stack is allocated in RAM.) High-speed Multiplication/Division Instructions • 16 bits × 8 bits (5 tCYC execution time) • 24 bits × 16 bits (12 tCYC execution time) • 16 bits ÷ 8 bits (8 tCYC execution time) • 24 bits ÷ 16 bits (12 tCYC execution time) Oscillation Circuits • RC oscillation circuit (internal): • CF oscillation circuit: • Crystal oscillation circuit: • PLL circuit (internal): For system clock For system clock, USB interface For system clock, time-of-day clock For system clock, USB interface No.A0137-3/22 LC87F1364A Standby Function • HALT mode: Halts instruction execution while allowing the peripheral circuits to continue operation. 1) Oscillation is not halted automatically. 2) Canceled by a system reset or occurrence of an interrupt. • HOLD mode: Suspends instruction execution and the operation of the peripheral circuits. 1) The PLL base clock generator, CF, RC and crystal oscillators automatically stop operation. 2) There are four ways of resetting the HOLD mode. (1) Setting the reset pin to the lower level. (2) Setting at least one of the INT0, INT1, and INT2 pins to the specified level (3) Having an interrupt source established at port 0 (4) Having an bus active interrupt source established in the USB interface circuit • X'tal HOLD mode: Suspends instruction execution and the operation of the peripheral circuits except the base timer. 1) The PLL base clock generator, CF and RC oscillator automatically stop operation. 2) The state of crystal oscillation established when the X'tal HOLD mode is entered is retained. 3) There are five ways of resetting the X'tal HOLD mode. (1) Setting the reset pin to the low level (2) Setting at least one of the INT0, INT1, and INT2 pins to the specified level (3) Having an interrupt source established at port 0 (4) Having an interrupt source established in the base timer circuit (5) Having an bus active interrupt source established in the USB interface circuit Package Form • MFP24S(300mil): Lead-free type Development Tools • On-chip debugger: TCB87 type-A or TCB87 type-B + LC87F1364A Flash ROM Programming Boards Package MFP24S(300mil) Programming boards W87F5300M Recommended EPROM Programmer Maker Flash Support Group, Inc. (Single) SANYO Model AF9708/AF9709/AF9709B (including product of Ando Electric Co.,Ltd) SKK(SANYO FWS) Supported version After 02.40 Application Version: After 1.03 Chip Data Version: After 2.01 Device LC87F1364A LC87F1364 No.A0137-4/22 LC87F1364A Package Dimensions unit : mm (typ) 3112B 12.5 24 13 5.4 7.6 1 1.0 (0.75) 0.35 12 0.15 SANYO : MFP24S(300mil) Pin Assignment P05/AN5/CKO P06/AN6/T6O P07/AN7/T7O P70/INT0/T0LCP/AN8/DPUP D+ DRES P17/FILT VSS1 XT1/CF1 XT2/CF2 VDD1 0.1 (1.5) 1.7max 0.63 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 P04/AN4/DBGP2 P03/AN3/DBGP1 P02/AN2/DBGP0 P01/AN1/URX1 P00/AN0/UTX1 P16/PWM1 P15/SCK1/INT3/T0IN/PWM0 P14/SI1/SB1/INT2/T0IN P13/SO1/INT1/T0HCP P12/SCK0 P11/SI0/SB0 P10/SO0 MFP24S 19 18 17 16 15 14 13 Top view No.A0137-5/22 LC87F1364A MFP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 NAME P05/AN5/CKO P06/AN6/T6O P07/AN7/T7O P70/INT0/T0LCP/AN8/DPUP D+ DRES P17/FILT VSS1 XT1/CF1 XT2/CF2 VDD1 P10/SO0 P11/SI0/SB0 P12/SCK0 P13/SO1/INT1/T0HCP P14/SI1/SB1/INT2/T0IN P15/SCK1/INT3/T0IN/PWM0 P16/PWM1 P00/AN0/UTX1 P01/AN1/URX1 P02/AN2/DBGP0 P03/AN3/DBGP1 P04/AN4/DBGP2 No.A0137-6/22 LC87F1364A System Block Diagram Interrupt control IR PLA Standby control RC PLL CF/X’tal Clock generator Flash-ROM PC SIO0 SIO1 Bus interface Port 0 Port 1 Port 7 ACC B register Timer 0 Timer 1 Timer 4 Timer 5 Timer 6 Timer 7 C register ALU INT0 to 3 Noise rejection filter UART1 PSW ADC RAR RAM Base timer Stack pointer PWM0 Watchdog timer PWM1 USB interface On-Chip-Debugger No.A0137-7/22 LC87F1364A Pin Description Pin Name VSS1 VDD1 Port 0 P00 to P07 I/O I/O - power supply pin + power supply pin • 8-bit I/O port • I/O specifiable in 4 bit units • Pull-up resistors can be turned on and off in 4 bit units. • HOLD reset input • Port 0 interrupt input • Pin functions P00: AN0 (ADC input)/UART1 transmit P01: AN1 (ADC input)/UART1 receive P02: AN2 (ADC input)/For On-Chip-Debugger P03: AN3 (ADC input)/For On-Chip-Debugger P04: AN4 (ADC input)/For On-Chip-Debugger P05: AN5 (ADC input)/System Clock Output P06: AN6 (ADC input)/timer 6 toggle outputs P07: AN7 (ADC input)/timer 7 toggle outputs Port 1 P10 to P17 I/O • 8-bit I/O port • I/O specifiable in 1 bit units • Pull-up resistors can be turned on and off in 1 bit units. • Pin functions P10: SIO0 data output P11: SIO0 data input/bus I/O P12: SIO0 clock I/O P13: SIO1 data output/INT1 input/HOLD reset input/timer OH capture input P14: SIO1 data input/bus I/O/INT2 input/ HOLD reset input/timer 0 event input/timer OL capture input P15: SIO1 clock I/O/INT3 input (with noise filter)/timer 0 event input/timer OH capture input /PWM 0 output P16: Timer 1 PWML output/PWM 1 output P17: Timer 1 PWMH output/beeper output/Internal PLL filter pin Interrupt acknowledge type Rising INT1 INT2 INT3 Port 7 P70 I/O • 1-bit I/O port • I/O specifiable in 1 bit units • Pull-up resistors can be turned on and off in 1 bit units. • Shared pins P70: INT0 input/HOLD reset input/timer 0L capture input/watchdog timer output/AN8 (ADC input) / D- 1.5kΩ pull-up resistor connect pin Interrupt acknowledge type Rising INT0 enable Falling enable Rising & Falling disable H level enable L level enable enable enable enable Falling enable enable enable Rising & Falling disable enable enable H level enable disable disable L level enable disable disable No Yes Description Option No No Yes RES XT1 XT2 DD+ I I I/O I/O I/O Reset pin Ceramic oscillator input pin/32.768kHz crystal oscillator input pin Ceramic oscillator input pin/32.768kHz crystal oscillator output pin USB data I/O pin DUSB data I/O pin D+ No No No No No No.A0137-8/22 LC87F1364A Port Output Types The table below lists the types of port outputs and the presence/absence of a pull-up resistor. Data can be read into any input port even if it is in the output mode. Port Name P00 to P07 Option selected in units of 1 bit Option type 1 2 P10 to P17 1 bit 1 2 P70 XT1 XT2 No No No CMOS Nch-open drain CMOS Nch-open drain Nch-open drain Input only 32.768kHz crystal oscillator output Output type Pull-up resistor Programmable (Note 1) No Programmable Programmable Programmable No No Note 1: Programmable pull-up resistors for port 0 are controlled in 4 bit units (P00 to 03, P04 to 07). USB Reference Power Option When a voltage 4.5V to 5.5V is supplied to VDD1 and the internal USB reference voltage circuit is activated, the H output level of the USB Port is 3.0V to 3.6V (the H output level of the ports except the USB Port is the VDD1 voltage level, however). The active/inactive state of the reference voltage circuit can be determined by option settings. According to the voltage to be supplied to VDD1, make option settings as shown below. Option setting VDD1 voltage (V) USB Regulator USB Regulator in HOLD mode USB Regulator in HALT mode Reference voltage circuit state Normal state HOLD mode HALT mode 4.5 to 5.5 USE USE USE active active active (1) USE NONUSE NONUSE active inactive inactive (2) USE NONUSE USE active inactive active (3) 3.0 to 3.6 NONUSE NONUSE NONUSE inactive inactive inactive (4) • When the USB reference voltage circuit is made inactive, the H output level of the USB Port becomes the VDD1 voltage level. • Use the setting (2) or (3) to make the reference voltage circuit inactive in HOLD or HALT mode. • When the reference voltage circuit is activated, the current drain increases by approximately 100µA compared with when the reference voltage circuit is inactive. No.A0137-9/22 LC87F1364A Absolute Maximum Ratings at Ta = 25°C, VSS1 = 0V Parameter Maximum supply voltage Input voltage Input/output voltage Peak output current High level output current IOPH(2) Average output current (Note 2) IOMH(2) Total output current Peak output Low level output current current IOPL(2) Average output current (Note 2) IOML(2) Total output current Allowable power Dissipation Operating ambient Temperature Storage ambient temperature Tstg Topr -20 -55 +70 °C +125 Pd max ΣIOAL(1) IOML(1) IOPL(1) ΣIOAH(1) PWM0, PWM1 Ports 0, 1 PWM0, PWM1 D+, DP00 to P05 Ports 1, P70 PWM0, PWM1 P06, 07 P00 to P05 Ports 1, P70 PWM0, PWM1 P06, 07 Ports 0, 1, P70 PWM0, PWM1 D+, DMFP24S Ta=-20 to +70°C Per 1 applicable pin Total of all applicable pins 20 75 mW Per 1 applicable pin Per 1 applicable pin 15 30 Per 1 applicable pin 20 IOMH(1) PWM0, PWM1 Ports 0, 1 IOPH(1) Ports 0, 1 • When CMOS output type is selected • Per 1 applicable pin Per 1 applicable pin • When CMOS output type is selected • Per 1 applicable pin Per 1 applicable pin Total of all applicable pins -50 mA -15 -7.5 -20 -10 VI(1) VIO(1) XT1, XT2 Ports 0, 1, 7 Symbol VDD max Pin/Remarks VDD1 VDD1 Conditions VDD[V] min -0.3 -0.3 -0.3 Specification typ max +6.5 VDD+0.3 VDD+0.3 V unit Note 2: The mean output current is a mean value measured over 100ms. No.A0137-10/22 LC87F1364A Allowable Operating Conditions at Ta = -20°C to +70°C, VSS1 = 0V Parameter Operating supply voltage VDD(2) Memory sustaining supply voltage High level input voltage VIH(2) VIH(3) Low level input voltage VIL(1) VIH(1) Port 1 P70 port input /interrupt side Port 70 watchdog timer side XT1, XT2, RES Port 1 P70 port input /interrupt side VIL(2) Port 0 2.5 to 5.5 2.5 to 5.5 4.0 to 5.5 2.5 to 4.0 4.0 to 5.5 2.5 to 4.0 VIL(3) VIL(4) Instruction cycle time (Note 4) External system clock frequency FEXCF(1) XT1 • XT2 pin open • System clock frequency division ratio=1/1 • External system clock duty =50±5% • XT2 pin open • System clock frequency division ratio=1/2 Oscillation frequency range (Note 5) FmRC FsX’tal XT1, XT2 FmCF XT1, XT2 6MHz ceramic oscillation See Fig. 1. Internal RC oscillation 32.768kHz crystal oscillation See Fig. 2. 2.5 to 5.5 2.5 to 5.5 2.5 to 5.5 0.3 6 1.0 32.768 2.0 kHz MHz 2.5 to 5.5 0.1 12 2.5 to 5.5 0.1 6 MHz tCYC 2.5 to 5.5 0.490 200 µs Port 70 watchdog timer side XT1, XT2, RES 2.5 to 5.5 2.5 to 5.5 2.5 to 5.5 0.3VDD +0.7 0.9VDD 0.75VDD VSS VSS VSS VSS VSS VSS VDD V VDD 0.1VDD +0.4 0.2VDD 0.15VDD +0.4 0.2VDD 0.8VDD -1.0 0.25VDD VDD VHD VDD1 Symbol VDD(1) Pin/Remarks VDD1 Conditions VDD[V] 0.490µs ≤ tCYC ≤ 200µs Except for onboard programming (Note 3) 0.490µs ≤ tCYC ≤ 200µs internal PLL oscillation RAM and register contents sustained in HOLD mode. 2.0 5.5 min 2.5 4.5 Specification typ max 5.5 5.5 unit Note 3: VDD must be held greater than or equal to 3.0V in the flash ROM onboard programming mode. Note 4: Relationship between tCYC and oscillation frequency is 3/FmCF at a division ratio of 1/1 and 6/FmCF at a division ratio of 1/2. Note 5: See Tables 1 and 2 for the oscillation constants. No.A0137-11/22 LC87F1364A Electrical Characteristics at Ta = -20°C to +70°C, VSS1 = 0V Parameter High level input current Symbol IIH(1) Pin/Remarks Ports 0, 1 Port 70 RES IIH(2) Low level input current IIL(1) XT1, XT2 Ports 0, 1 Port 70 RES IIL(2) High level output voltage VOH(1) VOH(2) VOH(3) VOH(4) VOH(5) VOH(6) PWM0, PWM1 P05 (CK0 when using system clock output function) Low level output voltage VOL(1) VOL(2) VOL(3) VOL(4) VOL(5) VOL(6) Pull-up resistance Rpu(1) Rpu(2) Hysteresis voltage VHYS Ports 0, 1 Port 70 RES Port 1 Port 70 Pin capacitance CP All pins For pins other than that under test: VIN=VSS F=1MHz Ta=25°C 2.5 to 5.5 10 pF Ports 0, 1 Port 70 PWM0, PWM1 P06, P07 IOL=10mA IOL=1.6mA IOL=1mA IOL=30mA IOL=5mA IOL=2.5mA VOH=0.9VDD 4.5 to 5.5 3.0 to 5.5 2.5 to 5.5 4.5 to 5.5 3.0 to 5.5 2.5 to 5.5 4.5 to 5.5 2.5 to 5.5 2.5 to 5.5 15 18 35 50 0.1VDD 1.5 0.4 0.4 1.5 0.4 0.4 80 150 kΩ XT1, XT2 Ports 0, 1 Conditions VDD[V] Output disabled Pull-up resistor off VIN=VDD (Including output Tr's off leakage current) VIN=VDD Output disabled Pull-up resistor off VIN=VSS (Including output Tr's off leakage current) VIN=VSS IOH=-1mA IOH=-0.4mA IOH=-0.2mA IOH=-10mA IOH=-1.6mA IOH=-1mA 2.5 to 5.5 VDD-0.4 V 2.5 to 5.5 4.5 to 5.5 3.0 to 5.5 2.5 to 5.5 4.5 to 5.5 3.0 to 5.5 -1 VDD-1 VDD-0.4 VDD-0.4 VDD-1.5 VDD-0.4 2.5 to 5.5 -1 2.5 to 5.5 1 µA 2.5 to 5.5 1 min Specification typ max unit V No.A0137-12/22 LC87F1364A Serial I/O Characteristics at Ta = -20°C to +70°C, VSS1 = 0V 1. SIO0 Serial I/O Characteristics (Note 4-1-1) Parameter Frequency Low level pulse width High level pulse width Input clock tSCKHA(1a) • Continuous data transmission/reception mode • USB is not in use simultaneous. • See Fig. 6. • (Note 4-1-2) tSCKHA(1b) • Continuous data transmission /reception mode • USB is in use simultaneous. Serial clock • See Fig.6. • (Note 4-1-2) Frequency Low level pulse width High level pulse width Output clock tSCKHA(2a) • Continuous data transmission /reception mode • USB is not in use simultaneous. • CMOS output selected • See Fig.6. tSCKHA(2b) • Continuous data transmission /reception mode • USB is in use simultaneous. • CMOS output selected • See Fig.6. Data setup time Serial input tsDI(1) SB0(P11), SI0(P11) • Must be specified with respect to rising edge of SIOCLK. • See Fig.6. Data hold time thDI(1) 2.7 to 5.5 Output delay Input clock time tdD0(2) tdD0(3) tdD0(1) SO0(P10), SB0(P11) • Continuous data transmission /reception mode • (Note 4-1-3) • Synchronous 8-bit mode • (Note 4-1-3) Output clock (Note 4-1-3) 2.7 to 5.5 (1/3)tCYC +0.05 2.7 to 5.5 2.7 to 5.5 0.03 2.7 to 5.5 0.03 tSCKH(2) +2tCYC tSCKH(2) +(19/3) tCYC 2.7 to 5.5 tSCKH(2) +2tCYC tSCKH(2) +(10/3) tCYC tCYC tSCKH(2) tSCK(2) tSCKL(2) SCK0(P12) • CMOS output selected • See Fig.6. 4/3 1/2 tSCK 1/2 7 2.7 to 5.5 4 tSCKH(1) Symbol tSCK(1) tSCKL(1) Pin /Remarks SCK0(P12) See Fig. 6. Conditions VDD[V] min 2 1 1 Specification typ max unit tCYC (1/3)tCYC +0.05 1tCYC +0.05 µs Note 4-1-1: These specifications are theoretical values. Add margin depending on its use. Note 4-1-2: To use serial-clock-input in continuous trans/rec mode, a time from SI0RUN being set when serial clock is "H" to the first negative edge of the serial clock must be longer than tSCKHA. Note 4-1-3: Must be specified with respect to falling edge of SIOCLK. Must be specified as the time to the beginning of output state change in open drain output mode. See Fig.6. Serial output No.A0137-13/22 LC87F1364A 2. SIO1 Serial I/O Characteristics (Note 4-2-1) Parameter Frequency Input clock Low level pulse width High level pulse width Frequency Output clock Low level pulse width High level pulse width Data setup time Serial input tsDI(2) SB1(P14), SI1(P14) Data hold time thDI(2) 2.7 to 5.5 Output delay time Serial output tdD0(4) SO1(P13), SB1(P14) • Must be specified with respect to falling edge of SIOCLK. • Must be specified as the time to the beginning of output state change in open drain output mode. • See Fig.6. 2.7 to 5.5 (1/3)tCYC +0.05 0.03 µs • Must be specified with respect to rising edge of SIOCLK. • See Fig.6. 2.7 to 5.5 0.03 tSCKH(4) 1/2 tSCK(4) tSCKL(4) 2.7 to 5.5 SCK1(P15) • CMOS output selected • See Fig.6. tSCKH(3) Symbol tSCK(3) tSCKL(3) Pin /Remarks SCK1(P15) CondiPtions VDD[V] See Fig.6. min 2 2.7 to 5.5 1 tCYC 1 2 1/2 tSCK Specification typ max unit Note 4-2-1: These specifications are theoretical values. Add margin depending on its use. Serial clock No.A0137-14/22 LC87F1364A Pulse Input Conditions at Ta = -20°C to +70°C, VSS1 = 0V Parameter High/low level pulse width Symbol tP1H(1) tP1L(1) tPIH(2) tPIL(2) tPIH(3) tPIL(3) tPIH(4) tPIL(4) tPIL(5) Pin/Remarks INT0(P70), INT1(P13), INT2(P14), INT3(P15) when noise filter time constant is 1/1 INT3(P15) when noise filter time constant is 1/32 INT3(P15) when noise filter time constant is 1/128 RES Conditions VDD[V] • Interrupt source flag can be set. • Event inputs for timer 0 or 1 are enabled. • Interrupt source flag can be set. • Event inputs for timer 0 are enabled. • Interrupt source flag can be set. • Event inputs for timer 0 are enabled. • Interrupt source flag can be set. • Event inputs for timer 0 are enabled. Resetting is enabled. 2.5 to 5.5 200 µs 2.5 to 5.5 256 2.5 to 5.5 64 2.5 to 5.5 2 tCYC 2.5 to 5.5 1 min Specification typ max unit AD Converter Characteristics at Ta = -20°C to +70°C, VSS1 = 0V Parameter Resolution Absolute accuracy Conversion time TCAD Symbol N ET Pin/Remarks AN0(P00) to AN7(P07), AN8(P70) AD conversion time = 32×tCYC (when ADCR2=0) (Note 7) 4.5 to 5.5 (Note 6) Conditions VDD[V] 3.0 to 5.5 3.0 to 5.5 15.68 (tCYC= 0.49µs) 31.36 3.0 to 5.5 AD conversion time = 64×tCYC (when ADCR2=1) (Note 7) 4.5 to 5.5 (tCYC= 0.98µs) 31.36 (tCYC= 0. 49µs) 31.36 3.0 to 5.5 Analog input voltage range Analog port input current IAINH IAINL VAIN=VDD VAIN=VSS VAIN (tCYC= 0. 49µs) 3.0 to 5.5 3.0 to 5.5 3.0 to 5.5 -1 VSS min Specification typ 8 max unit bit ±1.5 97.92 (tCYC= 3.06µs) 97.92 (tCYC= 3.06µs) 97.92 (tCYC= 1.53µs) 97.92 (tCYC= 1.53µs) VDD 1 LSB µs V µA Note 6: The quantization error (±1/2LSB) is excluded from the absolute accuracy value. Note 7: The conversion time refers to the interval from the time the instruction for starting the converter is issued till the time the complete digital value corresponding to the analog input value is loaded in the required register. No.A0137-15/22 LC87F1364A Consumption Current Characteristics at Ta = -20°C to +70°C, VSS1 = 0V Parameter Normal mode consumption current (Note 8) IDDOP(3) IDDOP(2) Symbol IDDOP(1) Pin /Remarks VDD1 Conditions VDD[V] • FmCF=6MHz ceramic oscillation mode • System clock set to 6MHz side • Internal RC oscillation stopped • 1/1 frequency division ration • FsX’tal=32.768kHz crystal oscillation mode • System clock set to PLL clock side • Internal RC oscillation stopped • 1/1 frequency division ration IDDOP(4) IDDOP(5) IDDOP(6) • FsX’tal=32.768kHz crystal oscillation mode • System clock set to internal RC oscillation • Internal PLL oscillation stopped • 1/2 frequency division ration • FsX’tal=32.768kHz crystal oscillation mode • System clock set to 32.768kHz side IDDOP(7) • Internal RC oscillation stopped • Internal PLL oscillation stopped • 1/2 frequency division ration HALT mode consumption current (Note 8) IDDHALT(2) IDDHALT(1) • HALT mode • FmCF=6MHz ceramic scillation mode • System clock set to 6MHz side • Internal RC oscillation stopped • 1/1 frequency division ration IDDHALT(3) • HALT mode • FsX'tal=32.768kHz crystal oscillation mode • System clock set to PLL clock side • Internal RC oscillation stopped • 1/1 frequency division ration IDDHALT(4) • HALT mode • FsX'tal=32.768kHz crystal oscillation mode IDDHALT(5) • System clock set to internal RC oscillation • Internal PLL oscillation stopped • 1/2 frequency division ration IDDHALT(6) • HALT mode • FsX'tal=32.768kHz crystal oscillation mode • System clock set to 32.768kHz side IDDHALT(7) • Internal RC oscillation stopped • Internal PLL oscillation stopped • 1/2 frequency division ration HOLD mode consumption current Timer HOLD mode consumption current IDDHOLD(4) IDDHOLD(2) IDDHOLD(3) IDDHOLD(1) HOLD mode • XT1=VDD or open (External clock mode) 2.5 to 4.5 Timer HOLD mode • FsX’tal=32.768kHz crystal oscillation mode 4.5 to 5.5 2.5 to 4.5 0.02 27 9.6 9.8 120 66 4.5 to 5.5 0.04 13 µA 2.5 to 4.5 12 73 4.5 to 5.5 30 130 2.5 to 4.5 0.19 1.1 4.5 to 5.5 0.33 1.6 4.5 to 5.5 3.6 9.6 mA 2.5 to 4.5 1.2 3.6 4.5 to 5.5 2.0 5.4 2.5 to 4.5 79 290 4.5 to 5.5 120 380 µA 4.5 to 5.5 2.5 to 4.5 0.67 0.43 3.1 2.3 4.5 to 5.5 6.7 17 mA 4.5 to 5.5 2.5 to 4.5 min Specification typ 5.3 3.5 Max 13 9.6 unit Note 8: The consumption current value includes none of the currents that flow into the output Tr and internal pull-up resistors. No.A0137-16/22 LC87F1364A USB Characteristics and Timing at Ta = -20°C to +70°C, VSS1 = 0V Parameter High level output Low level output Output signal crossover voltage Differential input sensitivity Differential input common mode range High level input Low level input USB data rise time USB data fall time Rise/fall time Symbol VOH(USB) VOL VCRS VDI VCM VIH(USB) VIL(USB) tR tF tRFM • tR/tF 75 75 80 • ⏐(D+)-(D-)⏐ Conditions min • 15kΩ±5% to GND • 1.5kΩ±5% to 3.6V 1.3 0.2 0.8 2.0 0.8 300 300 125 2.5 2.8 Specification typ max 3.6 0.3 2.0 unit V V V V V V V ns ns % F-ROM Write Characteristics at Ta = +10°C to +55°C, VSS1 = 0V Parameter Onboard programming current Programming time tFW(1) • 128-byte programming • Erasing current included • Time for setting up 128-byte data excluded. 3.0 to 5.5 22.5 45 mS Symbol IDDFW(1) Pin VDD1 Conditions VDD[V] • 128-byte programming • Erasing current included 3.0 to 5.5 25 40 mA min Specification typ max unit No.A0137-17/22 LC87F1364A Characteristics of a Sample External Clock Oscillation Circuit Given below are the characteristics of a sample external clock oscillation circuit that are measured using a SANYOdesignated oscillation characteristics evaluation board and external components with circuit constant values with which the oscillator vendor confirmed normal and stable oscillation. Table 1 Characteristics of a Sample External Clock Oscillator Circuit with a Crystal Oscillator Nominal Frequency Vendor Name EPSON TOYOCOM Circuit Constant Oscillator Name C1 [pF] 32.768kHz MC-306 22 C2 [pF] 22 Rf1 [Ω] Open Rd1 [Ω] 820k Operating Voltage Range [V] 2.5 to 5.5 Oscillation Stabilization Time typ [s] 1.3 max [s] 3 Applicable CL value=12.5pF Remarks The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized after the instruction for starting the subclock oscillation circuit is executed and to the time interval that is required for the oscillation to get stabilized after the HOLD mode is reset (see Figure 4). Note: The components that are involved in oscillation should be placed as close to the IC and to one another as possible because they are vulnerable to the influences of the circuit pattern. XT1 Rf1 XT2 Rd1 C1 X’tal C2 Figure 1 Crystal Oscillation Circuit Table 2 Characteristics of a Sample External Clock Oscillator Circuit with a CF Oscillator Nominal Frequency 6MHz Vendor Name MURATA Circuit Constant Oscillator Name C3 [pF] CSTCR6M00G15***-R0 (39) C4 [pF] (39) Rf2 [Ω] Open Rd2 [Ω] 1k Operating Voltage Range [V] 2.5 to 5.5 Oscillation Stabilization Time typ [ms] 0.1 max [ms] 0.5 Built in C3, C4 Remarks The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized after VDD goes above the operating voltage lower limit (see Figure 4). XT1 XT2 Rf2 Rd2 C3 CF C4 Figure 2 CF Oscillation Circuit No.A0137-18/22 LC87F1364A 0.5VDD Figure 3 AC Timing Measurement Point VDD Operating VDD lower limit GND Reset time Power supply RES Internal RC oscillation tmsCF CF oscillation (XT1, XT2) tmsX’tal Crystal oscillation (XT1, XT2) State Unpredictable Reset Instruction execut Reset Time and Oscillation Stabilization Time HOLD reset signal HOLD reset signal absen HOLD reset signal valid Internal RC oscillation tmsCF CF oscillation (XT1, XT2) tmsX’tal Crystal Oscillation (XT1, XT2) State HOLD HALT HOLD Reset Signal and Oscillation Stabilization Time Figure 4 Oscillation Stabilization Times No.A0137-19/22 LC87F1364A P17/FILT 0Ω + 2.2µF When using the internal PLL circuit to generate the 6MHz clock for USB or system clock, it is necessary to connect a filter circuit such as that shown to the left to the P17/FILT pin.. Figure 5 Filter Circuit for the Internal PLL Circuit VDD RRES RES CRES Note: Determine the value of CRES and RRES so that the reset signal is present for a period of 200µs after the supply voltage goes beyond the lower limit of the IC's operating voltage. Figure 6 Reset Circuit No.A0137-20/22 LC87F1364A SIOCLK: DATAIN: DI0 DI1 DI2 DI3 DI4 DI5 DI6 DI7 DI8 DATAOUT: DO0 DO1 DO2 DO3 DO4 DO5 DO6 DO7 Data RAM transfer period (SIO0 only) DO8 tSCK tSCKL SIOCLK: tsDI DATAIN: tdDO DATAOUT: Data RAM transfer period (SIO0 only) tSCKLA SIOCLK: tsDI DATAIN: tdDO DATAOUT: thDI tSCKHA thDI tSCKH Figure 7 Serial Input/Output Waveforms tPIL tPIH Figure 8 Pulse Input Timing Signal Waveform Voh Vcrs D+ tr 90% 10% 90% tr 10% Vol D- Figure 9 USB Data Signal Timing and Voltage Level No.A0137-21/22 LC87F1364A SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein. SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO Semiconductor Co.,Ltd. products described or contained herein are controlled under any of applicable local export control laws and regulations, such products may require the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written consent of SANYO Semiconductor Co.,Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO Semiconductor Co.,Ltd. product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. Upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third party. SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's intellctual property rights which has resulted from the use of the technical information and products mentioned above. This catalog provides information as of July, 2006. Specifications and information herein are subject to change without notice. PS No.A0137-22/22