LC87F1G64A

Ordering number : ENA0477 LC87F1G64A Overview CMOS IC FROM 64K byte, RAM 3K byte on-chip 8-bit 1-chip Microcontroller with Full-Speed USB The SANYO LC87F1G64A is an 8-bit microcomputer that, centered around a CPU running at a minimum bus cycle time of 83.3ns, integrates on a single chip a number of hardware features such as 64K-byte flash ROM (onboard programmable), 3072-byte RAM, an on-chip debugger, a sophisticated 16-bit timers/counters (may be divided into 8-bit timers), 16-bit timers/counter (may be divided into 8-bit timers/counters or 8-bit PWMs), four 8-bit timers with a prescaler, a base timer serving as a time-of-day clock, two synchronous SIO interface (with automatic block transmit/ receive function), an asynchronous/synchronous SIO interface, a UART interface (full duplex), a Full-Speed USB interface (function controller), an 8-bit 12-channel AD converter, two 12-bit PWM channels, a system clock frequency divider, ROM correction function, and a 32-source 10-vector address interrupt feature. Features Flash ROM • Capable of on-board-programming with wide range, 3.0 to 5.5V, of voltage source. • Block-erasable in 128 byte units • 65536 × 8 bits RAM • 3072 × 9 bits Minimum Bus Cycle • 83.3ns (CF=12MHz) Note: The bus cycle time here refers to the ROM read speed. Minimum Instruction Cycle Time • 250ns (CF=12MHz) * This production is produced and sold by SANYO under license of the Silicon Storage Technology Inc. Specifications and information herein are subject to change without notice. Any and all SANYO Semiconductor products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft's control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO Semiconductor representative nearest you before using any SANYO Semiconductor products described or contained herein in such applications. SANYO Semiconductor assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor products described or contained herein. Ver.1.07 D0606HKIM 20061109-S00012 No.A0477-1/29 LC87F1G64A Ports • I/O ports Ports whose I/O direction can be designated in 1 bit units 28 (P10 to P17, P20 to P27, P30 to P34, P70 to P73, PWM0, PWM1, XT2) Ports whose I/O direction can be designated in 4 bit units 8 (P00 to P07) • USB ports 2 (D+, D-) • Dedicated oscillator ports 2 (CF1, CF2) • Input-only port (also used for oscillation) 1 (XT1) • Reset pins 1 (RES) • Power pins 6 (VSS1 to 3, VDD1 to 3) Timers • Timer 0: 16-bit timer/counter with two capture registers. Mode 0: 8-bit timer with an 8-bit programmable prescaler (with two 8-bit capture registers) × 2 channels Mode 1: 8-bit timer with an 8-bit programmable prescaler (with two 8-bit capture registers) + 8-bit counter (with two 8-bit capture registers) Mode 2: 16-bit timer with an 8-bit programmable prescaler (with two 16-bit capture registers) Mode 3: 16-bit counter (with two 16-bit capture registers) • Timer 1: 16-bit timer/counter that supports PWM/toggle outputs Mode 0: 8-bit timer with an 8-bit prescaler (with toggle outputs) + 8-bit timer/counter with an 8-bit prescaler (with toggle outputs) Mode 1: 8-bit PWM with an-8bit prescaler × 2 channels Mode 2: 16-bit timer/counter with an 8-bit prescaler (with toggle outputs) (toggle outputs also possible from the lower-order 8 bits) Mode 3: 16-bit timer with an 8-bit prescaler (with toggle outputs) (The lower-order 8 bits can be used as PWM.) • Timer 4: 8-bit timer with a 6-bit prescaler • Timer 5: 8-bit timer with a 6-bit prescaler • Timer 6: 8-bit timer with a 6-bit prescaler (with toggle output) • Timer 7: 8-bit timer with a 6-bit prescaler (with toggle output) • Base timer 1) The clock is selectable from the subclock (32.768kHz crystal oscillation), system clock, and timer 0 prescaler output. 2) Interrupts programmable in 5 different time schemes SIO • SIO0: Synchronous serial interface 1) LSB first/MSB first mode selectable 2) Transfer clock cycle: 4/3 to 512/3 tCYC 3) Automatic continuous data transmission (1 to 256 bits, specifiable in 1 bit units, suspension and resumption of data transmission possible in 1 byte units) • SIO1: 8-bit asynchronous/synchronous serial interface Mode 0: Synchronous 8-bit serial I/O (2- or 3-wire configuration, 2 to 512 tCYC transfer clocks) Mode 1: Asynchronous serial I/O (half-duplex, 8 data bits, 1 stop bit, 8 to 2048 tCYC baudrates) Mode 2: Bus mode 1 (start bit, 8 data bits, 2 to 512 tCYC transfer clocks) Mode 3: Bus mode 2 (start detect, 8 data bits, stop detect) • SIO4: Synchronous serial interface 1) LSB first/MSB first mode selectable 2) Transfer clock cycle: 4/3 to 1020/3 tCYC 3) Automatic continuous data transmission (1 to 3072 bytes, specifiable in 1 byte units, suspension and resumption of data transmission possible in 1 byte or 2 bytes units) 4) Auto-start-on-falling-edge function 5) Clock polarity selectable 6) CRC16 calculator circuit built in No.A0477-2/29 LC87F1G64A Full Duplex UART 1) Data length: 7/8/9 bits selectable 2) Stop bits: 1 bit (2 bits in continuous transmission mode) 3) Baud rate: 16/3 to 8192/3 tCYC AD Converter: 8 bits × 12 channels PWM: Multifrequency 12-bit PWM × 2 channels USB Interface (function controller) • Compliant with USB 2.0 Full-Speed • Supports a maximum of 8 user-defined endpoints. Endpoint Transfer Type Control Bulk Interrupt Isochronous Max. payload 64 64 64 64 64 1023 1023 64 64 EP0 EP1 EP2 EP3 EP4 EP5 EP6 EP7 EP8 - Audio Interface 1) Sampling frequency (fs): 32kHz, 44.1kHz, 48kHz 2) PLL clock frequency: 12.288MHz, 16.9344MHz, 18.432MHz 3) Supported master clocks Bit Clock Master Clock 384fs 48fs 192fs 96fs 384fs 64fs 256fs 128fs 4) Data lengths of 16, 18, 20, 24 bits selectable 5) LSB first/MSB first mode selectable 6) Left Justified/Right Justified selectable Watchdog Timer • External RC watchdog timer • Interrupt and reset signals selectable Clock Output Function 1) Able to output selected oscillation clock 1/1, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64 as system clock. 2) Able to output oscillation clock of sub clock. No.A0477-3/29 LC87F1G64A Interrupts • 32 sources, 10 vector addresses 1) Provides three levels (low (L), high (H), and highest (X)) of multiplex interrupt control. Any interrupt requests of the level equal to or lower than the current interrupt are not accepted. 2) When interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest level takes precedence over the other interrupts. For interrupts of the same level, the interrupt into the smallest vector address takes precedence. No. 1 2 3 4 5 6 7 8 9 10 Vector Address 00003H 0000BH 00013H 0001BH 00023H 0002BH 00033H 0003BH 00043H 0004BH Level X or L X or L H or L H or L H or L H or L H or L H or L H or L H or L INT0 INT1 INT2/T0L/INT4/USB bus active INT3/INT5/base timer T0H/INT6 T1L/T1H/INT7 SIO0/USB bus reset/USB suspend/UART1 receive SIO1/USB endpoint/USB-SOF/SIO4/UART1 transmit/AIF ADC/T6/T7 Port 0/PWM0/PWM1/T4/T5 Interrupt Source • Priority Level: X > H > L • Of interrupts of the same level, the one with the smallest vector address takes precedence. Subroutine Stack Levels: 1536 levels (the stack is allocated in RAM.) High-speed Multiplication/Division Instructions • 16 bits × 8 bits (5 tCYC execution time) • 24 bits × 16 bits (12 tCYC execution time) • 16 bits ÷ 8 bits (8 tCYC execution time) • 24 bits ÷ 16 bits (12 tCYC execution time) Oscillation Circuits • RC oscillation circuit (internal): • CF oscillation circuit: • Crystal oscillation circuit: • PLL circuit (internal): For system clock For system clock For system clock, time-of-day clock For USB interface (see Fig.5), audio interface (see Fig.6) Standby Function • HALT mode: Halts instruction execution while allowing the peripheral circuits to continue operation. 1) Oscillation is not halted automatically. 2) Canceled by a system reset or occurrence of an interrupt. • HOLD mode: Suspends instruction execution and the operation of the peripheral circuits. 1) The PLL base clock generator , CF, RC and crystal oscillators automatically stop operation. 2) There are four ways of resetting the HOLD mode. (1) Setting the reset pin to the lower level. (2) Setting at least one of the INT0, INT1, INT2, INT4, and INT5 pins to the specified level (3) Having an interrupt source established at port 0 (4) Having an bus active interrupt source established in the USB interface circuit • X'tal HOLD mode: Suspends instruction execution and the operation of the peripheral circuits except the base timer. 1) The PLL base clock generator, CF and RC oscillator automatically stop operation. 2) The state of crystal oscillation established when the X'tal HOLD mode is entered is retained. 3) There are five ways of resetting the X'tal HOLD mode. (1) Setting the reset pin to the low level (2) Setting at least one of the INT0, INT1, INT2, INT4, and INT5 pins to the specified level (3) Having an interrupt source established at port 0 (4) Having an interrupt source established in the base timer circuit (5) Having an bus active interrupt source established in the USB interface circuit No.A0477-4/29 LC87F1G64A ROM Correction Function • Executes the correction program on detection of a match with the program counter value. • Correction program area size: 128 bytes Package Form • TQFP48J(7×7): • QIP48E(14×14): • TQFP64J(10×10): Lead-free type Lead-free type Lead-free type Development Tools • On-chip debugger: TCB87 type-A or TCB87 type-B + LC87F1G64A Flash ROM Programming Boards Package QIP48E(14×14) TQFP48J(7×7) TQFP64J(10×10) Programming boards W87F55256Q W87F55256SQ W87F15256TQ Recommended EPROM programmer Maker Flash Support Group, Inc. (Single) SANYO Model AF9708/AF9709/AF9709B (including product of Ando Electric Co.,Ltd) SKK (SANYO FWS) Application Version: After 1.03 Chip Data Version: After 2.01 LC87F1G64 Supported version After 02.61 Device LC87F1G64A FAST Package Dimensions unit : mm (typ) 3288 9.0 Package Dimensions unit : mm (typ) 3156A 17.2 0.5 36 37 25 24 36 37 25 24 7.0 9.0 14.0 48 1 0.5 (0.75) 12 0.2 13 48 13 1 1.0 (1.5) 0.35 12 0.15 0.125 (1.0) 1.2max 3.0max 0.1 0.1 (2.7) SANYO : TQFP48J(7X7) SANYO : QIP48E(14X14) 17.2 No.A0477-5/29 0.8 7.0 14.0 LC87F1G64A Package Dimensions unit : mm (typ) 3310 12.0 48 49 33 32 10.0 64 1 0.5 (1.25) 16 0.18 17 12.0 0.125 1.2 MAX 0.1 (1.0) SANYO : TQFP64J(10X10) Pin Assignments DD+ VDD3 VSS3 P34/UFILT P33/AFILT P32/ACF2 P31/ACF1 P30/MCLK P70/INT0/T0LCP/AN8/DPUP P71/INT1/T0HCP/AN9 P72/INT2/T0IN 36 35 34 33 32 31 30 29 28 27 26 25 P27/INT5/LRCK P26/INT5/BCLK P25/INT5/SDAT P24/INT5/INT7/SCK4 P23/INT4/SI4/WR P22/INT4/SO4/RD P21/INT4/URX1 P20/INT4/INT6/UTX1 P07/AN7/T7O P06/AN6/T6O P05/AN5/CKO P04/AN4/DBGP2 0.5 10.0 37 38 39 40 41 42 43 44 45 46 47 48 LC87F1G64A 24 23 22 21 20 19 18 17 16 15 14 13 P03/AN3/DBGP1 P02/AN2/DBGP0 P01/AN1 P00/AN0 VSS2 VDD2 PWM0 PWM1 P17/T1PWMH/BUZ P16/T1PWML P15/SCK1 P14/SI1/SB1 P73/INT3/T0IN RES XT1/AN10 XT2/AN11 VSS1 CF1 CF2 VDD1 P10/SO0 P11/SI0/SB0 P12/SCK0 P13/SO1 1 2 3 4 5 6 7 8 9 10 11 12 Top view SANYO: TQFP48J(7×7) SANYO: QIP48E(14×14) “Lead-free Type” “Lead-free Type” No.A0477-6/29 LC87F1G64A P24/INT5/INT7/SCK4 P23/INT4/SI4/WR P22/INT4/SO4/RD P20/INT4/INT6/UTX1 P25/INT5/SDAT P27/INT5/LRCK P26/INT5/BCLK P04/AN4/DBGP2 P21/INT4/URX1 P05/AN5/CKO P07/AN7/T7O P06/AN6/T6O NC NC 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 NC NC DD+ VDD3 VSS3 P34/UFILT P33/AFILT P32/ACF2 P31/ACF1 P30/MCLK P70/INT0/T0LCP/AN8/DPUP P71/INT1/T0HCP/AN9 P72/INT2/T0IN NC NC 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 1 NC 2 NC 3 P73/INT3/T0IN 4 RES 5 XT1/AN10 6 XT2/AN11 7 VSS1 8 CF1 9 10 11 12 13 14 15 16 P11/SI0/SB0 P12/SCK0 NC P10/SO0 CF2 VDD1 P13/SO1 NC 32 31 30 29 28 27 26 NC NC P03/AN3/DBGP1 P02/AN2/DBGP0 P01/AN1 P00/AN0 VSS2 VDD2 PWM0 PWM1 P17/T1PWMH/BUZ P16/T1PWML P15/SCK1 P14/SI1/SB1 NC NC NC NC 25 24 23 22 21 20 19 18 17 LC87F1G64A Top view SANYO: TQFP64J(10×10) “Lead-free Type” No.A0477-7/29 LC87F1G64A TQFP48J/ QIP48E 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 TQFP48J/ QIP48E 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 NAME P73/INT3/T0IN RES XT1/AN10 XT2/AN11 VSS1 CF1 CF2 VDD1 P10/SO0 P11/SI0/SB0 P12/SCK0 P13/SO1 P14/SI1/SB1 P15/SCK1 P16/T1PWML P17/T1PWMH/BUZ PWM1 PWM0 VDD2 VSS2 P00/AN0 P01/AN1 P02/AN2/DBGP0 P03/AN3/DBGP1 NAME P04/AN4/DBGP2 P05/AN5/CKO P06/AN6/T6O P07/AN7/T7O P20/INT4/INT6/UTX1 P21/INT4/URX1 P22/INT4/SO4/RD P23/INT4/SI4/WR P24/INT5/INT7/SCK4 P25/INT5/SDAT P26/INT5/BCLK P27/INT5/LRCK DD+ VDD3 VSS3 P34/UFILT P33/AFILT P32/ACF2 P31/ACF1 P30/MCLK P70/INT0/T0LCP/AN8/DPUP P71/INT1/T0HCP/AN9 P72/INT2/T0IN No.A0477-8/29 LC87F1G64A TQFP64J 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 NC NC P73/INT3/T0IN RES XT1/AN10 XT2/AN11 VSS1 CF1 CF2 VDD1 P10/SO0 P11/SI0/SB0 P12/SCK0 P13/SO1 NC NC NC NC P14/SI1/SB1 P15/SCK1 P16/T1PWML P17/T1PWMH/BUZ PWM1 PWM0 VDD2 VSS2 P00/AN0 P01/AN1 P02/AN2/DBGP0 P03/AN3/DBGP1 NC NC NAME TQFP64J 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 NC NC P04/AN4/DBGP2 P05/AN5/CKO P06/AN6/T6O P07/AN7/T7O P20/INT4/INT6/UTX1 P21/INT4/URX1 P22/INT4/SO4/RD P23/INT4/SI4/WR P24/INT5/INT7/SCK4 P25/INT5/SDAT P26/INT5/BCLK P27/INT5/LRCK NC NC NC NC DD+ VDD3 VSS3 P34/UFILT P33/AFILT P32/ACF2 P31/ACF1 P30/MCLK P70/INT0/T0LCP/AN8/DPUP P71/INT1/T0HCP/AN9 P72/INT2/T0IN NC NC NAME No.A0477-9/29 LC87F1G64A System Block Diagram Interrupt control IR PLA Standby control FROM CF RC X’tal USB PLL Clock generator PC SIO0 Bus interface Port 0 ACC SIO1 B register SIO4 Port 1 C register Timer 0 Port 2 ALU Timer 1 Port 3 Timer 4 Port 7 INT0 to 7 Noise filter UART1 PSW Timer 5 RAR Timer 6 RAM Timer 7 Audio interface ADC Stack pointer Base timer Watchdog timer PWM0 On-chip debugger PWM1 USB interface No.A0477-10/29 LC87F1G64A Pin Description Pin Name VSS1, VSS2, VSS3 VDD1, VDD2 VDD3 Port 0 P00 to P07 I/O +power supply pin USB reference voltage pin • 8-bit I/O port • I/O specifiable in 4-bit units • Pull-up resistors can be turned on and off in 4-bit units. • HOLD reset input • Port 0 interrupt input • Pins functions AD converter input port: AN0 to AN7 (P00 to P07) On-chip debugger pins: DBGP0 to DBGP2 (P02 to P04) P01: Audio interface SDAT input P05: System Clock Output/Audio interface SDAT input P06: Timer 6 toggle outputs P07: Timer 7 toggle outputs Port 1 P10 to P17 I/O • 8-bit I/O port • I/O specifiable in 1-bit units • Pull-up resistors can be turned on and off in 1-bit units. • Pin functions P10: SIO0 data output P11: SIO0 data input/bus I/O P12: SIO0 clock I/O P13: SIO1 data output P14: SIO1 data input/bus I/O P15: SIO1 clock I/O P16: Timer 1 PWML output P17: Timer 1 PWMH output/beeper output Port 2 P20 to P27 I/O • 8-bit I/O port • I/O specifiable in 1-bit units • Pull-up resistors can be turned on and off in 1-bit units. • Pin functions P20 to P23: INT4 input/HOLD reset input/timer 1 event input/timer 0L capture input/ timer 0H capture input P24 to P27: INT5 input/HOLD reset input/timer 1 event input/timer 0L capture input/ timer 0H capture input P20: UART1 transmit/INT6 input/timer 0L capture 1 input P21: UART1 receive/Audio interface SDAT input P22: SIO4 date I/O/parallel interface RD output P23: SIO4 date I/O/parallel interface WR output P24: SIO4 clock I/O/INT7 input/timer 0H capture 1 input P25: Audio interface SDAT I/O P26: Audio interface BCLK I/O P27: Audio interface LRCK I/O Interrupt acknowledge type Rising INT4 INT5 INT6 INT7 enable enable enable enable Falling enable enable enable enable Rising & Falling enable enable enable enable H level disable disable disable disable L level disable disable disable disable Yes Yes No Yes Yes I/O -power supply pin Description Option No Continued on next page. No.A0477-11/29 LC87F1G64A Continued from preceding page. Pin Name Port 3 P30 to P34 I/O I/O • 5-bit I/O port • I/O specifiable in 1-bit units • Pull-up resistors can be turned on and off in 1-bit units. • Pin functions P30: Audio interface master clock I/O P31: Audio interface oscillator input P32: Audio interface oscillator output P33: Audio interface PLL filter pin (see Fig.6) P34: USB interface PLL filter pin (see Fig.5) Port 7 P70 to P73 I/O • 4-bit I/O port • I/O specifiable in 1-bit units • Pull-up resistors can be turned on and off in 1-bit units. • Pin functions P70: INT0 input/HOLD reset input/timer 0L capture input/watchdog timer output/ D+ 1.5kΩ pull-up resistor connect pin P71: INT1 input/HOLD reset input/timer 0H capture input P72: INT2 input/HOLD reset input/timer 0 event input/timer 0L capture input/ High speed clock counter input P73: INT3 input (with noise filter)/timer 0 event input/timer 0H capture input AD converter input port: AN8(P70), AN9(P71) Interrupt acknowledge type Rising INT0 INT1 INT2 INT3 enable enable enable enable Falling enable enable enable enable Rising & Falling disable disable enable enable H level enable enable disable disable L level enable enable disable disable No Description Option Yes PWM0 PWM1 DD+ RES XT1 I/O I/O I/O Input Input • PWM0 and PWM1 output port • General-purpose input port • USB data I/O pin D• General-purpose I/O port • USB data I/O pin D+ • General-purpose I/O port Reset pin • 32.768kHz crystal oscillator input pin • Pin functions General-purpose input port AD converter input port: AN10 Must be connected to VDD1 if not to be used. No No No No No XT2 I/O 32.768kHz crystal oscillator output pin • Pin functions General-purpose I/O port AD converter input port: AN11 Must be set for oscillation and kept open if not to be used. No CF1 CF2 Input Output Ceramic resonator input pin Ceramic resonator output pin No No No.A0477-12/29 LC87F1G64A Port Output Types The table below lists the types of port outputs and the presence/absence of a pull-up resistor. Data can be read into any input port even if it is in the output mode. Port Name P00 to P07 Option Selected in Units of 1 bit Option Type 1 2 P10 to P17 P20 to P27 P30 to P34 P70 P71 to P73 PWM0, PWM1 D+, DXT1 XT2 No No No No No No Nch-open drain CMOS CMOS CMOS Input only 32.768kHz crystal oscillator output Programmable Programmable No No No No 1 bit 1 2 CMOS Nch-open drain CMOS Nch-open drain Output Type Pull-up Resistor Programmable (Note 1) No Programmable Programmable Note 1: Programmable pull-up resistors for port 0 are controlled in 4 bit units (P00 to 03, P04 to 07). Power Pin Treatment Connect the IC as shown below to minimize the noise input to the VDD1 pin. Be sure to electrically short the VSS1, VSS2, and VSS3 pins. Example 1: When the microcontroller is in the backup state in the HOLD mode, the power to sustain the high level of output ports is supplied by their backup capacitors. LSI Power supply For backup VDD1 VDD2 VDD3 VSS1 VSS2 VSS3 Example 2: The high level output at ports is not sustained and unstable in the HOLD backup mode. LSI For backup Power supply VDD1 VDD2 VDD3 VSS1 VSS2 VSS3 No.A0477-13/29 LC87F1G64A USB Reference Power Option When a voltage 4.5 to 5.5V is supplied to VDD1 and the internal USB reference voltage circuit is activated, the reference voltage for USB port output is generated. The active/inactive state of reference voltage circuit can be switched by the option select. The procedure for marking the option selection is described below. (1) Option select USB Regulator USB Regulator at HOLD mode USB Regulator at HALT mode Reference voltage circuit state Normal state HOLD mode HALT mode USE USE USE active active active (2) USE NONUSE NONUSE active inactive inactive (3) USE NONUSE USE active inactive active (4) NONUSE NONUSE NONUSE inactive inactive inactive • When the USB reference voltage circuit is made inactive, the level of the reference voltage for USB port output is equal to VDD1. • Selection (2) or (3) can be used to set the reference voltage circuit inactive in HOLD or HALT mode. • When the reference voltage circuit is activated, the current drain increase by approximately 100µA compared with when the reference voltage circuit is inactive. Example 1: VDD1=VDD2=3.3V • Inactivating the reference voltage circuit (selection (4)). • Connecting VDD3 to VDD1 and VDD2. LSI P70 For backup Power supply 3.3V 1.5kΩ VDD1 D+ D5pF 0Ω VSS1 VSS2 VSS3 2.2µF 27 to 33Ω To USB connector VDD2 VDD3 UFILT Example 2: VDD1=VDD2=5.0V • Activating the reference voltage circuit (selection (1)). • Isolating VDD3 from VDD1 and VDD2, and connecting capacitor between VDD3 and VSS. LSI P70 1.5kΩ VDD1 D+ DVDD2 5pF 2.2µF 0.1µF VSS1 VSS2 VSS3 2.2µF VDD3 UFILT 0Ω 27 to 33Ω To USB connector For backup Power supply 5V No.A0477-14/29 LC87F1G64A Absolute Maximum Ratings at Ta = 25°C, VSS1 = VSS2 = VSS3 = 0V Parameter Maximum supply voltage Input voltage Input/output voltage Peak output current IOPH(2) IOPH(3) PWM0, PWM1 Ports 3 P71 to P73 Average output current (Note 1-1) IOMH(2) IOMH(3) PWM0, PWM1 Ports 3 P71 to P73 Total output current ΣIOAH(1) ΣIOAH(2) ΣIOAH(3) ΣIOAH(4) ΣIOAH(5) Peak output current IOPL(2) IOPL(3) Low level output current Average output current (Note 1-1) IOML(2) IOML(3) Total output current ΣIOAL(1) ΣIOAL(2) ΣIOAL(3) ΣIOAL(4) ΣIOAL(5) Allowable power Dissipation Pd max IOML(1) IOPL(1) Ports 0, 2 Ports 1 PWM0, PWM1 Ports 0, 1, 2 PWM0, PWM1 Ports 3 P71 to P73 D+, DP02 to P07 Ports 1, 2 PWM0, PWM1 P00, P01 Ports 3, 7, XT2 P02 to P07 Ports 1, 2 PWM0, PWM1 P00, P01 Ports 3, 7, XT2 Ports 0, 2 Ports 1 PWM0, PWM1 Ports 0, 1, 2 PWM0, PWM1 Ports 3, 7, XT2 D+, DQIP48E(14×14) TQFP48J(7×7) TQFP64J(10×10) Operating ambient Temperature Storage ambient temperature Tstg Topr -20 -55 Total of all applicable pins Total of all applicable pins Ta=-20to+70°C Total of all applicable pins Per 1 applicable pin Per 1 applicable pin Total of all applicable pins Total of all applicable pins 20 7.5 45 45 80 15 25 330 190 280 +70 °C +125 mW Per 1 applicable pin Per 1 applicable pin Per 1 applicable pin 15 30 10 Total of all applicable pins Per 1 applicable pin 20 Total of all applicable pins Total of all applicable pins IOMH(1) Ports 0, 1, 2 IOPH(1) VI(1) VIO(1) XT1, CF1 Ports 0, 1, 2, 3, 7 PWM0, PWM1, XT2 Ports 0, 1, 2 • When CMOS output type is selected • Per 1 applicable pin Per 1 applicable pin • When CMOS output type is selected • Per 1 applicable pin High level output current • When CMOS output type is selected • Per 1 applicable pin Per 1 applicable pin • When CMOS output type is selected • Per 1 applicable pin Total of all applicable pins Total of all applicable pins -25 -25 -45 -10 -25 mA -3 -15 -7.5 -5 -20 -10 Symbol VDD max Pin/Remarks VDD1, VDD2, VDD3 Conditions VDD[V] VDD1=VDD2=VDD3 min -0.3 -0.3 -0.3 Specification typ max +6.5 VDD+0.3 VDD+0.3 V unit Note 1-1: The mean output current is a mean value measured over 100ms. No.A0477-15/29 LC87F1G64A Allowable Operating Conditions at Ta = -20°C to +70°C, VSS1 = VSS2 = VSS3 = 0V Parameter Operating supply voltage (Note 2-1) Memory sustaining supply voltage High level input voltage VIH(1) Ports 0, 1, 2, 3 P71 to P73 P70 port input/ interrupt side PWM0, PWM1 VIH(2) VIH(3) Low level input voltage VIL(2) VIL(3) VIL(4) VIL(5) VIL(6) Instruction cycle time (Note 2-2) External system clock frequency FEXCF(1) CF1 tCYC Except for onboard programming • CF2 pin open • System clock frequency division ratio=1/1 • External system clock duty =50±5% • CF2 pin open • System clock frequency division ratio=1/1 • External system clock duty =50±5% Oscillation frequency range (Note 2-3) FmRC FsX’tal XT1, XT2 FmCF(2) CF1, CF2 FmCF(1) CF1, CF2 12 MHz ceramic oscillation See Fig. 1. 6 MHz ceramic oscillation See Fig. 1. Internal RC oscillation 32.768kHz crystal oscillation See Fig. 2. 3.0 to 5.5 2.7 to 5.5 2.7 to 5.5 2.7 to 5.5 0.3 12 6 1.0 32.768 2.0 kHz MHz 2.7 to 5.5 0.1 6 MHz 3.0 to 5.5 0.1 12 Port 70 watchdog timer side XT1, XT2, CF1, RES VIL(1) Port 70 watchdog timer side XT1, XT2, CF1, RES Ports 1, 2 P71 to P73 P70 port input/ interrupt side Ports 0, 3 PWM0, PWM1 2.7 to 5.5 2.7 to 5.5 4.0 to 5.5 2.7 to 4.0 4.0 to 5.5 2.7 to 4.0 2.7 to 5.5 2.7 to 5.5 3.0 to 5.5 2.7 to 5.5 0.9VDD 0.75VDD VSS VSS VSS VSS VSS VSS 0.245 0.490 VDD VDD 0.1VDD +0.4 0.2VDD 0.15VDD +0.4 0.2VDD 0.8VDD -1.0 0.25VDD 200 µs 200 V 2.7 to 5.5 0.3VDD +0.7 VDD VHD VDD1=VDD2=VDD3 Symbol VDD(1) Pin/Remarks VDD1=VDD2=VDD3 Conditions VDD[V] 0.245µs≤tCYC≤200µs 0.490µs≤tCYC≤200µs Except for onboard programming RAM and register contents sustained in HOLD mode. 2.0 5.5 min 3.0 2.7 Specification typ max 5.5 5.5 unit Note 2-1: VDD must be held greater than or equal to 3.0V in the flash ROM onboard programming mode. Note 2-2: Relationship between tCYC and oscillation frequency is 3/FmCF at a division ratio of 1/1 and 6/FmCF at a division ratio of 1/2. Note 2-3: See Tables 1 and 2 for the oscillation constants. No.A0477-16/29 LC87F1G64A Electrical Characteristics at Ta = -20°C to +70°C, VSS1 = VSS2 = VSS3 = 0V Parameter High level input current Symbol IIH(1) Pin/Remarks Ports 0, 1, 2, 3 Port 7 RES PWM0, PWM1 D+, DIIH(2) IIH(3) Low level input current IIL(1) XT1, XT2 Conditions VDD[V] Output disabled Pull-up resistor off VIN=VDD (Including output Tr's off leakage current) For input port specification VIN=VDD CF1 Ports 0, 1, 2, 3 Port 7 RES PWM0, PWM1 D+, DIIL(2) IIL(3) High level output voltage VOH(1) VOH(2) VOH(3) VOH(4) VOH(5) P30 (when using MCLK output function) P73 (when using clock output function) VOH(6) VOH(7) VOH(8) Low level output voltage VOL(1) VOL(2) VOL(3) VOL(4) VOL(5) VOL(6) VOL(7) VOL(8) Pull-up resistance Rpu(1) Rpu(2) Hysteresis voltage Pin capacitance VHYS CP Ports 0, 1, 2, 3 Port 7 RES Ports 1, 2, 7 All pins For pins other than that under test: VIN=VSS f=1MHz Ta=25°C 2.7 to 5.5 10 pF Ports 0, 1, 2 PWM0, PWM1 XT2 Ports 3, 7 PWM0, PWM1 P05 (CK0 when using system clock output function) P00, P01 IOH=-10mA IOH=-1.6mA IOH=-1mA IOL=30mA IOL=5mA IOL=2.5mA IOL=10mA IOL=1.6mA IOL=1mA IOL=1.6mA IOL=1mA VOH=0.9VDD 4.5 to 5.5 3.0 to 5.5 2.7 to 5.5 4.5 to 5.5 3.0 to 5.5 2.7 to 5.5 4.5 to 5.5 3.0 to 5.5 2.7 to 5.5 3.0 to 5.5 2.7 to 5.5 4.5 to 5.5 2.7 to 5.5 2.7 to 5.5 15 18 35 50 0.1VDD VDD-1.5 VDD-0.4 VDD-0.4 1.5 0.4 0.4 1.5 0.4 0.4 0.4 0.4 80 150 V kΩ V 2.7 to 5.5 VDD-0.4 XT1, XT2 CF1 Ports 0, 1, 2, 3 P71 to P73 VIN=VDD Output disabled Pull-up resistor off VIN=VSS (Including output Tr's off leakage current) For input port specification VIN=VSS VIN=VSS IOH=-1mA IOH=-0.4mA IOH=-0.2mA IOH=-1.6mA IOH=-1mA 2.7 to 5.5 2.7 to 5.5 4.5 to 5.5 3.0 to 5.5 2.7 to 5.5 3.0 to 5.5 -1 -15 VDD-1 VDD-0.4 VDD-0.4 VDD-0.4 2.7 to 5.5 -1 2.7 to 5.5 2.7 to 5.5 1 15 µA 2.7 to 5.5 1 min Specification typ max unit No.A0477-17/29 LC87F1G64A Serial I/O Characteristics at Ta = -20°C to +70°C, VSS1 = VSS2 = VSS3 = 0V 1. SIO0 Serial I/O Characteristics (Note 4-1-1) Parameter Frequency Low level pulse width High level pulse width tSCKHA(1a) • Continuous data transmission/ reception mode • USB, SIO4 nor AIF are not in use simultaneous. • See Fig.9. Input clock • (Note 4-1-2) tSCKHA(1b) • Continuous data transmission/reception mode • USB is in use simultaneous. • SIO4 nor AIF are not in use simultaneous. • See Fig.9. • (Note 4-1-2) tSCKHA(1c) • Continuous data transmission/ reception mode • USB, SIO4 and AIF are in use simultaneous. Serial clock • See Fig.9. • (Note 4-1-2) Frequency Low level pulse width High level pulse width tSCKHA(2a) • Continuous data transmission/ reception mode • USB, SIO4 nor AIF are not in use simultaneous. Output clock • CMOS output selected • See Fig.9. tSCKHA(2b) • Continuous data transmission/ reception mode • USB is in use simultaneous. • SIO4 nor AIF are not in use simultaneous. • CMOS output selected • See Fig.9. tSCKHA(2c) • Continuous data transmission/ reception mode • USB, SIO4 and AIF are in use simultaneous. • CMOS output selected • See Fig.9. tSCKH(2) +2tCYC tSCKH(2) +(25/3) tCYC tSCKH(2) +2tCYC tSCKH(2) +(19/3) tCYC tCYC 2.7 to 5.5 tSCKH(2) +2tCYC tSCKH(2) +(10/3) tCYC tSCKH(2) tSCK(2) tSCKL(2) SCK0(P12) • CMOS output selected • See Fig.9. 4/3 1/2 tSCK 1/2 9 7 2.7 to 5.5 tCYC 4 tSCKH(1) Symbol tSCK(1) tSCKL(1) Pin/Remarks SCK0(P12) See Fig.9. Conditions VDD[V] min 2 1 1 Specification typ max unit Note 4-1-1: These specifications are theoretical values. Add margin depending on its use. Note 4-1-2: To use serial-clock-input in continuous trans/rec mode, a time from SI0RUN being set when serial clock is "H" to the first negative edge of the serial clock must be longer than tSCKHA. Continued on next page. No.A0477-18/29 LC87F1G64A Continued from preceding page. Parameter Data setup time Serial input Symbol tsDI(1) Pin/Remarks SB0(P11), SI0(P11) Data hold time thDI(1) 2.7 to 5.5 Output delay Input clock time tdD0(2) tdD0(1) SO0(P10), SB0(P11) • Continuous data transmission/reception mode • (Note 4-1-3) • Synchronous 8-bit mode • (Note 4-1-3) tdD0(3) (Note 4-1-3) 2.7 to 5.5 (1/3)tCYC +0.05 2.7 to 5.5 2.7 to 5.5 0.03 Conditions VDD[V] • Must be specified with respect to rising edge of SIOCLK. • See Fig.9. 2.7 to 5.5 0.03 min Specification typ max unit (1/3)tCYC +0.05 1tCYC +0.05 µs Serial output Note 4-1-3: Must be specified with respect to falling edge of SIOCLK. Must be specified as the time to the beginning of output state change in open drain output mode. See Fig.9. 2. SIO1 Serial I/O Characteristics (Note 4-2-1) Parameter Frequency Input clock Low level pulse width High level pulse width Frequency Output clock Low level pulse width High level pulse width Data setup time Serial input tsDI(2) SB1(P14), SI1(P14) Data hold time thDI(2) • Must be specified with respect to rising edge of SIOCLK. • See Fig.9. 2.7 to 5.5 Output delay time Serial output tdD0(4) SO1(P13), SB1(P14) • Must be specified with respect to falling edge of SIOCLK. • Must be specified as the time to the beginning of output state change in open drain output mode. • See Fig.9. 2.7 to 5.5 (1/3)tCYC +0.05 0.03 2.7 to 5.5 0.03 tSCKH(4) 1/2 tSCK(4) tSCKL(4) 2.7 to 5.5 SCK1(P15) • CMOS output selected • See Fig.9. tSCKH(3) Symbol tSCK(3) tSCKL(3) Pin/Remarks SCK1(P15) See Fig.9. Conditions VDD[V] min 2 2.7 to 5.5 1 tCYC 1 2 1/2 tSCK Specification typ max unit Serial clock Output clock µs Note 4-2-1: These specifications are theoretical values. Add margin depending on its use. No.A0477-19/29 LC87F1G64A 3. SIO4 Serial I/O Characteristics (Note 4-3-1) Parameter Frequency Low level pulse width High level pulse width tSCKH(5) tSCKHA(5a) • USB, AIF nor continuous data Transmission/reception mode Of SIO0 are not in use simultaneous. • See Fig.9. Input clock • (Note 4-3-2) tSCKHA(5b) • USB is in use simultaneous. • AIF nor continuous data transmission/reception mode of SIO0 are not in use simultaneous. • See Fig.9. • (Note 4-3-2) tSCKHA(5c) • USB and continuous data transmission/ reception mode of SIO0 are in use simultaneous. • AIF is not in use simultaneous. Serial clock • See Fig.9. • (Note 4-3-2) Frequency Low level pulse width High level pulse width tSCKHA(6a) • USB, AIF nor continuous data transmission/reception mode of SIO0 are not in use simultaneous. • CMOS output selected Output clock • See Fig.9. tSCKHA(6b) • USB is in use simultaneous. • AIF nor continuous data transmission/reception mode of SIO0 are not in use simultaneous. • CMOS output selected • See Fig.9. tSCKHA(6c) • USB and continuous data transmission/reception mode of SIO0 are in use simultaneous. • AIF is not in use simultaneous. • CMOS output selected • See Fig.9. Data setup time Serial input tsDI(3) SO4(P22), SI4(P23) Data hold time thDI(3) 2.7 to 5.5 0.03 • Must be specified with respect to rising edge of SIOCLK. • See Fig.9. 2.7 to 5.5 0.03 µs tSCKH(6) +(5/3) tCYC tSCKH(6) +(28/3) tCYC tSCKH(6) +(5/3) tCYC tSCKH(6) +(19/3) tCYC tCYC 2.7 to 5.5 tSCKH(6) +(5/3) tCYC tSCKH(6) +(10/3) tCYC tSCKH(6) tSCK(6) tSCKL(6) SCK4(P24) • CMOS output selected • See Fig.9. 4/3 1/2 tSCK 1/2 10 7 2.7 to 5.5 tCYC 4 Symbol tSCK(5) tSCKL(5) Pin/ Remarks SCK4(P24) See Fig.9. Conditions VDD[V] min 2 1 1 Specification typ max unit Note 4-3-1: These specifications are theoretical values. Add margin depending on its use. Note 4-3-2: To use serial-clock-input in continuous trans/rec mode, a time from SI4RUN being set when serial clock is "H" to the first negative edge of the serial clock must be longer than tSCKHA. Continued on next page. No.A0477-20/29 LC87F1G64A Continued from preceding page. Parameter Output delay time Serial output Symbol tdD0(5) Pin/ Remarks SO4(P22), SI4(P23) Conditions VDD[V] • Must be specified with respect to rising edge of SIOCLK. • Must be specified as the time to the beginning of output state change in open drain output mode. • See Fig.9. 2.7 to 5.5 (1/3)tCYC +0.05 µs min Specification typ max unit Pulse Input Conditions at Ta = -20°C to +70°C, VSS1 = VSS2 = VSS3 = 0V Parameter High/low level pulse width Symbol tP1H(1) tP1L(1) Pin/Remarks INT0(P70), INT1(P71), INT2(P72), INT4(P20 to P23), INT5(P24 to P27), INT6(P20), INT7(P24) tPIH(2) tPIL(2) tPIH(3) tPIL(3) tPIH(4) tPIL(4) tPIL(5) INT3(P73) when noise filter time constant is 1/1 INT3(P73) when noise filter time constant is 1/32 INT3(P73) when noise filter time constant is 1/128 RES • Interrupt source flag can be set. • Event inputs for timer 0 are enabled. • Interrupt source flag can be set. • Event inputs for timer 0 are enabled. • Interrupt source flag can be set. • Event inputs for timer 0 are enabled. Resetting is enabled. 2.7 to 5.5 200 µs 2.7 to 5.5 256 2.7 to 5.5 64 2.7 to 5.5 2 tCYC Conditions VDD[V] • Interrupt source flag can be set. • Event inputs for timer 0 or 1 are enabled. 2.7 to 5.5 1 min Specification typ max unit AD Converter Characteristics at Ta = -20°C to +70°C, VSS1 = VSS2 = VSS3 = 0V Parameter Resolution Absolute accuracy Conversion time TCAD N ET Symbol Pin/Remarks AN0(P00) to AN7(P07), AN8(P70), AN9(P71), AN10(XT1), AN11(XT2) AD conversion time=32×tCYC (when ADCR2=0) (Note 6-2) 4.5 to 5.5 (Note 6-1) Conditions VDD[V] 3.0 to 5.5 3.0 to 5.5 15.68 (tCYC= 0.49µs) 23.52 3.0 to 5.5 AD conversion time=64×tCYC (when ADCR2=1) (Note 6-2) 4.5 to 5.5 (tCYC= 0.735µs) 18.82 (tCYC= 0. 294µs) 47.04 3.0 to 5.5 Analog input voltage range Analog port input current IAINH IAINL VAIN=VDD VAIN=VSS VAIN (tCYC= 0. 735µs) 3.0 to 5.5 3.0 to 5.5 3.0 to 5.5 -1 VSS min Specification typ 8 ±1.5 97.92 (tCYC= 3.06µs) 97.92 (tCYC= 3.06µs) 97.92 (tCYC= 1.53µs) 97.92 (tCYC= 1.53µs) VDD 1 V µA µs max unit bit LSB Note 6-1: The quantization error (±1/2LSB) is excluded from the absolute accuracy value. Note 6-2: The conversion time refers to the interval from the time the instruction for starting the converter is issued till the time the complete digital value corresponding to the analog input value is loaded in the required register. No.A0477-21/29 LC87F1G64A Consumption Current Characteristics at Ta = -20°C to +70°C, VSS1 = VSS2 = VSS3 = 0V Parameter Normal mode consumption current (Note 7-1) Symbol IDDOP(1) IDDOP(2) Pin/ Remarks VDD1 =VDD2 =VDD3 Conditions VDD[V] • FmCF=12MHz ceramic oscillation mode • FsX’tal=32.768kHz crystal oscillation mode • System clock set to 12MHz side • Internal PLL oscillation stopped • Internal RC oscillation stopped • 1/1 frequency division ration IDDOP(3) IDDOP(4) • FmCF=12MHz ceramic oscillation mode • FsX’tal=32.768kHz crystal oscillation mode • System clock set to 12MHz side • Internal PLL oscillation mode • Internal RC oscillation stopped • 1/1 frequency division ration IDDOP(5) IDDOP(6) IDDOP(7) • FmCF=12MHz ceramic oscillation mode • FsX’tal=32.768kHz crystal oscillation mode • System clock set to 6MHz side • Internal RC oscillation stopped • 1/2 frequency division ration IDDOP(8) IDDOP(9) IDDOP(10) IDDOP(11) IDDOP(12) IDDOP(13) • FmCF=0MHz (oscillation stopped) • FsX’tal=32.768kHz crystal oscillation mode • System clock set to internal RC oscillation • 1/2 frequency division ration • FmCF=0MHz (oscillation stopped) • FsX’tal=32.768kHz crystal oscillation mode • System clock set to 32.768kHz side • Internal RC oscillation stopped • 1/2 frequency division ration HALT mode consumption current (Note 7-1) IDDHALT(1) IDDHALT(2) VDD1 =VDD2 =VDD3 • HALT mode • FmCF=12MHz ceramic oscillation mode • FsX’tal=32.768kHz crystal oscillation mode • System clock set to 12MHz side • Internal PLL oscillation stopped • Internal RC oscillation stopped • 1/1 frequency division ration IDDHALT(3) IDDHALT(4) • HALT mode • FmCF=12MHz ceramic oscillation mode • FsX’tal=32.768kHz crystal oscillation mode • System clock set to 12MHz side • Internal PLL oscillation mode • Internal RC oscillation stopped • 1/1 frequency division ration IDDHALT(5) IDDHALT(6) IDDHALT(7) • HALT mode • FmCF=12MHz ceramic oscillation mode • FsX’tal=32.768kHz crystal oscillation mode • System clock set to 6MHz side • Internal RC oscillation stopped • 1/2 frequency division ration 2.7 to 3.0 1.3 3.0 4.5 to 5.5 3.0 to 3.6 3.0 1.6 7.2 3.9 3.0 to 3.6 4.0 9.6 mA 4.5 to 5.5 7.3 18 3.0 to 3.6 2.7 6.5 4.5 to 5.5 4.9 12 2.7 to 3.0 14 43 2.7 to 3.0 4.5 to 5.5 3.0 to 3.6 0.30 41 17 1.3 160 60 µA 4.5 to 5.5 3.0 to 3.6 0.67 0.35 3.2 1.6 2.7 to 3.0 3.0 6.7 4.5 to 5.5 3.0 to 3.6 6.4 3.7 15 8.7 3.0 to 3.6 7.3 18 mA 4.5 to 5.5 13 32 3.0 to 3.6 5.6 14 4.5 to 5.5 min Specification typ 9.9 max 24 unit Note 7-1: The consumption current value includes none of the currents that flow into the output Tr and internal pull-up resistors. Continued on next page. No.A0477-22/29 LC87F1G64A Continued from preceding page. Parameter HALT mode consumption current (Note 7-1) Symbol IDDHALT(8) IDDHALT(9) IDDHALT(10) Pin/ Remarks VDD1 =VDD2 =VDD3 • HALT mode • FmCF=0MHz (oscillation stopped) • FsX'tal=32.768kHz crystal oscillation mode • System clock set to internal RC oscillation • 1/2 frequency division ration IDDHALT(11) IDDHALT(12) IDDHALT(13) • HALT mode • FmCF=0MHz (oscillation stopped) • FsX'tal=32.768kHz crystal oscillation mode • System clock set to 32.768kHz side • Internal RC oscillation stopped • 1/2 frequency division ration HOLD mode consumption current Timer HOLD mode consumption current IDDHOLD(1) IDDHOLD(2) IDDHOLD(3) IDDHOLD(4) IDDHOLD(5) IDDHOLD(6) VDD1 Timer HOLD mode • CF1=VDD or open (External clock mode) • FsX’tal=32.768kHz crystal oscillation mode 2.7 to 3.0 3.3 14 VDD1 HOLD mode • CF1=VDD or open (External clock mode) 4.5 to 5.5 3.0 to 3.6 2.7 to 3.0 4.5 to 5.5 3.0 to 3.6 0.14 0.04 0.03 21 5.1 24 15 12 90 24 µA 2.7 to 3.0 5.8 22 4.5 to 5.5 3.0 to 3.6 26 8.2 110 33 2.7 to 3.0 0.15 0.62 Conditions VDD[V] 4.5 to 5.5 3.0 to 3.6 min Specification typ 0.37 0.18 max 1.8 0.83 mA unit Note 7-1: The consumption current value includes none of the currents that flow into the output Tr and internal pull-up resistors. USB Characteristics and Timing at Ta = 0°C to +70°C, VSS1 = VSS2 = VSS3 = 0V Parameter High level output Low level output Output signal crossover voltage Differential input sensitivity Differential input common mode range High level input Low level input USB data rise time USB data fall time Symbol VOH(USB) VOL(USB) VCRS VDI VCM VIH(USB) VIL(USB) tR tF • RS=27 to 33Ω,CL=50pF • VDD3=3.0 to 3.6V • RS=27 to 33Ω,CL=50pF • VDD3=3.0 to 3.6V 4 4 • |(D+)-(D-)| Conditions min • 15kΩ±5% to GND • 1.5kΩ±5% to 3.6 V 2.8 0.0 1.3 0.2 0.8 2.0 0.8 20 20 2.5 Specification typ max 3.6 0.3 2.0 unit V V V V V V V ns ns F-ROM Programming Characteristics at Ta = +10°C to +55°C, VSS1 = VSS2= VSS3 =0V Parameter Onboard programming current Programming time tFW(1) • 128-byte programming • Erasing current included • Time for setting up 128-byte data is excluded. 3.0 to 5.5 22.5 45 ms Symbol IDDFW(1) Pin VDD1 Conditions VDD[V] • 128-byte programming • Erasing current included 3.0 to 5.5 25 40 mA min Specification typ max unit No.A0477-23/29 LC87F1G64A Characteristics of a Sample Main System Clock Oscillation Circuit Given below are the characteristics of a sample main system clock oscillation circuit that are measured using a SANYO-designated oscillation characteristics evaluation board and external components with circuit constant values with which the oscillator vendor confirmed normal and stable oscillation. Table 1 Characteristics of a Sample Main System Clock Oscillator Circuit with a Ceramic Oscillator Nominal Frequency 6MHz 8MHz 10MHz 12MHz Vendor Name MURATA MURATA MURATA MURATA Circuit Constant Oscillator Name C1 [pF] CSTCR6M00G15***-R0 CSTCE8M00G15***-R0 CSTCE10M0G15***-R0 CSTCE12M0G15***-R0 (39) (33) (33) (33) C2 [pF] (39) (33) (33) (33) Rd1 [Ω] 1k 680 470 470 Operating Voltage Range [V] 2.7 to 5.5 3.0 to 5.5 3.0 to 5.5 3.0 to 5.5 Oscillation Stabilization Time typ [ms] 0.05 0.05 0.05 0.05 max [ms] 0.50 0.50 0.50 0.50 Built-in C1, C2 Remarks The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized after VDD goes above the operating voltage lower limit (see Figure 4). Characteristics of a Sample Subsystem Clock Oscillator Circuit Given below are the characteristics of a sample subsystem clock oscillation circuit that are measured using a SANYOdesignated oscillation characteristics evaluation board and external components with circuit constant values with which the oscillator vendor confirmed normal and stable oscillation. Table 2 Characteristics of a Sample Subsystem Clock Oscillator Circuit with a CF Oscillator Nominal Frequency Vendor Name EPSON TOYOCOM Circuit Constant Oscillator Name C3 [pF] 32.768kHz MC-306 18 C4 [pF] 18 Rf [Ω] OPEN Rd2 [Ω] 510k Operating Voltage Range [V] 2.7 to 5.5 Oscillation Stabilization Time typ [s] 1.1 max [s] 3.0 Applicable CL value=12.5pF Remarks The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized after the instruction for starting the subclock oscillation circuit is executed and to the time interval that is required for the oscillation to get stabilized after the HOLD mode is reset (see Figure 4). Note: The components that are involved in oscillation should be placed as close to the IC and to one another as possible because they are vulnerable to the influences of the circuit pattern. CF1 CF2 XT1 XT2 Rd1 Rf Rd2 C1 CF C2 C3 X’tal C4 Figure 1 CF Oscillator Circuit Figure 2 XT Oscillator Circuit 0.5VDD Figure 3 AC Timing Measurement Point No.A0477-24/29 LC87F1G64A VDD Power Supply Reset time Operating VDD lower limit GND RES Internal RC oscillation tmsCF CF oscillation (XT1, XT2) tmsX’tal Crystal oscillation (XT1, XT2) Operating mode Unpredictable Reset Instruction execution Reset Time and Oscillation Stabilization Time HOLD reset signal HOLD reset signal valid Internal RC oscillation tmsCF CF oscillation (XT1, XT2) tmsX’tal Crystal Oscillation (XT1, XT2) Operating mode HOLD HALT HOLD Reset Signal and Oscillation Stabilization Time Figure 4 Oscillation Stabilization Time No.A0477-25/29 LC87F1G64A P34/UFILT Rd 0Ω + Cd 2.2µF When using the internal PLL circuit to generate the 48 MHz clock for USB , it is necessary to connect a filter circuit such as that shown to the left to the P34/UFILT pin. Figure 5 External Filter Circuit for the Internal USB-dedicated PLL Circuit P33/AFILT Cp 10µF + - Rd 2kΩ Cd 33µF When using the internal PLL circuit to generate the master clock for the audio interface, it is necessary to connect a filter circuit such as that shown to the left to the P33 pin. Figure 6 External Filter Circuit for the Internal Audio Interface Dedicated PLL Circuit No.A0477-26/29 LC87F1G64A VD3OEN P70 1.5kΩ D+ 27 to 33Ω 5pF Note: It’s necessary to adjust the Circuit Constant of the USB Port Peripheral Circuit each mounting board. Make the D+ Pull-up resistors available to control on/off according to the Vbus. D27 to 33Ω 5pF Figure 7 USB Port Peripheral Circuit VDD RRES RES CRES Note: Determine the value of CRES and RRES so that the reset signal is present for a period of 200µs after the supply voltage goes beyond the lower limit of the IC's operating voltage. Figure 8 Reset Circuit No.A0477-27/29 LC87F1G64A SIOCLK: DATAIN: DI0 DI1 DI2 DI3 DI4 DI5 DI6 DI7 DI8 DATAOUT: DO0 DO1 DO2 DO3 DO4 DO5 DO6 DO7 Data RAM transfer period (SIO0, 4 only) DO8 tSCK tSCKL SIOCLK: tsDI DATAIN: tdDO DATAOUT: thDI tSCKH Data RAM transfer period (SIO0, 4 only) tSCKL SIOCLK: tsDI DATAIN: tdDO DATAOUT: thDI tSCKHA Figure 9 Serial I/O Waveforms tPIL tPIH Figure 10 Pulse Input Timing Signal Waveform Voh Vcrs D+ tr 90% 10% 90% tr 10% Vol D- Figure 11 USB Data Signal Timing and Voltage Level No.A0477-28/29 LC87F1G64A Specifications of any and all SANYO Semiconductor products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment. SANYO Semiconductor Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. 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Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO Semiconductor believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of December, 2006. Specifications and information herein are subject to change without notice. PS No.A0477-29/29