LC87F1M16A

Ordering number : ENA1909A LC87F1M16A Overview CMOS IC 16K-byte FROM and 1024-byte RAM integrated 8-bit 1-chip Microcontroller with Full-Speed USB The LC87F1M16A is an 8-bit microcomputer that, centered around a CPU running at a minimum bus cycle time of 83.3ns, integrates on a single chip a number of hardware features such as 16K-byte flash ROM (onboard programmable), 1024-byte RAM, an on-chip debugger, a sophisticated 16-bit timer/counter (may be divided into 8-bit timers), a 16-bit timer (may be divided into 8-bit timers or 8-bit PWMs), four 8-bit timers with a prescaler, a base timer serving as a timeof-day clock, two channels of synchronous SIO interface (with automatic block transmission/reception capabilities), an asynchronous/synchronous SIO interface, a UART interface (full duplex), a UART interface with Smartcard interface function (full duplex), a full-speed USB interface (function), a 12-bit 20-channel AD converter (12- or 8-bit resolution selectable), 2 channels of 12-bit PWM, a system clock frequency divider, an internal reset and a 35-source 10-vector interrupt feature. Features Flash ROM • Capable of on-board programming with a wide range of supply voltages: 3.0 to 5.5V • Block-erasable in 128 byte units • Writes data in 2-byte units • 16384 × 8 bits RAM • 1024 × 9 bits Bus Cycle Time • 83.3ns (When CF=12MHz) Note: The bus cycle time here refers to the ROM read speed. * This product is licensed from Silicon Storage Technology, Inc. (USA), and manufactured and sold by SANYO Semiconductor Co., Ltd. Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment (home appliances, AV equipment, communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee thereof. If you should intend to use our products for applications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our customer shall be solely responsible for the use. Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer' s products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer' s products or equipment. Ver.2.01 42011HKIM 20110311-S00003 No.A1909-1/32 LC87F1M16A Minimum Instruction Cycle Time (tCYC) • 250ns (When CF=12MHz) Ports • I/O ports Ports whose I/O direction can be designated in 1-bit units 35 (P00 to P07, P10 to P17, P20 to P27, P31 to P34, P70 to P73, PWM0, PWM1, XT2) • USB ports 2 (D+, D-) • Dedicated oscillator ports 2 (CF1, CF2) • Input-only port (also used for oscillation) 1 (XT1) • Reset pins 1 (RES) • Dedicated debugger port 1 (OWP0) • Power supply pins 6 (VSS1 to 3, VDD1 to 3) Timers • Timer 0: 16-bit timer/counter with 2 capture registers. Mode 0: 8-bit timer with an 8-bit programmable prescaler (with two 8-bit capture registers) × 2 channels Mode 1: 8-bit timer with an 8-bit programmable prescaler (with two 8-bit capture registers) + 8-bit counter (with two 8-bit capture registers) Mode 2: 16-bit timer with an 8-bit programmable prescaler (with two 16-bit capture registers) Mode 3: 16-bit counter (with two 16-bit capture registers) • Timer 1: 16-bit timer/counter that supports PWM/toggle outputs Mode 0: 8-bit timer with an 8-bit prescaler (with toggle outputs) + 8-bit timer/ counter with an 8-bit prescaler (with toggle outputs) Mode 1: 8-bit PWM with an 8-bit prescaler × 2 channels Mode 2: 16-bit timer/counter with an 8-bit prescaler (with toggle outputs) (toggle outputs also possible from lower-order 8 bits) Mode 3: 16-bit timer with an 8-bit prescaler (with toggle outputs) (lower-order 8 bits may be used as a PWM output) • Timer 4: 8-bit timer with a 6-bit prescaler • Timer 5: 8-bit timer with a 6-bit prescaler • Timer 6: 8-bit timer with a 6-bit prescaler (with toggle outputs) • Timer 7: 8-bit timer with a 6-bit prescaler (with toggle outputs) • Base timer (1) The clock is selectable from the subclock (32.768kHz crystal oscillation), system clock, and timer 0 prescaler output. (2) Interrupts programmable in 5 different time schemes SIO • SIO0: Synchronous serial interface (1) LSB first/MSB first mode selectable (2) Transfer clock cycle: 4/3 to 512/3 tCYC (3) Automatic continuous data transmission (1 to 256 bits, specifiable in 1-bit units) (Suspension and resumption of data transmission possible in 1 byte units) • SIO1: 8-bit asynchronous/synchronous serial interface Mode 0: Synchronous 8-bit serial I/O (2- or 3-wire configuration, 2 to 512 tCYC transfer clocks) Mode 1: Asynchronous serial I/O (half-duplex, 8 data bits, 1 stop bit, 8 to 2048 tCYC baudrates) Mode 2: Bus mode 1 (start bit, 8 data bits, 2 to 512 tCYC transfer clocks) Mode 3: Bus mode 2 (start detect, 8 data bits, stop detect) • SIO4: Synchronous serial interface (1) LSB first/MSB first mode selectable (2) Transfer clock cycle: 4/3 to 1020/3 tCYC (3) Automatic continuous data transmission (1 to 1024 bytes, specifiable in 1 byte units, suspension and resumption of data transmission possible in 1 byte or 2 bytes units) (4) Clock polarity selectable (5) CRC16 calculator circuit built in No.A1909-2/32 LC87F1M16A Full Duplex UART • UART1 (1) Data length : 7/8/9 bits selectable (2) Stop bits : 1 bit (2 bits in continuous transmission mode) (3) Baud rate : 16/3 to 8192/3 tCYC • SCUART (1) Data length : 7/8 bits selectable (2) Stop bits : 1/2 bits selectable (3) Parity bits : None/even parity/odd parity (4) Baud rate : 8/3 to 8192/3 tCYC (5) LSB first/MSB first mode delectable (6) Smartcard interface function AD Converter: 12 bits × 20 channels • 12-/8-bit resolution selectable AD converter PWM: Multifrequency 12-bit PWM × 2 channels USB Interface (function controller) (1) Compliant with USB 2.0 Full-Speed (2) Supports a maximum of 6 user-defined endpoints. Endpoint Transfer Type Control Bulk Interrupt Isochronous Max. payload 64 64 64 64 64 64 64 EP0 EP1 EP2 EP3 EP4 EP5 EP6 - Watchdog Timer • Internal counter watchdog timer (1) Generates an internal reset on an overflow occurring in the timer running on the low-speed RC oscillator clock (approx. 30kHz) or subclock. (2) Operating mode at HALT/HOLD mode is selectable from 3 modes (continue counting/suspend operation/suspend counting with the count value retained) Clock Output Function (1) Can output a clock with a clock rate of 1/1, 1/2, 1/4, 1/8, 1/16, 1/32, or 1/64 of the source oscillator clock selected as the system clock. (2) Can output the source oscillation clock for the subclock. No.A1909-3/32 LC87F1M16A Interrupts • 35 sources, 10 vector addresses (1) Provides three levels (low (L), high (H), and highest (X)) of multiplex interrupt control. Any interrupt requests of the level equal to or lower than the current interrupt are not accepted. (2) When interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest level takes precedence over the other interrupts. For interrupts of the same level, the interrupt into the smallest vector address takes precedence. No. 1 2 3 4 5 6 7 Vector Address 00003H 0000BH 00013H 0001BH 00023H 0002BH 00033H Level X or L X or L H or L H or L H or L H or L H or L INT0 INT1 INT2/T0L/INT4/USB bus active INT3/INT5/base timer T0H/INT6 T1L/T1H/INT7 SIO0/USB bus reset/USB suspend/UART1 receive complete/ SCUART receive complete SIO1/USB endpoint/USB-SOF/SIO4/ 8 9 10 0003BH 00043H 0004BH H or L H or L H or L UART1 buffer empty/UART1 transmit complete/ SCUART buffer empty/SCUART transmit complete ADC/T6/T7 Port 0/PWM0/PWM1/T4/T5 Interrupt Source • Priority levels X > H > L • Of interrupts of the same level, the one with the smallest vector address takes precedence. Subroutine Stack Levels: 512 levels maximum (The stack is allocated in RAM.) High-speed Multiplication/Division Instructions • 16 bits × 8 bits ( 5 tCYC execution time) • 24 bits × 16 bits (12 tCYC execution time) • 16 bits ÷ 8 bits ( 8 tCYC execution time) • 24 bits ÷ 16 bits (12 tCYC execution time) Oscillation and PLL Circuits • RC oscillation circuit (internal) • Low-speed RC oscillation circuit (internal) • CF oscillation circuit • Crystal oscillation circuit • PLL circuit (internal) : For system clock (approx. 1MHz) : For watchdog timer (approx. 30kHz) : For system clock : For system clock, time-of-day clock : For USB interface (see Fig.5) Internal Reset Circuit •Power-on reset (POR) function (1) POR reset is generated only at power-on time. (2) The POR release level can be selected from 4 levels (2.57V, 2.87V, 3.86V and 4.35V) through option configuration. •Low-voltage detection reset (LVD) function (1) LVD and POR functions are combined to generate resets when power is turned on and when power voltage falls below a certain level. (2) The use/disuse of the LVD function and the voltage threshold level can be selected from 3 levels (2.81V, 3.79V and 4.28V) through option configuration. No.A1909-4/32 LC87F1M16A Standby Function • HALT mode: Halts instruction execution while allowing the peripheral circuits to continue operation. (1) Oscillation is not halted automatically. (2) There are three ways of resetting the HOLD mode. 1) Setting the reset pin to the lower level 2) Having the watchdog timer or LVD function generate a reset 3) Having an interrupt generated • HOLD mode: Suspends instruction execution and the operation of the peripheral circuits. (1) The PLL base clock generator, CF, RC and crystal oscillators automatically stop operation. Note: The low-speed RC oscillator is controlled directly by the watchdog timer; its oscillation in the standby mode is also controlled by the watchdog timer. (2) There are five ways of resetting the HOLD mode. 1) Setting the reset pin to the lower level 2) Having the watchdog timer or LVD function generate a reset 3) Having an interrupt source established at one of the INT0, INT1, INT2, INT4 or INT5 pins * INT0 and INT1 HOLD mode reset is available only when level detection is set. 4) Having an interrupt source established at port 0 5) Having an bus active interrupt source established in the USB interface circuit • X'tal HOLD mode: Suspends instruction execution and the operation of the peripheral circuits except the base timer. (1) The PLL base clock generator, CF and RC oscillator automatically stop operation. Note: The low-speed RC oscillator is controlled directly by the watchdog timer; its oscillation in the standby mode is also controlled by the watchdog timer. (2) The state of crystal oscillation established when the X'tal HOLD mode is entered is retained. (3) There are six ways of resetting the X'tal HOLD mode. 1) Setting the reset pin to the low level 2) Having the watchdog timer or LVD function generate a reset 3) Having an interrupt source established at either INT0, INT1, INT2, INT4 or INT5 * INT0 and INT1 HOLD mode reset is available only when level detection is set. 4) Having an interrupt source established at port 0 5) Having an interrupt source established in the base timer circuit 6) Having an bus active interrupt source established in the USB interface circuit Package Form • SQFP48 (7×7): Lead-/Halogen-free type Development Tools • On-chip debugger: TCB87 type-C (one wire communication cable) + LC87F1M16A No.A1909-5/32 LC87F1M16A Flash ROM Programming Boards Package SQFP48(7×7) Programming boards W87F55256SQ Flash Programmer Maker Flash Support Group, Inc. (FSG) Flash Support Group, Inc. (FSG) + Sanyo (Note 1) Single/Gang Programmer Sanyo Onboard Single/Gang Programmer SKK/SKK Type B (SanyoFWS) SKK-DBG Type C (SanyoFWS) Application Version 1.06 or later Chip Data Version 2.31 or later LC87F1M16 Onboard Single/Gang Programmer Single Programmer Model AF9709/AF9709B/AF9709C (Including Ando Electric Co., Ltd. models) AF9101/AF9103(Main unit) (FSG models) SIB87(Inter Face Driver) (Sanyo model) (Note 2) LC87F1M16A Rev 03.32 or later 87F016JU Supported version Device For information about AF-Series: Flash Support Group, Inc. TEL: +81-53-459-1050 E-mail: sales@j-fsg.co.jp Note1: On-board-programmer from FSG (AF9101/AF9103) and serial interface driver from SANYO (SIB87) together can give a PC-less, standalone on-board-programming capabilities. Note2: It needs a special programming devices and applications depending on the use of programming environment. Please ask FSG or SANYO for the information. No.A1909-6/32 LC87F1M16A Package Dimensions unit : mm (typ) 3163B 9.0 7.0 36 37 25 24 48 1 0.5 (0.75) 12 0.18 13 7.0 9.0 0.15 1.7max 0.1 (1.5) SANYO : SQFP48(7X7) DD+ VDD3 VSS3 P34/UFILT P33 P32/SCRX P31/SCTX OWP0 P70/INT0/T0LCP/DPUP P71/INT1/T0HCP P72/INT2/T0IN 37 38 39 40 41 42 43 44 45 46 47 48 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 P27/INT5/AN19/DPUP2 P26/INT5/AN18 P25/INT5/AN17 P24/INT5/INT7/AN16/SCK4 P23/INT4/AN15/SI4 P22/INT4/AN14/SO4 P21/INT4/AN13/URX1 P20/INT4/INT6/AN12/UTX1 P07/AN7/T7O P06/AN6/T6O P05/AN5/CKO P04/AN4 Pin Assignment 0.5 LC87F1M16A P03/AN3 P02/AN2/TDN2 P01/AN1/TDP1 P00/AN0/TDN1 VSS2 VDD2 PWM0/AN9/TDP0 PWM1/AN8/TDN0 P17/T1PWMH/BUZ P16/T1PWML P15/SCK1 P14/SI1/SB1 P73/INT3/T0IN RES XT1/AN10 XT2/AN11 VSS1 CF1 CF2 VDD1 P10/SO0 P11/SI0/SB0 P12/SCK0 P13/SO1 1 2 3 4 5 6 7 8 9 10 11 12 Top view SANYO: SQFP48(7×7) “Lead-/Halogen-free Type” No.A1909-7/32 LC87F1M16A SQFP48 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 NAME P73/INT3/T0IN RES XT1/AN10 XT2/AN11 VSS1 CF1 CF2 VDD1 P10/SO0 P11/SI0/SB0 P12/SCK0 P13/SO1 P14/SI1/SB1 P15/SCK1 P16/T1PWML P17/T1PWMH/BUZ PWM1/AN8/TDN0 PWM0/AN9/TDP0 VDD2 VSS2 P00/AN0/TDN1 P01/AN1/TDP1 P02/AN2/TDN2 P03/AN3 SQFP48 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 NAME P04/AN4 P05/AN5/CKO P06/AN6/T6O P07/AN7/T7O P20/INT4/INT6/AN12/UTX1 P21/INT4/AN13/URX1 P22/INT4/AN14/SO4 P23/INT4/AN15/SI4 P24/INT5/INT7/AN16/SCK4 P25/INT5/AN17 P26/INT5/AN18 P27/INT5/AN19/DPUP2 DD+ VDD3 VSS3 P34/UFILT P33 P32/SCRX P31/SCTX OWP0 P70/INT0/T0LCP/DPUP P71/INT1/T0HCP P72/INT2/T0IN No.A1909-8/32 LC87F1M16A System Block Diagram Interrupt control IR PLA Standby control FROM CF RC X’tal USB PLL Clock generator PC SIO0 Bus interface Port 0 ACC SIO1 B register SIO4 Port 1 C register Timer 0 Port 2 ALU Timer 1 Port 3 Timer 4 Port 7 INT0 to INT7 Noise filter UART1 SCUART PSW Timer 5 RAR Timer 6 RAM Timer 7 Stack pointer Base timer ADC Watchdog timer PWM0 USB interface On-chip debugger PWM1 High current driver No.A1909-9/32 LC87F1M16A Pin Description Pin Name VSS1,VSS2, VSS3 VDD1, VDD2 VDD3 Port 0 P00 to P07 I/O - Power supply Description No Option I/O + Power supply USB reference voltage • 8-bit I/O ports • I/O specifiable in 1-bit units • Pull-up resistors can be turned on and off in 1-bit units • HOLD reset input • Port 0 interrupt input • Pin functions AD converter input ports: AN0 to AN7(P00 to P07) P00: High current Nch driver(TDN1) P01: High current Pch driver(TDP1) P02: High current Nch driver(TDN2) P05: System clock output P06: Timer 6 toggle output P07: Timer 7 toggle output No Yes Yes Port 1 P10 to P17 I/O • 8-bit I/O port • I/O specifiable in 1-bit units • Pull-up resistors can be turned on and off in 1-bit units • Pin functions P10: SIO0 data output P11: SIO0 data input/bus I/O P12: SIO0 clock I/O P13: SIO1 data output P14: SIO1 data input/bus I/O P15: SIO1 clock I/O P16: Timer 1 PWML output P17: Timer 1 PWMH output/beeper output Yes Port 2 P20 to P27 I/O • 8-bit I/O ports • I/O specifiable in 1-bit units • Pull-up resistors can be turned on and off in 1-bit units • Pin functions AD converter input ports: AN12 to AN19(P20 to P27) P20 to P23: INT4 input/HOLD reset input/timer 1 event input/timer 0L capture input/ timer 0H capture input P24 to P27: INT5 input/HOLD reset input/timer 1 event input/timer 0L capture input/ timer 0H capture input P20: INT6 input/timer 0L capture 1 input/UART1 transmit P21: UART1 receive P22: SIO4 date I/O P23: SIO4 date I/O P24: INT7 input/timer 0H capture 1 input/SIO4 clock I/O P27: D+ 1.5kΩ pull-up resistor connect pin Interrupt acknowledge types Rising INT4 INT5 INT6 INT7 • 4-bit I/O ports • I/O specifiable in 1-bit units • Pull-up resistors can be turned on and off in 1-bit units • Pin functions P31: SCUART transmit P32: SCUART receive P34: USB interface PLL filter pin (see Fig. 5.) enable enable enable enable Falling enable enable enable enable Rising & Falling enable enable enable enable H level disable disable disable disable L level disable disable disable disable Yes Port 3 P31 to P34 I/O Yes Continued on next page. No.A1909-10/32 LC87F1M16A Continued from preceding page. Pin Name Port 7 P70 to P73 I/O I/O • 4-bit I/O port • I/O specifiable in 1-bit units • Pull-up resistors can be turned on and off in 1-bit units • Pin functions P70: INT0 input/HOLD reset input/timer 0L capture input/ D+ 1.5kΩ pull-up resistor connect pin P71: INT1 input/HOLD reset input/timer 0H capture input P72: INT2 input/HOLD reset input/timer 0 event input/timer 0L capture input/ high speed clock counter input P73: INT3 input (input with noise filter)/timer 0 event input/timer 0H capture input Interrupt acknowledge types Rising INT0 INT1 INT2 INT3 enable enable enable enable Falling enable enable enable enable Rising & Falling disable disable enable enable H level enable enable disable disable L level enable enable disable disable Description Option No PWM0 PWM1 I/O • PWM0, PWM1 output port • Pin functions General-purpose input ports AD converter input ports: AN8(PWM1), AN9(PWM0) PWM0: High current Pch driver(TDP0) PWM1: High current Nch driver(TDN0) No DD+ RES XT1 I/O I/O Input Input • USB data I/O pin D• General-purpose I/O port • USB data I/O pin D+ • General-purpose I/O port External reset input/internal reset output pin • 32.768kHz crystal oscillator input • Pin functions General-purpose input port AD converter input ports: AN10 No No No No XT2 I/O • 32.768kHz crystal oscillator output • Pin functions General-purpose I/O AD converter input port: AN11 No CF1 CF2 OWP0 Input Output I/O Ceramic resonator input Ceramic resonator output Dedicated debugger port No No No No.A1909-11/32 LC87F1M16A On-chip Debugger Pin Connection Requirements For the treatment of the on-chip debugger pins, refer to the separately available documents entitled “Rd87 On-chip Debugger Installation Manual” Recommended Unused Pin Connections Port Name Board P00 to P07 P10 to P17 P20 to P27 P31 to P34 P70 to P73 PWM0, PWM1 D+, DXT1 XT2 OWP0 Open Open Open Open Open Open Open Pulled low with a 100kΩ resistor or less Open Pulled low with a 100kΩ resistor Output low Output low Output low Output low Output low Output low Output low Output low Recommended Unused Pin Connections Software Note: P34 and UFILT share the same pin, so if USB function is used, the pin must be set to input mode. Port Output Types The table below lists the types of port outputs and the presence/absence of a pull-up resistor. Data can be read into any input port even if it is in the output mode. Port Name P00 to P07 P10 to P17 P20 to P27 P31 to P34 P70 P71 to P73 PWM0, PWM1 D+, DXT1 XT2 No No No No No No Nch-open drain CMOS CMOS CMOS Input only 32.768kHz crystal resonator output (N channel open drain when in general-purpose output mode) Programmable Programmable No No No No 2 Nch-open drain Programmable Option selected in units of 1 bit Option type 1 CMOS Output type Pull-up resistor Programmable No.A1909-12/32 LC87F1M16A User Option Table Option Name Port output form P00 to P07 enable 1 bit Option Type Flash Version Option Selected in Units of CMOS Nch-open drain CMOS P10 to P17 enable 1 bit Nch-open drain CMOS P20 to P27 enable 1 bit Nch-open drain CMOS P31 to P34 Program start address USB Regulator USB Regulator USB Regulator (at HOLD mode) USB Regulator (at HALT mode) Main clock 8MHz selection Low-voltage detection reset function Detect function Detect level Power-on reset function Power-On reset level enable enable enable enable enable enable enable 1 bit Nch-open drain 00000h 03E00h USE NONUSE USE enable NONUSE USE enable NONUSE ENABLE DISABLE Enable: Use Disable: Not Used 3-level 4-level Option Selection No.A1909-13/32 LC87F1M16A USB Reference Power Option When a voltage 4.5 to 5.5V is supplied to VDD1 and the internal USB reference voltage circuit is activated, the reference voltage for USB port output is generated. The active/inactive state of the reference voltage circuit can be switched by option select. The procedure for marking the option selection is described below. (1) Option settings USB regulator USB regulator at HOLD mode USB regulator at HALT mode Reference voltage circuit state Normal mode HOLD mode HALT mode USE USE USE active active active (2) USE NONUSE NONUSE active inactive inactive (3) USE NONUSE USE active inactive active (4) NONUSE NONUSE NONUSE inactive inactive inactive • When the USB reference voltage circuit is made inactive, the level of the reference voltage for USB port output is equal to VDD1. • Selection (2) or (3) can be used to set the reference voltage circuit inactive in HOLD or HALT mode. • When the reference voltage circuit is activated, the current drain increases by approximately 100μA compared with when the reference voltage circuit is inactive. Example 1: VDD1=VDD2=3.3V • Inactivating the reference voltage circuit (selection (4)). • Connecting VDD3 to VDD1 and VDD2. LSI P70/P27 1.5kΩ VDD1 D+ D5pF 0Ω VSS1 VSS2 VSS3 2.2μF 27 to 33Ω To USB connector Power supply 3.3V VDD2 VDD3 UFILT 2.2μF Example 2: VDD1=VDD2=5.0V • Activating the reference voltage circuit (selection (1)). • Isolating VDD3 from VDD1 and VDD2, and connecting capacitor between VDD3 and VSS. LSI P70/P27 1.5kΩ Power supply 5V VDD1 D+ DVDD2 5pF 2.2μF 0.1µF VSS1 VSS2 VSS3 2.2μF VDD3 UFILT 0Ω 27 to 33Ω To USB connector No.A1909-14/32 LC87F1M16A Absolute Maximum Ratings at Ta = 25°C, VSS1 = VSS2 = VSS3 = 0V Parameter Maximum supply voltage Input voltage Input/output voltage Peak output current IOPH(2) IOPH(3) IOPH(1) VI(1) VIO(1) XT1, CF1, RES Ports 0, 1, 2, 3, 7 PWM0, PWM1 XT2 P00, P02 to P07 Ports 1, 2 PWM1 PWM0(TDP0) P01(TDP1) IOPH(4) Port 3 P71 to P73 Average output current High level output current (Note 1-1) IOMH(2) IOMH(3) PWM1 PWM0(TDP0) P01(TDP1) IOMH(4) Port 3 P71 to P73 Total output current ΣIOAH(2) ΣIOAH(3) ΣIOAH(4) ΣIOAH(5) ΣIOAH(6) ΣIOAH(1) P00, P02 to P07 Ports 2 Port 1 PWM1 PWM0(TDP0) P01(TDP1) Ports 0, 1, 2 PWM0, PWM1 Port 3 P71 to P73 D+, DIOMH(1) P00, P02 to P07 Ports 1, 2 • When CMOS output type is selected • Per 1 applicable pin Per 1 applicable pin • When CMOS output type is selected • Per 1 applicable pin • When CMOS output type is selected • Per 1 applicable pin • When CMOS output type is selected • Per 1 applicable pin Per 1 applicable pin • When CMOS output type is selected • Per 1 applicable pin • When CMOS output type is selected • Per 1 applicable pin Total current of all applicable pins Total current of all applicable pins Total current of all applicable pins Total current of all applicable pins Total current of all applicable pins Total current of all applicable pins -25 -25 -50 -100 -10 -25 -3 -30 mA -15 -7.5 -5 -50 -20 -10 -0.3 VDD+0.3 Symbol VDD max Pin/Remarks VDD1, VDD2, VDD3 Conditions VDD[V] VDD1= VDD2= VDD3 min -0.3 -0.3 Specification typ max +6.5 VDD+0.3 V unit Note 1-1: The average output current is an average of current values measured over 100ms intervals. Continued on next page. No.A1909-15/32 LC87F1M16A Continued from preceding page. Parameter Peak output current IOPL(2) IOPL(3) Symbol IOPL(1) Pin/Remarks P03 to P07 Ports 1, 2 PWM0 P01 PWM1(TDN0) P00(TDN1) P02(TDN2) IOPL(4) Average output current (Note 1-1) Low level output current IOML(2) IOML(3) IOML(1) Ports 3, 7 XT2 P03 to P07 Ports 1, 2 PWM0 P01 PWM1(TDN0) P00(TDN1) P02(TDN2) IOML(4) Total output current ΣIOAL(2) ΣIOAL(3) ΣIOAL(1) Ports 3, 7 XT2 P01, P03 to P07 Ports 2 Port 1 PWM0 PWM1(TDN0) P00(TDN1) P02(TDN2) ΣIOAL(4) ΣIOAL(5) ΣIOAL(6) Allowable power Dissipation Operating ambient Temperature Storage ambient temperature Tstg Topr Pd max Ports 0, 1, 2 PWM0, PWM1 Ports 3, 7 XT2 D+, DSQFP48(7×7) Total current of all applicable pins Total current of all applicable pins Total current of all applicable pins Ta=-30 to +70°C Ta=-40 to +85°C -40 -55 140 15 25 190 140 +85 °C +125 Total current of all applicable pins Total current of all applicable pins Total current of all applicable pins 50 Per 1 applicable pin 7.5 45 45 Per 1 applicable pin Per 1 applicable pin 30 mA 20 Per 1 applicable pin 15 Per 1 applicable pin 10 Per 1 applicable pin Per 1 applicable pin 50 30 Conditions VDD[V] Per 1 applicable pin 20 min Specification typ max unit mW Note 1-1: The average output current is an average of current values measured over 100ms intervals. No.A1909-16/32 LC87F1M16A Allowable Operating Conditions at Ta = -40°C to +85°C, VSS1 = VSS2 = VSS3 = 0V Parameter Operating supply voltage (Note 2-1) Symbol VDD(1) Pin/Remarks VDD1=VDD2=VDD3 Conditions 0.245μs ≤ tCYC ≤ 200μs 0.490μs ≤ tCYC ≤ 200μs Except in onboard programming mode 0.245μs ≤ CYC ≤ 0.383μs USB circuit active Memory sustaining supply voltage High level input voltage VIH(2) Low level input voltage VIL(2) VIL(3) VIL(4) VIL(5) Instruction cycle time (Note 2-2) tCYC Except for onboard programming mode USB circuit active External system clock frequency FEXCF(1) CF1 • CF2 pin open • System clock frequency division ratio=1/1 • External system clock duty =50±5% • CF2 pin open • System clock frequency division ratio=1/1 • External system clock duty =50±5% Oscillation frequency range (Note 2-3) FmRC FmSLRC FsX’tal XT1, XT2 FmCF CF1, CF2 When 12MHz ceramic oscillation See Fig. 1. Internal RC oscillation Internal low-speed RC oscillation 32.768kHz crystal oscillation See Fig. 2. 3.0 to 5.5 2.7 to 5.5 2.7 to 5.5 2.7 to 5.5 0.5 15 12 1.0 30 32.768 2.0 60 kHz MHz 2.7 to 5.5 0.1 6 MHz 3.0 to 5.5 0.1 12 XT1, XT2, CF1,RES Port 0 PWM0, PWM1 VIL(1) VIH(1) Port 0, 1, 2, 3, 7 PWM0, PWM1 XT1, XT2, CF1,RES Port 1, 2, 3, 7 2.7 to 5.5 2.7 to 5.5 4.0 to 5.5 2.7 to 4.0 4.0 to 5.5 2.7 to 4.0 2.7 to 5.5 3.0 to 5.5 2.7 to 5.5 3.0 to 5.5 0.3VDD +0.7 0.75VDD VSS VSS VSS VSS VSS 0.245 0.490 0.245 VDD VDD 0.1VDD +0.4 0.2VDD 0.15VDD +0.4 0.2VDD 0.25VDD 200 200 0.383 μs V VHD VDD1=VDD2=VDD3 RAM and register contents sustained in HOLD mode. 2.0 5.5 Specification VDD[V] min 3.0 2.7 3.0 typ max 5.5 5.5 5.5 unit Note 2-1: VDD must be held greater than or equal to 3.0V in the flash ROM onboard programming mode. Note 2-2: Relationship between tCYC and oscillation frequency is 3/FmCF at a division ratio of 1/1 and 6/FmCF at a division ratio of 1/2. Note 2-3: See Tables 1 and 2 for the oscillation constants. No.A1909-17/32 LC87F1M16A Electrical Characteristics at Ta = -40°C to +85°C, VSS1 = VSS2 = VSS3 = 0V Parameter High level input current Symbol IIH(1) Pin/Remarks Ports 0, 1, 2, 3, 7 RES PWM0, PWM1 D+, DIIH(2) IIH(3) Low level input current IIL(1) XT1, XT2 Conditions VDD[V] Output disabled Pull-up resistor off VIN=VDD (Including output Tr's off leakage current) Input port configuration VIN=VDD CF1 Ports 0, 1, 2, 3, 7 RES PWM0, PWM1 D+, DIIL(2) IIL(3) High level output voltage VOH(1) VOH(2) VOH(3) VOH(4) VOH(5) VOH(6) VOH(7) PWM0, WM1 P05(CKO when using system clock output function) PWM0, P01 (when using high current driver) Low level output voltage VOL(1) VOL(2) VOL(3) VOL(4) VOL(5) VOL(6) VOL(7) VOL(8) VOL(9) PWM1, P00, P02 (when using high current driver) Pull-up resistance Rpu(1) Rpu(2) Hysteresis voltage Pin capacitance VHYS CP RES Port 1, 2, 3, 7 All pins For pins other than that under test: VIN=VSS f=1MHz Ta=25°C 2.7 to 5.5 10 pF Ports 0, 1, 2, 3, 7 VOH=0.9VDD 4.5 to 5.5 2.7 to 5.5 2.7 to 5.5 15 18 35 50 0.1VDD 80 150 kΩ V Ports 0, 1, 2 PWM0, PWM1 XT2 Ports 3, 7 P00, P01 IOL=30mA IOL=5mA IOL=2.5mA IOL=10mA IOL=1.6mA IOL=1mA IOL=1.6mA IOL=1mA IOL=30mA 4.5 to 5.5 0.15 0.5 4.5 to 5.5 3.0 to 5.5 2.7 to 5.5 4.5 to 5.5 3.0 to 5.5 2.7 to 5.5 3.0 to 5.5 2.7 to 5.5 1.5 0.4 0.4 1.5 0.4 0.4 0.4 0.4 V XT1, XT2 VIN=VDD Output disabled Pull-up resistor off VIN=VSS (Including output Tr's off leakage current) Input port configuration VIN=VSS CF1 Ports 0, 1, 2, 3 P71 to P73 VIN=VSS IOH=-1mA IOH=-0.4mA IOH=-0.2mA IOH=-10mA IOH=-1.6mA IOH=-1mA IOH=-30mA 4.5 to 5.5 VDD-0.5 VDD-0.15 2.7 to 5.5 2.7 to 5.5 4.5 to 5.5 3.0 to 5.5 2.7 to 5.5 4.5 to 5.5 3.0 to 5.5 2.7 to 5.5 -1 -15 VDD-1 VDD-0.4 VDD-0.4 VDD-1.5 VDD-0.4 VDD-0.4 2.7 to 5.5 -1 2.7 to 5.5 2.7 to 5.5 1 15 μA 2.7 to 5.5 1 min Specification typ max unit No.A1909-18/32 LC87F1M16A Serial I/O Characteristics at Ta = -40°C to +85°C, VSS1 = VSS2 = VSS3 = 0V 1. SIO0 Serial I/O Characteristics (Note 4-1-1) Parameter Frequency Low level pulse width High level pulse width tSCKHA(1a) • Continuous data transmission/ reception mode • USB nor SIO4 are not in use simultaneous. Input clock • See Fig. 8. • (Note 4-1-2) tSCKHA(1b) • Continuous data transmission/ reception mode • USB is in use simultaneous • SIO4 is not in use simultaneous. • See Fig. 8. • (Note 4-1-2) tSCKHA(1c) • Continuous data transmission/ reception mode • USB and SIO4 are in use simultaneous. Serial clock • See Fig. 8. • (Note 4-1-2) Frequency Low level pulse width High level pulse width tSCKHA(2a) • Continuous data transmission/ reception mode • USB nor SIO4 are not in use simultaneous. Output clock • CMOS output selected • See Fig. 8. tSCKHA(2b) • Continuous data transmission/ reception mode • USB is in use simultaneous • SIO4 is not in use simultaneous. • CMOS output selected • See Fig. 8. tSCKHA(2c) • Continuous data transmission/ reception mode • USB and SIO4 are in use simultaneous. • CMOS output selected • See Fig. 8. tSCKH(2) +2tCYC tSCKH(2) +(25/3) tCYC tSCKH(2) +2tCYC 2.7 to 5.5 tSCKH(2) +(19/3) tCYC tCYC tSCKH(2) +2tCYC tSCKH(2) +(10/3) tCYC tSCKH(2) tSCK(2) tSCKL(2) SCK0(P12) • CMOS output selected • See Fig. 8. 4/3 1/2 tSCK 1/2 9 7 2.7 to 5.5 tCYC 4 tSCKH(1) Symbol tSCK(1) tSCKL(1) Pin/ Remarks SCK0(P12) See Fig. 8. Conditions VDD[V] min 2 1 1 Specification typ max unit Note 4-1-1: These specifications are theoretical values. Add margin depending on its use. Note 4-1-2: To use serial-clock-input in continuous trans/rec mode, a time from SI0RUN being set when serial clock is "H" to the first negative edge of the serial clock must be longer than tSCKHA. Continued on next page. No.A1909-19/32 LC87F1M16A Continued from preceding page. Parameter Data setup time Serial input Symbol tsDI(1) Pin/ Remarks SB0(P11), SI0(P11) Data hold time thDI(1) Conditions VDD[V] • Must be specified with respect to rising edge of SIOCLK. • See Fig. 8. 2.7 to 5.5 0.03 Output delay Input clock time tdD0(2) tdD0(1) SO0(P10), SB0(P11) • Continuous data transmission/ reception mode • (Note 4-1-3) • Synchronous 8-bit mode • (Note 4-1-3) 2.7 to 5.5 tdD0(3) Output clock (Note 4-1-3) (1/3)tCYC +0.05 0.03 min Specification typ max unit (1/3)tCYC +0.05 1tCYC +0.05 μs Note 4-1-3: Must be specified with respect to falling edge of SIOCLK. Must be specified as the time to the beginning of output state change in open drain output mode. See Fig. 8. 2. SIO1 Serial I/O Characteristics (Note 4-2-1) Parameter Frequency Input clock Low level pulse width High level pulse width Frequency Output clock Low level pulse width High level pulse width Data setup time Serial input tsDI(2) SB1(P14), SI1(P14) Data hold time thDI(2) • Must be specified with respect to rising edge of SIOCLK. • See Fig. 8. 2.7 to 5.5 0.01 Output delay time Serial output tdD0(4) SO1(P13), SB1(P14) • Must be specified with respect to falling edge of SIOCLK. • Must be specified as the time to the beginning of output state change in open drain output mode. • See Fig. 8. 2.7 to 5.5 (1/2)tCYC +0.05 μs (1/3)tCYC +0.01 tSCKH(4) tSCK(4) tSCKL(4) SCK1(P15) • When CMOS output type is selected • See Fig. 8. 2.7 to 5.5 tSCKH(3) Symbol tSCK(3) tSCKL(3) Pin/ Remarks SCK1(P15) See Fig. 8. Conditions VDD[V] min 2 2.7 to 5.5 1 tCYC 1 2 1/2 tSCK 1/2 Specification typ max unit Note 4-2-1: These specifications are theoretical values. Add margin depending on its use. Serial clock Serial output No.A1909-20/32 LC87F1M16A 3. SIO4 Serial I/O Characteristics (Note 4-3-1) Parameter Frequency Low level pulse width High level pulse width tSCKHA(5a) • USB nor continuous data transmission/reception mode of SIO0 are not in use simultaneous. Input clock • See Fig.8. • (Note 4-3-2) tSCKHA(5b) • USB is in use simultaneous. • Do not use SIO0 continuous data transmission mode at the same time. • See Fig.8. • (Note 4-3-2) tSCKHA(5c) • USB and continuous data transmission/ reception mode of SIO0 are in use simultaneous. Serial clock • See Fig.8. • (Note 4-3-2) Frequency Low level pulse width High level pulse width tSCKHA(6a) • USB nor continuous data transmission/reception mode of SIO0 are not in use simultaneous. Output clock • CMOS output selected • See Fig.8. tSCKHA(6b) • USB is in use simultaneous. • Do not use SIO0 continuous data transmission mode at the same time. • CMOS output selected • See Fig8. tSCKHA(6c) • USB and continuous data transmission/reception mode of SIO0 are in use simultaneous. • CMOS output selected • See Fig.8. Data setup time Serial input tsDI(3) SO4(P22), SI4(P23) Data hold time thDI(3) 2.7 to 5.5 0.03 • Must be specified with respect to rising edge of SIOCLK. • See Fig.8. 2.7 to 5.5 0.03 μs tSCKH(6) +(5/3) tCYC tSCKH(6) +(28/3) tCYC 2.7 to 5.5 tSCKH(6) +(5/3) tCYC tSCKH(6) +(19/3) tCYC tCYC tSCKH(6) +(5/3) tCYC tSCKH(6) +(10/3) tCYC tSCKH(6) tSCK(6) tSCKL(6) SCK4(P24) • CMOS output selected • See Fig.8 4/3 1/2 tSCK 1/2 10 7 2.7 to 5.5 tCYC 4 tSCKH(5) Symbol tSCK(5) tSCKL(5) Pin/ Remarks SCK4(P24) See Fig.8. Conditions VDD[V] min 2 1 1 Specification typ max unit Note 4-3-1: These specifications are theoretical values. Add margin depending on its use. Note 4-3-2: To use serial-clock-input in continuous trans/rec mode, a time from SI4RUN being set when serial clock is "H" to the first negative edge of the serial clock must be longer than tSCKHA. Continued on next page. No.A1909-21/32 LC87F1M16A Continued from preceding page. Parameter Output delay time Serial output Symbol tdD0(5) Pin/ Remarks SO4(P22), SI4(P23) Conditions VDD[V] • Must be specified with respect to rising edge of SIOCLK. • Must be specified as the time to the beginning of output state change in open drain output mode. • See Fig.8. 2.7 to 5.5 (1/3)tCYC +0.05 μs min Specification typ max unit Pulse Input Conditions at Ta = -40°C to +85°C, VSS1 = VSS2 = VSS3 = 0V Parameter High/low level pulse width Symbol tP1H(1) tP1L(1) Pin/Remarks INT0(P70), INT1(P71), INT2(P72), INT4(P20 to P23), INT5(P24 to P27), INT6(P20), INT7(P24) tPIH(2) tPIL(2) tPIH(3) tPIL(3) tPIH(4) tPIL(4) tPIL(5) INT3(P73) when noise filter time constant is 1/1 INT3(P73) when noise filter time constant is 1/32 INT3(P73) when noise filter time constant is 1/128 RES • Interrupt source flag can be set. • Event inputs for timer 0 are enabled. • Interrupt source flag can be set. • Event inputs for timer 0 are nabled. • Interrupt source flag can be set. • Event inputs for timer 0 are enabled. Resetting is enabled. 2.7 to 5.5 200 μs 2.7 to 5.5 256 2.7 to 5.5 64 2.7 to 5.5 2 tCYC Conditions VDD[V] • Interrupt source flag can be set. • Event inputs for timer 0 or 1 are enabled. 2.7 to 5.5 1 min Specification typ max unit No.A1909-22/32 LC87F1M16A AD Converter Characteristics at Ta = -40°C to +85°C, VSS1 = VSS2 = VSS3 = 0V Parameter Resolution Absolute accuracy Conversion time TCAD Symbol N ET Pin/Remarks AN0(P00) to AN7(P07), AN8(PWM1), AN9(PWM0), AN10(XT1), AN11(XT2), Analog input voltage range Analog port input current IAINH IAINL VAIN AN12(P20) to AN19(P27) VAIN=VDD VAIN=VSS 3.0 to 5.5 3.0 to 5.5 -1 1 μA See conversion time calculation formulas. (Note 6-2) (Note 6-1) Conditions VDD[V] 3.0 to 5.5 3.0 to 5.5 4.5 to 5.5 3.0 to 5.5 3.0 to 5.5 32 64 VSS min Specification typ 12 max unit bit ±16 115 115 VDD LSB μs V Parameter Resolution Absolute accuracy Conversion time TCAD Symbol N ET Pin/Remarks AN0(P00) to AN7(P07), AN8(PWM1), AN9(PWM0), AN10(XT1), AN11(XT2), Analog input voltage range Analog port input current IAINH IAINL VAIN AN12(P20) to AN19(P27) VAIN=VDD VAIN=VSS 3.0 to 5.5 3.0 to 5.5 -1 1 μA See conversion time calculation formulas. (Note 6-2) (Note 6-1) Conditions VDD[V] 3.0 to 5.5 3.0 to 5.5 4.5 to 5.5 3.0 to 5.5 3.0 to 5.5 20 40 VSS min Specification typ 8 max unit bit ±1.5 90 90 VDD LSB μs V Conversion time calculation formulas : 12-bits AD Converter Mode : TCAD (Conversion time) = ((52/(AD division ratio))+2) × (1/3) × tCYC 8-bits AD Converter Mode : TCAD (Conversion time) = ((32/(AD division ratio))+2) × (1/3) × tCYC External oscillator FmCF[MHz] 12 3.0 to 5.5 1/1 250 1/16 69.5 42.8 Supply Voltage Range VDD[V] 4.0 to 5.5 System Clock Division (SYSDIV) 1/1 Cycle Time tCYC [ns] 250 AD Frequency Division Ratio (ADDIV) 1/8 12-bit AD 34.8 8-bit AD 21.5 Conversion Time (TCAD)[μs] Note 6-1: The quantization error (±1/2LSB) must be excluded from the absolute accuracy. The absolute accuracy must be measured in the microcontroller's state in which no I/O operations occur at the pins adjacent to the analog input channel. Note 6-2: The conversion time refers to the period from the time an instruction for starting a conversion process till the time the conversion results register(s) are loaded with a complete digital conversion value corresponding to the analog input value. The conversion time is 2 times the normal-time conversion time when: • The first AD conversion is performed in the 12-bit AD conversion mode after a system reset. • The first AD conversion is performed after the AD conversion mode is switched from 8-bit to 12-bit conversion mode. No.A1909-23/32 LC87F1M16A Power-on Reset (POR) Characteristics at Ta = -40°C to +85°C, VSS1 = VSS2 = VSS3 = 0V Specification Parameter POR release voltage Symbol PORRL Conditions Select from option (Note 7-1) Option selected voltage 2.57V 2.87V 3.86V 4.35V Detection voltage unknown state Power supply rise time PORIS POUKS See Fig.11 (Note 7-2) Power supply rise time from 0V to 1.6V min 2.45 2.75 3.73 4.21 typ 2.57 2.87 3.86 4.35 0.7 max 2.69 2.99 3.99 4.49 0.95 100 ms V unit Note 7-1: The POR release level can be selected out of 4 levels only when the LVD reset function is disabled. Note 7-2: POR is in unknown state before transistor start operation. Low Voltage Detection Reset (LVD) Characteristics at Ta = -40°C to +85°C, VSS1 = VSS2 = VSS3 = 0V Specification Parameter LVD reset voltage (Note 8-2) Symbol LVDET Conditions Select from option See Fig.12 (Note 8-1) (Note 8-3) LVD hysteresis width LVHYS Option selected voltage 2.81V 3.79V 4.28V 2.81V 3.79V 4.28V Detection voltage unknown state Low voltage detection minimum width (Reply sensitivity). TLVDW LVUKS See Fig.12 (Note 8-4) LVDET-0.5V See Fig.13 0.2 ms min 2.71 3.69 4.18 typ 2.81 3.79 4.28 55 60 60 0.7 0.95 V mV max 2.91 3.89 4.38 V unit Note 8-1: The LVD reset level can be selected out of 3 levels only when the LVD reset function is enabled. Note 8-2: LVD reset voltage specification values do not include hysteresis voltage. Note 8-3: LVD reset voltage may exceed its specification values when port output state changes and and/or when a large current flows through port. Note 8-4: LVD is in unknown state before transistor start operation. No.A1909-24/32 LC87F1M16A Consumption Current Characteristics at Ta = -40°C to +85°C, VSS1 = VSS2 = VSS3 = 0V Parameter Normal mode consumption current (Note 9-1) (Note 9-2) IDDOP(2) Symbol IDDOP(1) Pin/ Remarks VDD1 =VDD2 =VDD3 Conditions VDD[V] • FmCF=12MHz ceramic oscillation mode • FsX'tal=32.768kHz crystal oscillation mode • System clock set to 12MHz side • Internal PLL oscillation stopped • Internal RC oscillation stopped • USB circuit stopped • 1/1 frequency division ratio IDDOP(3) • FmCF=12MHz ceramic oscillation mode • FsX'tal=32.768kHz crystal oscillation mode • System clock set to 12MHz side IDDOP(4) • Internal PLL oscillation mode active • Internal RC oscillation stopped • USB circuit active • 1/1 frequency division ratio IDDOP(5) IDDOP(6) IDDOP(7) IDDOP(8) IDDOP(9) IDDOP(10) IDDOP(11) IDDOP(12) IDDOP(13) HALT mode consumption current (Note9-1) (Note9-2) IDDHALT(2) IDDHALT(1) • FmCF=12MHz ceramic oscillation mode • FsX'tal=32.768kHz crystal oscillation mode • System clock set to 6MHz side • Internal RC oscillation stopped • 1/2 frequency division ratio • FmCF=0Hz(oscillation stopped) • FsX'tal=32.768kHz crystal oscillation mode • System clock set to internal RC oscillation • 1/2 frequency division ratio • FmCF=0Hz(oscillation stopped) • FsX'tal=32.768kHz crystal oscillation mode • System clock set to crystal oscillation. (32.768kHz) • Internal RC oscillation stopped • 1/2 frequency division ratio • HALT mode • FmCF=12MHz ceramic oscillation mode • FsX'tal=32.768kHz crystal oscillation mode • System clock set to 12MHz side • Internal PLL oscillation stopped • Internal RC oscillation stopped • USB circuit stopped • 1/1 frequency division ratio IDDHALT(3) • HALT mode • FmCF=12MHz ceramic oscillation mode • FsX'tal=32.768kHz crystal oscillation mode • System clock set to 12MHz side IDDHALT(4) • Internal PLL oscillation mode active • Internal RC oscillation stopped • USB circuit active • 1/1 frequency division ratio IDDHALT(5) IDDHALT(6) IDDHALT(7) IDDHALT(8) IDDHALT(9) IDDHALT(10) • HALT mode • FmCF=12MHz ceramic oscillation mode • FsX'tal=32.768kHz crystal oscillation mode • System clock set to 6MHz side • Internal RC oscillation stopped • 1/2 frequency division ratio • HALT mode • FmCF=0Hz(oscillation stopped) • FsX'tal=32.768kHz crystal oscillation mode • System clock set to internal RC oscillation. • 1/2 frequency division ratio 2.7 to 3.0 0.17 0.57 4.5 to 5.5 3.0 to 3.6 2.7 to 3.0 4.5 to 5.5 3.0 to 3.6 2.7 1.3 1.1 0.48 0.22 4.8 2.4 1.8 1.9 0.81 3.0 to 3.6 4.2 7.5 mA 4.5 to 5.5 8.1 15 3.0 to 3.6 2.2 4.0 4.5 to 5.5 4.3 7.6 4.5 to 5.5 3.0 to 3.6 2.7 to 3.0 4.5 to 5.5 3.0 to 3.6 2.7 to 3.0 4.5 to 5.5 3.0 to 3.6 2.7 to 3.0 5.6 3.6 3.0 0.76 0.43 0.36 48 18 14 9.5 6.0 4.8 2.8 1.5 1.2 140 55 40 μA 3.0 to 3.6 7.0 13 mA 4.5 to 5.5 13 23 3.0 to 3.6 5.1 9.2 4.5 to 5.5 8.8 16 min Specification typ max unit Note 9-1: The consumption current value includes none of the currents that flow into the output transistors and internal pull-up resistors. Note9-2: Unless otherwise specified, the consumption current for the LVD circuits is not included. Continued on next page. No.A1909-25/32 LC87F1M16A Continued from preceding page. Parameter HALT mode consumption current (Note 9-1) (Note 9-2) IDDHALT(13) IDDHALT(12) Symbol IDDHALT(11) Pin/ Remarks VDD1 =VDD2 =VDD3 • HALT mode • FmCF=0MHz (oscillation stopped) • FsX'tal=32.768kHz crystal oscillation mode • System clock set to crystal oscillation. (32.768kHz) • Internal RC oscillation stopped • 1/2 frequency division ratio HOLD mode consumption current (Note 9-1) (Note 9-2) IDDHOLD(1) IDDHOLD(2) IDDHOLD(3) IDDHOLD(4) IDDHOLD(5) IDDHOLD(6) IDDHOLD(7) IDDHOLD(8) IDDHOLD(9) Timer HOLD mode consumption current (Note 9-1) (Note 9-2) IDDHOLD(12) IDDHOLD(11) IDDHOLD(10) • HOLD mode • LVD option selected • CF1=VDD or open (External clock mode) • HOLD mode • Watchdog timer operation mode (internal low-speed RC oscillation circuit operation) • CF1=VDD or open (External clock mode) • Timer HOLD mode • CF1=VDD or open (External clock mode) • FsX’tal=32.768kHz crystal oscillation mode 2.7 to 3.0 4.5 to 5.5 3.0 to 3.6 2.7 to 3.0 1.2 31 7.0 4.3 14 110 34 22 3.0 to 3.6 1.4 16 VDD1 • HOLD mode • CF1=VDD or open (External clock mode) 4.5 to 5.5 3.0 to 3.6 2.7 to 3.0 4.5 to 5.5 3.0 to 3.6 2.7 to 3.0 4.5 to 5.5 0.08 0.03 0.02 2.9 2.2 2.1 2.9 24 11 9.6 29 15 12 32 μA 2.7 to 3.0 6.4 27 Conditions VDD[V] 4.5 to 5.5 3.0 to 3.6 min Specification typ 35 9.5 max 120 39 unit Note 9-1: The consumption current value includes none of the currents that flow into the output transistors and internal pull-up resistors. Note9-2: Unless otherwise specified, the consumption current for the LVD circuits is not included. USB Characteristics and Timing at Ta = -40°C to +85°C, VSS1 = VSS2 = VSS3 = 0V Parameter High level output Low level output Output signal crossover voltage Differential input sensitivity Differential input common mode range High level input Low level input USB data rise time Symbol VOH(USB) VOL(USB) VCRS VDI VCM VIH(USB) VIL(USB) tR tF • RS=27 to 33Ω, CL=50pF • VDD3=3.0 to 3.6V USB data fall time • RS=27 to 33Ω, CL=50pF • VDD3=3.0 to 3.6V 4 4 • ⏐(D+)-(D-)⏐ Conditions min • 15kΩ±5% to GND • 1.5kΩ±5% to 3.6V 2.8 0.0 1.3 0.2 0.8 2.0 0.8 20 20 2.5 Specification typ max 3.6 0.3 2.0 unit V V V V V V V ns ns F-ROM Programming Characteristics at Ta = +10°C to +55°C, VSS1 = 0V Parameter Onboard programming current Programming time tFW(1) tFW(2) Symbol IDDFW(1) Pin/ Remarks VDD1 Conditions VDD[V] • Excluding power dissipation in the microcontroller block • Erase operation • Write operation 3.0 to 5.5 min Specification typ 5 20 40 max 10 30 60 unit mA ms μs 3.0 to 5.5 No.A1909-26/32 LC87F1M16A Characteristics of a Sample Main System Clock Oscillation Circuit Given below are the characteristics of a sample main system clock oscillation circuit that are measured using a SANYO-designated oscillation characteristics evaluation board and external components with circuit constant values with which the oscillator vendor confirmed normal and stable oscillation. Table 1 Characteristics of a Sample Main System Clock Oscillator Circuit with a Ceramic Oscillator at Ta = -40°C to +85°C Nominal Frequency Vendor Name Circuit Constant Oscillator Name C1 [pF] 12MHz MURATA CSTCE12M0GH5L**-R0 (33) C2 [pF] (33) Rd1 [Ω] 470 Operating Voltage Range [V] 3.0 to 5.5 Oscillation Stabilization Time typ [ms] 0.1 max [ms] 0.5 C1 and C2 integrated SMD type Remarks The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized in the following cases (see Figure 4): • Till the oscillation gets stabilized after VDD goes above the operating voltage lower limit. • Till the oscillation gets stabilized after the instruction for starting the main clock oscillation circuit is executed. • Till the oscillation gets stabilized after the HOLD mode is reset. • Till the oscillation gets stabilized after the X'tal HOLD mode is reset with CFSTOP (OCR register, bit 0) set to 0. Characteristics of a Sample Subsystem Clock Oscillator Circuit Given below are the characteristics of a sample subsystem clock oscillation circuit that are measured using a SANYOdesignated oscillation characteristics evaluation board and external components with circuit constant values with which the oscillator vendor confirmed normal and stable oscillation. Table 2 Characteristics of a Sample Subsystem Clock Oscillator Circuit with a Crystal Oscillator Nominal Frequency Vendor Name Circuit Constant Oscillator Name C3 [pF] 32.768kHz EPSON TOYOCOM MC-306 18 C4 [pF] 18 Rf [Ω] OPEN Rd2 [Ω] 680k Operating Voltage Range [V] 2.7 to 5.5 Oscillation Stabilization Time typ [s] 1.1 max [s] Applicable 3.0 CL value=12.5pF SMD type Remarks The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized in the following cases (see Figure 4): • Till the oscillation gets stabilized after the instruction for starting the subclock oscillation circuit is executed. • Till the oscillation gets stabilized after the HOLD mode is reset with EXTOSC (OCR register, bit 6) set to 1. Note: The components that are involved in oscillation should be placed as close to the IC and to one another as possible because they are vulnerable to the influences of the circuit pattern. CF1 CF2 XT1 Rf XT2 Rd1 Rd2 C1 CF C2 C3 X’tal C4 Figure 1 CF Oscillator Circuit Figure 2 Crystal Oscillator Circuit No.A1909-27/32 LC87F1M16A 0.5VDD Figure 3 AC Timing Measurement Point VDD Operating VDD lower limit GND Reset time Power supply RES Internal RC oscillation tmsCF CF1, CF2 tmsX’tal XT1, XT2 Operating mode Unpredictable Reset Instruction execution Reset Time and Oscillation Stabilization Time HOLD reset signal HOLD reset signal valid Internal RC oscillation tmsCF CF1,CF2 tmsX’tal XT1, XT2 Operating mode HOLD HALT HOLD Reset Signal and Oscillation Stabilization Time Figure 4 Oscillation Stabilization Time No.A1909-28/32 LC87F1M16A P34/UFILT Rd 0kΩ + Cd - 2.2μF When using the internal PLL circuit to generate the-48MHz clock for USB, it is necessary to connect a filter circuit such as that shown to the left to the P34/UFILT pin. After PLL settings, 20ms or more is required to stabilize. Figure 5 External Filter Circuit for the Internal USB-dedicated PLL Circuit VD3OEN/ VD3OE2 P70/ P27 1.5kΩ D+ 27 to 33Ω 5pF Note: It’s necessary to adjust the Circuit Constant of the USB Port Peripheral Circuit each mounting board. Make the D+ Pull-up resistors available to control on/off according to the Vbus. D27 to 33Ω 5pF Figure 6 USB Port Peripheral Circuit VDD RRES RES CRES Note: The external circuit for reset may vary depending on the usage of POR and LVD. See “Reset Function” in the user’s manual. Figure 7 Sample Reset Circuit No.A1909-29/32 LC87F1M16A SIOCLK: DATAIN: DI0 DI1 DI2 DI3 DI4 DI5 DI6 DI7 DI8 DATAOUT: DO0 DO1 DO2 DO3 DO4 DO5 DO6 DO7 Data RAM transfer period (SIO0, 4 only) DO8 tSCK tSCKL SIOCLK: tsDI DATAIN: tdDO DATAOUT: Data RAM transfer period (SIO0, 4 only) tSCKL SIOCLK: tsDI DATAIN: tdDO DATAOUT: thDI tSCKHA thDI tSCKH Figure 8 Serial Input/Output Waveform tPIL tPIH Figure 9 Pulse Input Timing Signal Waveform Voh Vcrs D+ tr 90% 10% 90% tr 10% Vol D- Figure 10 USB Data Signal Timing and Voltage Level No.A1909-30/32 LC87F1M16A (a) (b) POR release voltage (PORRL) VDD Reset period Reset unknown area (POUKS) RES 100μs or longer Reset period Figure 11 Example of POR Only (LVD Deselected) Mode Waveforms (at Reset Pin with RRES Pull-up Resistor Only) • The POR function generates a reset only when the power voltage goes up from the VSS level. • No stable reset will be generated if power is turned on again when the power level does not go down to the VSS level as shown in (a). If such a case is anticipated, use the LVD function together with the POR function as shown below or implement an external reset circuit. • A reset is generated only when the power level goes down to the VSS level as shown in (b) and power is turned on again after this condition continues for 100μs or longer. LVD hysteresis width (LVHYS) LVD release voltage (LVDET+LVHYS) VDD LVD reset voltage (LVDET) Reset period Reset unknown area (LVUKS) RES Reset period Reset period Figure 12 Example of POR + LVD Mode Waveforms (at Reset Pin with RRES Pull-up Resistor Only) • Reset are generated both when power is turned on and when the power level lowers. • A hysteresis width (LVHYS) is provided to prevent the repetitions of reset release and entry cycles near the detection level. VDD LVD release voltage LVD detect voltage TLVDW VSS LVDET-0.5V Figure 13 Minimum Low Voltage Detection Width (Example of Voltage Sag/Fluctuation Waveform) No.A1909-31/32 LC87F1M16A SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein. SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO Semiconductor Co.,Ltd. products described or contained herein are controlled under any of applicable local export control laws and regulations, such products may require the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written consent of SANYO Semiconductor Co.,Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO Semiconductor Co.,Ltd. product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. Upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third party. SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's intellectual property rights which has resulted from the use of the technical information and products mentioned above. This catalog provides information as of March, 2011. Specifications and information herein are subject to change without notice. PS No.A1909-32/32