LC87F2C64A

Ordering number : ENA1935 LC87F2C64A Overview CMOS IC 64K-byte FROM and 2048-byte RAM integrated 8-bit 1-chip Microcontroller The SANYO LC87F2C64A is an 8-bit microcomputer that, centered around a CPU running at a minimum bus cycle time of 83.3ns, integrates on a single chip a number of hardware features such as 64K-byte flash ROM (onboard programmable), 2048-byte RAM, an on-chip debugger, sophisticated 16-bit timer/counter (may be divided into 8-bit timers), a 16-bit timer/counter (may be divided into 8-bit timers/counters or 8-bit PWMs), four 8-bit timers with a prescaler, a calendar function (RTC), High-speed clock counter, a synchronous SIO interface (with automatic block transmission/reception capabilities), an asynchronous/synchronous SIO interface, two channels of UART interface (full duplex), four 12bit-PWMs, a 12/8-bit 16-channel AD converter, a system clock frequency divider, an internal reset function and a 28-source 10-vector interrupt feature. Features Flash ROM • On-board-programmable with wide range (3.0 to 5.5V) of voltage source • Block-erasable in 128 byte units • Writable in 2-byte units • 65536 × 8 bits RAM • 2048 × 9 bits Minimum Bus Cycle • 83.3ns (12MHz at VDD=3.0V to 5.5V) • 250ns (4MHz at VDD=2.4V to 5.5V) Note: The bus cycle time here refers to the ROM read speed. * This product is licensed from Silicon Storage Technology, Inc. (USA), and manufactured and sold by SANYO Semiconductor Co., Ltd. Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment. The products mentioned herein shall not be intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee thereof. If you should intend to use our products for new introduction or other application different from current conditions on the usage of automotive device, communication device, office equipment, industrial equipment etc. , please consult with us about usage condition (temperature, operation time etc.) prior to the intended use. If there is no consultation or inquiry before the intended use, our customer shall be solely responsible for the use. Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer ' s products or equipment. Ver.0.21 O1911HKIM 20100216-S00003 No.A1935-1/28 LC87F2C64A Minimum Instruction Cycle Time • 250ns (12MHz at VDD=3.0 to 5.5V) • 750ns (4MHz at VDD=2.4 to 5.5V) Temperature Range • -30 to +70 degree Celsius Ports • Normal withstand voltage I/O ports Ports I/O direction can be designated in 1-bit units • Normal withstand voltage input port (Oscillator) • Reset pin • Power pins 71 (P0n, P1n, P2n, P30 to P34, P70 to P73, P8n, PAn, PBn, PCn, Pen, XT2, CF2) 2 (XT1, CF1) 1 (RES) 6 (VSS1 to VSS3, VDD1 to VDD3) Timers • Timer 0: 16-bit timer/counter with a capture register Mode 0: 8-bit timer with an 8-bit programmable prescaler (with an 8-bit capture register) × 2 channels Mode 1: 8-bit timer with an 8-bit programmable prescaler (with an 8-bit capture register) + 8-bit counter (with a 8-bit capture register) Mode 2: 16-bit timer with an 8-bit programmable prescaler (with a 16-bit capture register) Mode 3: 16-bit counter (with a 16-bit capture register) • Timer 1: 16-bit timer/counter that supports PWM/toggle outputs Mode 0: 8-bit timer with an 8-bit prescaler (with toggle outputs) + 8-bit timer/counter with an 8-bit prescaler (with toggle outputs) Mode 1: 8-bit PWM with an 8-bit prescaler × 2 channels Mode 2: 16-bit timer/counter with an 8-bit prescaler (with toggle outputs) (toggle outputs also possible from the lower-order 8 bits) Mode 3: 16-bit timer with an 8-bit prescaler (with toggle outputs) (The lower-order 8 bits can be used as PWM.) • Timer 4: 8-bit timer with a 6-bit prescaler • Timer 5: 8-bit timer with a 6-bit prescaler • Timer 6: 8-bit timer with a 6-bit prescaler (with toggle output) • Timer 7: 8-bit timer with a 6-bit prescaler (with toggle output) • Base timer 1) The clock is selectable from the sub-clock (32.768kHz crystal oscillation/slow RC oscillation), system clock, and prescaler output from timer 0. 2) Interrupts are programmable in 5 different time schemes. • Real time clock (RTC) 1) Used with a base timer, it can be used as a century + year + month + day + hour + minute + second counter. 2) Calendar counts up to December 31, 2799 with automatic leap-year calculation. High-speed Clock Counter • Count clocks with a maximum clock rate of 24MHz (when main clock is 12MHz) • Real-time output No.A1935-2/28 LC87F2C64A SIO • SIO0: 8-bit synchronous serial interface 1) LSB first/MSB first mode selectable 2) Built-in 8-bit baud rate generator (maximum transfer clock cycle = 4/3 tCYC) 3) Automatic continuous data transmission (1 to 256 bits specifiable in 1 bit units, suspension and resumption of data transmission possible in 1 byte units) 4) HOLD/X’tal HOLD mode release function by receiving 1-byte (8-bit clock) • SIO1: 8-bit asynchronous/synchronous serial interface Mode 0: Synchronous 8-bit serial I/O (2- or 3-wire configuration, 2 to 512 tCYC transfer clocks) Mode 1: Asynchronous serial I/O (half-duplex, 8 data bits, 1 stop bit, 8 to 2048 tCYC baud rates) Mode 2: Bus mode 1 (start bit, 8 data bits, 2 to 512 TCYC transfer clocks) Mode 3: Bus mode 2 (start detect, 8 data bits, stop detect) UART: 2 channels • Full duplex • 7/8/9 bit data bits selectable • 1 stop bit (2-bit in continuous data transmission) • Built-in baudrate generator Remote Control Receiver Circuit • Noise rejection function on P73/INT3/T0IN pin (noise rejection filter’s time constant can be selected from 1, 32 or 128 tCYC.) AD Converter: 12 bits × 16 channels • 12 bits/8 bits AD converter resolution selectable PWM: 4 channels • Multi frequency 12-bit PWM Clock Output Function • Output clock with a frequency 1/1, 1/2, 1/4, 1/8, 1/16, 1/32 or 1/64 of the source clock of the system clock. • Output clock of the sub-clock. Buzzer Output • 2kHz or 4kHz buzzer output can be generated using base timer. Watchdog Timer • Watchdog timer can generate interrupt or system reset. • Two types of watchdog timers are available: (1) External RC watchdog timer (2) Base timer watchdog timer • Watchdog timer with base timer can select only one period (1, 2, 4 or 8s) by the user option. Once set the watchdog timer period and start the watchdog timer, the period is not changeable. No.A1935-3/28 LC87F2C64A Interrupts • 28 sources, 10 vector addresses (1) Provides three levels (low (L), high (H), and highest (X)) of multiplex interrupt control. Any interrupt requests of the level equal to or lower than the current interrupt are not accepted. (2) When interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest level takes precedence over the other interrupts. For interrupts of the same level, the interrupt into the smallest vector address takes precedence. No. 1 2 3 4 5 6 7 8 9 10 Vector Address 00003H 0000BH 00013H 0001BH 00023H 0002BH 00033H 0003BH 00043H 0004BH Level X or L X or L H or L H or L H or L H or L H or L H or L H or L H or L INT0 INT1 INT2/INT4/T0L INT3/INT5/Base timer0/ Base timer1/RTC T0H T1L/T1H SIO0/UART1 receive/UART2 receive SIO1/UART1 transmit/UART2 transmit ADC/T6/T7/PWM4, 5/SPI Port0/T4/T5/PWM0, 1 Interrupt Source • Priority levels X > H > L • Of interrupts of the same level, the one with the smallest vector address takes precedence. • IFLG (List of interrupt source flag function) (1) Shows a list of interrupt source flags that caused a branching to a particular vector address (shown in the table above). Subroutine Stack Levels • 1024 levels (Stack is allocated in RAM) High-speed Multiplication/Division Instructions • 16 bits×8 bits (5 tCYC execution time) • 24 bits×16 bits (12 tCYC execution time) • 16 bits÷8 bits (8 tCYC execution time) • 24 bits÷16 bits (12 tCYC execution time) Oscillation Circuits • On-chip fast RC oscillation circuit : For system clock • On-chip slow RC oscillation circuit : For system clock • CF oscillation circuit : For system clock, with built in Rf • Crystal oscillation circuit : For low-speed system clock • On-chip Frequency variable RC oscillation circuit : For system clock (1) Adjustable by ±4% (typical) step from selected center frequency (2) Frequency measurable by referencing input signal from XT1 System Clock Divider Function • Enables low power consumption operation • The minimum instruction cycle selectable from 250ns, 500ns, 1.0μs, 2.0μs, 4.0μs, 8.0μs, 16.0μs, 32.0μs, and 64μs (at a main clock rate of 12MHz). Internal Reset Function • Power-on reset (POR) function (1) POR reset is generated only at power-on. (2) The POR release level can be selected through option configuration. • Low-voltage detection reset (LVD) function (1) LVD and POR functions are combined to generate resets when power is turned on and when power voltage falls below a certain level. (2) The use/no-use of the LVD function and the low voltage threshold level can be selected through option configuration. No.A1935-4/28 LC87F2C64A Standby Function • HALT mode: Halts instruction execution while allowing the peripheral circuits to continue operation. (1) Oscillation is not halted automatically. (2) There are three ways of resetting the HALT mode. 1) Setting the reset pin to the lower level 2) System resetting by watchdog timer 3) Occurrence of an interrupt • HOLD mode: Suspends instruction execution and the operation of the peripheral circuits. (1) The CF, RC, crystal, and frequency variable RC oscillators automatically stop operation. (2) There are five ways of resetting the HOLD mode. 1) Setting the reset pin to the lower level 2) System resetting by watchdog timer 3) Setting at least one of the INT0, INT1, INT2, INT3, INT4, INT5 pins to the specified level 4) Having an interrupt source established at port 0 5) Having an interrupt source established in SPI receiving 1-byte (8-bit clock) • X’'tal HOLD mode: Suspends instruction execution and the operation of the peripheral circuits except the base timer. (1) The CF, RC, and frequency variable RC oscillators automatically stop operation. (2) The state of crystal oscillation established when the X’tal HOLD mode is entered is retained. (3) Power-save mode is available for even lower current consumption. (4) There are seven ways of resetting the X’tal HOLD mode. 1) Setting the reset pin to the low level 2) System resetting by watchdog timer 3) Setting at least one of the INT0, INT1, INT2, INT3, INT4, INT5 pins to the specified level 4) Having an interrupt source established at port0 5) Having an interrupt source established in the base timer circuit 6) Having an interrupt source established in the RTC 7) Having an interrupt source established in SPI receiving 1-byte (8-bit clock) On-chip Debugging Function (flash ROM version) • Supports software debugging with the test device installed on the target board. Data Security Function (flash ROM version) • Protects the program data stored in flash memory from unauthorized read or copy. Note: The data security function does not necessarily provide an absolute data security. Shipping form • QFP80 (14×14): Lead-free type • TQFP80J (12×12): Lead-free type Development Tools • On-chip-debugger: TCB87 TypeB + LC87F2C64A No.A1935-5/28 LC87F2C64A Package Dimensions unit : mm (typ) 3255 17.2 60 61 41 40 80 1 (0.83) 0.65 0.25 20 21 0.15 3.0max 0.1 (2.7) SANYO : QFP80(14X14) Package Dimensions unit : mm (typ) 3290 14.0 12.0 60 61 41 40 14.0 17.2 0.8 12.0 21 14.0 80 1 0.5 (1.25) 0.2 20 14.0 0.125 1.2max 0.1 (1.0) SANYO : TQFP80J(12X12) 0.5 No.A1935-6/28 Pin Assignment P03/URX2 P04 P05/CKO P06/T6O P07/T7O VSS3 VDD3 PA0/PWM0 PA1/PWM0 PA2/PWM0 PA3/PWM0 PA4/PWM1 PA5/PWM1 PA6/PWM1 PA7/PWM1 P30/PWM4 P31/PWM5 P32/DBGP0 P33/DBGP1 P34/DBGP2 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 LC87F2C64A LC87F2C64A P70/INT0/T0LCP P71/INT1/T0HCP P72/INT2/T0IN/NKIN P73/INT3/T0IN RES XT1 XT2 VSS1 CF1 CF2 VDD1 P80/AN0 P81/AN1 P82/AN2 P83/AN3 P84/AN4 P85/AN5 P86/AN6 P87/AN7 PB0/AN8 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VSS2 VDD2 PE2 PE1 PE0 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 PB7/AN15 PB6/AN14 PB5/AN13 PB4/AN12 PB3/AN11 PB2/AN10 PB1/AN9 P02/UTX2 P01/URX1 P00/UTX1 P17/T1PWMH/BUZ P16/T1PWML P15/SCK1 P14/SI1/SB1 P13/SO1 P12/SCK0 P11/SI0/SB0 P10/SO0 P27/INT5/T1IN/T0LCP/T0HCP P26/INT5/T1IN/T0LCP/T0HCP P25/INT5/T1IN/T0LCP/T0HCP P24/INT5/T1IN/T0LCP/T0HCP P23/INT4/T1IN/T0LCP/T0HCP P22/INT4/T1IN/T0LCP/T0HCP P21/INT4/T1IN/T0LCP/T0HCP P20/INT4/T1IN/T0LCP/T0HCP PE3 Top view SANYO: QFP80 (14×14) “Lead-free type” SANYO: TQFP80J (12×12) “Lead-free type” No.A1935-7/28 LC87F2C64A System Block Diagram Interrupt Control IR PLA Stand-by Control Flash ROM CF RC × 2 VMRC X’tal RES Clock Generator PC WDT Reset Circuit (POR/LVD) Reset Control ACC B Register SIO0 Bus Interface C Register SIO1 Port 0 ALU UART1 Port 1 UART2 Timer 0 (High-speed clock counter) Port 2 PSW Port 3 RAR Timer 1 Port 7 Timer 4 Port 8 RAM Timer 5 ADC Stack Pointer Timer 6 INT0 to 5 Noise rejection filter Watchdog Timer Timer 7 Port A On-Chip-Debugger Base Timer Port B RTC Port C PWM0/1 Port E PWM4/5 No.A1935-8/28 LC87F2C64A Pin Description Pin Name VSS1 to VSS3 VDD1 to VDD3 V1 VDC CUP1, CUP2 PORT 0 P00 to P07 I/O I/O - Power supply pin + Power supply pin Open Open Open • 8-bit I/O port • I/O specifiable in 1 bit units • Pull-up resistors can be turned on and off in 1 bit units. • HOLD release input • Port 0 interrupt input Other functions: P00: UART1 transmit P01: UART1 receive P02: UART2 transmit P03: UART2 receive P05: System clock output P06: Timer 6 toggle output P07: Timer 7 toggle output PORT 1 P10 to P17 I/O • 8-bit I/O port • I/O specifiable in 1 bit units • Pull-up resistors can be turned on and off in 1 bit units. Other functions: P10: SIO0 data output P11: SIO0 data input/bus I/O P12: SIO0 clock I/O P13: SIO1 data output P14: SIO1 data input/bus I/O P15: SIO1 clock I/O P16: Timer 1PWML output P17: Timer 1PWMH output/beeper output PORT 2 P20 to P27 I/O • 8-bit I/O port • I/O specifiable in 1 bit units • Pull-up resistors can be turned on and off in 1 bit units. Other functions: P20 to P23: INT4 input/HOLD release input/timer 1 event input /timer 0L capture input/timer 0H capture input P24 to P27: INT5 input/HOLD release input/timer 1 event input /timer 0L capture input/timer 0H capture input • Interrupt acknowledge type Rising INT4 INT5 PORT 3 P30 to P34 I/O • 5-bit I/O port • I/O specifiable in 1 bit units • Pull-up resistors can be turned on and off in 1 bit units. Other functions: P30: PWM4 output P31: PWM5 output P32 (DBGP0) to P34 (DBGP2): On-chip-debugger port (Only on Flash version) Yes Yes Falling Yes Yes Rising & Falling Yes Yes H level No No L level No No Yes Yes Yes Description Option No No No No No Yes Continued on next page. No.A1935-9/28 LC87F2C64A Continued from preceding page. Pin Name PORT 7 P70 to P73 I/O I/O • 4-bit I/O port • I/O specifiable in 1 bit units • Pull-up resistors can be turned on and off in 1 bit units. Other functions: P70: INT0 input/HOLD release input/timer 0L capture input /watchdog timer output P71: INT1 input/HOLD release input/timer 0H capture input P72: INT2 input/HOLD release input/timer 0 event input /timer 0L capture input/high speed clock counter input P73: INT3 input (with noise filter)/ HOLD release input /timer 0 event input/timer 0H capture input • Interrupt acknowledge type Rising INT0 INT1 INT2 INT3 PORT 8 P80 to P87 I/O • 8-bit I/O port • I/O specifiable in 1 bit units Other functions: P80 to P87(AN0 to AN7): AD converter input PORT A PA0 to PA7 I/O • 8-bit I/O port • I/O specifiable in 1 bit units • Pull-up resistors can be turned on and off in 1 bit units. Other functions: PA0 to PA3: PWM0 output PA4 to PA7: PWM1 output PORT B PB0 to PB7 I/O • 8-bit I/O port • I/O specifiable in 1 bit units • Pull-up resistors can be turned on and off in 1 bit units. Other functions: PB0 to PB7 (AN8 to AN15): AD converter input PORT C PC0 to PC7 PORT E PE0 to PE3 RES XT1 I/O I I/O I/O • 8-bit I/O port • I/O specifiable in 1 bit units • Pull-up resistors can be turned on and off in 1 bit units. • 4-bit I/O port • I/O specifiable in 1 bit units • Pull-up resistors can be turned on and off in 1 bit units. External reset input pin/Internal reset output pin • Input for 32.768kHz crystal oscillation Other functions: • General purpose input port *Connect to VDD1 when the port is not used. XT2 I/O • Output for 32.768kHz crystal oscillation Other functions: • General-purpose I/O port *Must be set for oscillation mode and kept open if not to be used. CF1 I • Input for ceramic resonator Other functions: • General purpose input port *Connect to VDD1 when the port is not used. CF2 I/O • Output for ceramic resonator Other functions: • General-purpose I/O port *Must be set for oscillation mode and kept open if not to be used. No No No No No Yes Yes Yes Yes Yes Yes Yes Yes Falling Yes Yes Yes Yes Rising & Falling No No Yes Yes H level Yes Yes No No L level Yes Yes No No No Description Option No No.A1935-10/28 LC87F2C64A Port Output Types The table below lists the types of port outputs and the presence/absence of a pull-up/down resistor. Data can be read into any input port even if it is in the output mode. Port Name P00 to P07 1bit P10 to P17 1bit P20 to P27 1bit P30 to P34 1bit P70 P71 to P73 P80 to P87 PA0 to PA7 1bit PB0 to PC7 1bit PC0 to PC7 1bit PE0 to PE3 1bit XT2 CF2 Option Selected iIn Units of Option Type 1 2 1 2 1 2 1 2 No No No 1 2 1 2 1 2 1 2 No No CMOS Nch-open drain CMOS Nch-open drain CMOS Nch-open drain CMOS Nch-open drain Nch-open drain CMOS Nch-open drain CMOS Nch-open drain CMOS Nch-open drain CMOS Nch-open drain CMOS Nch-open drain 32.768kHz crystal oscillator output or Nch-open drain when selected as normal port Ceramic resonator output or Nch-open drain when selected as normal port No Output Type Pull-Up Resistor Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable No Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable No No.A1935-11/28 LC87F2C64A User Option Table Option Name Port output type Option to be Applied on P00 to P07 Yes P10 to P17 Yes P20 to P27 Yes P30 to P34 Yes PA0 to PA7 Yes PB0 to PB7 Yes PC0 to PC7 Yes PE0 to PE3 Yes Program start address Base timer Watchdog timer Watchdog timer period Yes Yes No*2 Yes Yes 1 bit Yes 1 bit Yes 1 bit Yes 1 bit Yes 1 bit Yes 1 bit Yes 1 bit Yes 1 bit Mask-ROM Version*1 Flash-ROM Version Option Selected in Units of Option Selection CMOS Nch-open drain CMOS Nch-open drain CMOS Nch-open drain CMOS Nch-open drain CMOS Nch-open drain CMOS Nch-open drain CMOS Nch-open drain CMOS Nch-open drain 0000H FE00H 1s 2s 4s 8s Low-Voltage detect function Detection level (Enable) - Yes - Power-on reset level (Disable) - Yes - *1: The option selection cannot to be changed after the mask is created. *2: Program start address for the mask-ROM version is 0000H. No.A1935-12/28 LC87F2C64A *Note1: Connect the IC as shown below to minimize the noise input to the VDD1. Be sure to electrically short the VSS1, VSS2 and VSS3 pins. *Note2: The internal memory is sustained by VDD1. If none of VDD2 and VDD3 are backed up, the high level output at the ports are unstable in the HOLD backup mode, allowing through current to flow into the input buffer and thus shortening the backup time. Make sure that the port outputs are held at the low level in the HOLD backup mode. Example of power connection when power-save mode is used LSI VDD1 Power Supply Back-up capacitors VDD2 VDD3 VSS1 VSS2 VSS3 No.A1935-13/28 LC87F2C64A Absolute Maximum Ratings at Ta=25°C, VSS1=VSS2=VSS3=0V Parameter Maximum supply voltage Input voltage Input/output voltage Peak output current IOPH(2) Mean output current High level output current (Note 1-1) Total output current IOMH(2) ∑IOAH(1) ∑IOAH(2) ∑IOAH(3) ∑IOAH(4) ∑IOAH(5) ∑IOAH(6) ∑IOAH(7) Peak output current IOPL(2) Mean output current (Note 1-1) Low level output current Total output current IOML(2) ∑IOAL(1) ∑IOAL(2) ∑IOAL(3) ∑IOAL(4) ∑IOAL(5) ∑IOAL(6) ∑IOAL(7) ∑IOAL(8) ∑IOAL(9) Power dissipation Pd max(1) IOML(1) IOPL(1) IOMH(1) Symbol VDD max VI VIO IOPH(1) Pin/Remarks VDD1, VDD2, VDD3 XT1, CF1, RES Ports 0, 1, 2, 3, 7, 8, A, B, C, E, XT2, CF2 Ports 0, 1, 2, 3, A, B, C, E P71, P72, P73 Ports 0, 1, 2, 3, A, B, C, E P71, P72, P73 Port 0, P14 to P17 Port 3, A Port 0, 3, A P14 to P17 Port 2 P10 to P13,PE3 Port B, C, PE0 to PE2 Port 2, B, C, E P10 to P13 P71, P72, P73 Ports 0, 1, 2, 3, A, B, C, E Port 7, 8 XT2, CF2 Ports 0, 1, 2, 3, A, B, C, E Port 7, 8 XT2, CF2 Port 0, P14 to P17 Port 3, A Port 0, 3, A P14 to P17 Port 2 P10 to P13, PE3 Port B, C, PE0 to PE2 Port 2, B, C,E P10 to P13 Port 7, XT2 Port 8, CF2 Port 7, 8, XT2, CF2 QFP80 • Total of all applicable pins • Total of all applicable pins • Total of all applicable pins • Ta=-30 to +70°C • Package only • Ta=-30 to +70°C • Package with thermal resistance board (Note 1-2) Pd max(2) TQFP80J • Ta=-30 to +70°C • Package only • Ta=-30 to +70°C • Package with thermal resistance board (Note 1-2) Operating ambient temperature Storage ambient temperature Tstg Topr -30 -55 +70 °C +125 T.B.D T.B.D T.B.D mW • Total of all applicable pins • Total of all applicable pins • Total of all applicable pins • Total of all applicable pins • Total of all applicable pins • Total of all applicable pins • Per 1 applicable pin • Per 1 applicable pin • Per 1 applicable pin • Total of all applicable pins • Per 1 applicable pin • Total of all applicable pins • Total of all applicable pins • Total of all applicable pins • CMOS output select • Per 1 applicable pin • Per 1 applicable pin • CMOS output select • Per 1 applicable pin • Per 1 applicable pin • Total of all applicable pins • Total of all applicable pins • Total of all applicable pins Conditions • VDD1=VDD2=VDD3 Specification VDD[V] min -0.3 -0.3 -0.3 -10 -5 -7.5 -3 -25 -25 -45 -25 -25 -45 -5 20 mA 10 15 7.5 45 45 80 45 45 80 15 15 20 T.B.D typ max +6.5 VDD+0.3 VDD+0.3 V unit Note 1-1: The mean output current is a mean value measured over 100ms. Note 1-2: SEMI standards thermal resistance board (size: 76.1×114.3×1.6tmm, glass epoxy) is used. No.A1935-14/28 LC87F2C64A Allowable Operating Conditions at Ta=-30 to +70°C, VSS1=VSS2=VSS3=0V Specification Parameter Operating supply voltage (Note 2-1) Memory sustaining supply voltage High level input voltage VIH(1) Ports 0, 1, 2, 3, 8, A, B, C, E, P71, P72, P73 P70 port input /interrupt side VIH(2) VIH(3) Low level input voltage VIL(1) Port 70 watchdog timer side XT1, XT2, CF1, CF2, RES Ports 0, 1, 2, 3, 8, A, B, C, E, P71, P72, P73 P70 port input /interrupt side VIL(2) VIL(3) Instruction cycle time (Note 2-1) External system clock frequency tCYC (Note 2-2) FEXCF CF1 • CF2 pin open • System clock frequency division ratio = 1/1 • External system clock duty = 50±5% • CF2 pin open • System clock frequency division ratio = 1/2 • External system clock duty = 50±5% Oscillation frequency range (Note 2-3) FmCF(2) FmVMRC(1) CF1, CF2 FmCF(1) CF1, CF2 • 12MHz ceramic oscillation • See Fig. 1. • 4MHz ceramic oscillation • See Fig. 1. • Frequency variable RC source oscillation • VMRAJ2 to 0 = 4 • VMFAJ2 to 0 = 0 • VMSL4M = 0 FmVMRC(2) • Frequency variable RC source oscillation • VMRAJ2 to 0 = 4 • VMFAJ2 to 0 = 0 • VMSL4M=1 FmRC FsRC FsX’tal XT1, XT2 • Internal fast RC oscillation • Internal slow RC oscillation • 32.768kHz crystal oscillation • See Fig. 2. 2.4 to 5.5 2.4 to 5.5 2.4 to 5.5 500 50 32.768 kHz 2.4 to 5.5 4 3.0 to 5.5 10 MHz 3.0 to 5.5 2.4 to 5.5 12 4 2.4 to 5.5 0.2 8 3.0 to 5.5 0.2 24 2.4 to 5.5 0.1 4 MHz 3.0 to 5.5 0.1 12 Port 70 watchdog timer side XT1, XT2, CF1, CF2, RES • Output disabled 2.4 to 5.5 2.4 to 5.5 3.0 to 5.5 2.4 to 5.5 VSS VSS 0.245 0.735 0.8VDD -1.0 0.25VDD 200 200 μs 2.4 to 5.5 VSS • Output disabled 0.1VDD +0.4 • Output disabled 2.4 to 5.5 2.4 to 5.5 0.9VDD 0.75VDD VDD VDD 2.4 to 5.5 Symbol VDD(1) VDD(2) VHD Pin/Remarks VDD1=VDD2 =VDD3 VDD1 Conditions VDD[V] • 0.245μs≤tCYC≤200μs • 0.735μs≤tCYC≤200μs • RAM and register contents sustained in HOLD mode. • Output disabled 0.3VDD +0.7 VDD min 3.0 2.4 2.2 typ max 5.5 5.5 5.5 unit V Note 2-1: VDD must be held greater than or equal to 3.0V in the flash ROM onboard programming mode. Note 2-2: Relationship between tCYC and oscillation frequency is 3/FmCF at a division ratio of 1/1 and 6/FmCF at a division ratio of 1/2. Note 2-3: See Table 1, 2 for the oscillation constants Continued on next page. No.A1935-15/28 LC87F2C64A Continued from preceding page. Parameter Frequency variable RC oscillation usable range Frequency variable RC oscillation adjustment range VmADJ(2) OpVMRC(2) VmADJ(1) • VMSL4M=1 • 1 step of VMRAJn (large range) • 1 step of VMFAJn (small range) Symbol OpVMRC(1) Pin/Remarks Conditions VDD[V] • VMSL4M=0 3.0 to 5.5 2.4 to 5.5 2.4 to 5.5 2.4 to 5.5 min 8 3.5 8 1 Specification typ 10 4 24 4 max 12 MHz 4.5 64 % 8 unit Electrical Characteristics at Ta=-30 to +70°C, VSS1=VSS2=VSS3=0V Specification Parameter High level input current Symbol IIH(1) Pin/Remarks Ports 0, 1, 2, 3, 7, 8, A, B, C, E Conditions VDD[V] • Output disabled • Pull-up resistor off • VIN=VDD (Including output Tr's off leakage current) IIH(3) IIH(4) IIH(5) Low level input current IIL(1) RES XT1, XT2 CF1, CF2 CF1 Ports 0, 1, 2, 3, 7, 8, A, B, C, E • VIN=VDD • Configured as input ports • VIN=VDD • VIN=VDD • Output disabled • Pull-up resistor off • VIN=VSS (Including output Tr's off leakage current) IIL(2) IIL(3) IIL(4) High level output voltage VOH(1) VOH(2) VOH(3) VOH(4) VOH(5) VOH(6) VOH(7) VOH(8) Low level output voltage VOL(1) VOL(2) VOL(3) VOL(4) VOL(5) Pull-up resistance Rpu Port 7, 8 XT2, CF2 Ports 0, 1, 2, 3, 7, A, B, C, E Hysteresis voltage Pin capacitance VHYS CP Ports 0, 1, 2, 3, 7, A, RES All pins • f=1MHz • Ta=25°C • For pins other than that under test: VIN=VSS 2.4 to 5.5 10 pF Ports 0, 1, 2, 3, A, B, C, E P30, P31, Port A (using as PWM) P71, P72, P73 RES XT1, XT2 CF1, CF2 CF1 Ports 0, 1, 2, 3, A, B, C • VIN=VSS • Configured as input ports • VIN=VSS • VIN=VSS • IOH=-1.0mA • IOH=-0.4mA • IOH=-0.2mA • IOH=-0.4mA • IOH=-0.2mA • IOH=-10mA • IOH=-1.6mA • IOH=-1.0mA • IOL=10mA • IOL=1.6mA • IOL=1.0mA • IOL=1.6mA • IOL=1.0mA • VOH=0.9VDD 2.4 to 5.5 2.4 to 5.5 2.4 to 5.5 4.5 to 5.5 3.0 to 5.5 2.4 to 5.5 3.0 to 5.5 2.4 to 5.5 4.5 to 5.5 3.0 to 5.5 2.4 to 5.5 4.5 to 5.5 3.0 to 5.5 2.4 to 5.5 3.0 to 5.5 2.4 to 5.5 4.5 to 5.5 2.4 to 4.5 2.4 to 5.5 15 25 40 70 0.1VDD -1 -1 -15 VDD-1 VDD-0.4 VDD-0.4 VDD-0.4 VDD-0.4 VDD-1.5 VDD-0.4 VDD-0.4 1.5 0.4 0.4 0.4 0.4 70 150 kΩ V V 2.4 to 5.5 -1 2.4 to 5.5 2.4 to 5.5 2.4 to 5.5 1 1 15 μA 2.4 to 5.5 1 min typ max unit No.A1935-16/28 LC87F2C64A Serial I/O Characteristics at Ta=-30 to +70°C, VSS1=VSS2=VSS3=0V 1. SIO0 Serial I/O Characteristics (Note 4-1-1) Specification Parameter Frequency Low level pulse width Input clock High level pulse width tSCKH(1) tSCKHA(1) • Continuous data transmission/reception mode Serial clock • See Fig. 6. (Note 4-1-2) Frequency Low level Output clock pulse width High level pulse width tSCKH(2) tSCKHA(2) • Continuous data transmission/reception mode • CMOS output selected • See Fig. 6. Data setup time Serial input Data hold time Output delay time Input clock tsDI thDI tdD0(1) SO0(P10), SB0(P11) SB0(P11), SI0(P11) • Must be specified with respect to rising edge of SIOCLK. • See Fig. 6. • Continuous data transmission/reception mode (Note 4-1-3) tdD0(2) • Synchronous 8-bit mode (Note 4-1-3) Output clock tdD0(3) (Note 4-1-3) (1/3)tCYC +0.05 2.4 to 5.5 1tCYC +0.05 (1/3)tCYC +0.05 μs 2.4 to 5.5 0.03 0.03 2.4 to 5.5 tSCK tSCKH(2) +2tCYC tSCKH(2) +(10/3) tCYC tSCK(2) tSCKL(2) SCK0(P12) • CMOS output selected • See Fig. 6. 1/2 1/2 4/3 4 2.4 to 5.5 tCYC Symbol tSCK(1) tSCKL(1) Pin/Remarks SCK0(P12) Conditions VDD[V] • See Fig. 6. min 2 1 1 typ max unit Note 4-1-1: These specifications are theoretical values. Add margin depending on its use. Note 4-1-2: When using serial clock input under continuous data transmission/reception mode, the time from SI0RUN is set while serial clock is “H” to the first falling edge of serial clock must be longer than tSCKHA. Note 4-1-3: Must be specified with respect to falling edge of SIOCLK. Must be specified as the time to the beginning of output state change in open drain output mode. See Fig. 6. Serial output No.A1935-17/28 LC87F2C64A 2. SIO1 Serial I/O Characteristics (Note 4-2-1) Specification Parameter Frequency Input clock Low level pulse width High level pulse width Output clock Frequency Low level pulse width High level pulse width Serial input Data setup time Data hold time tsDI(2) thDI(2) SB1(P14), SI1(P14) • Must be specified with respect to rising edge of SIOCLK. • See Fig. 6. Output delay time tdD0(4) SO1(P13), SB1(P14) • Must be specified with respect to falling edge of Serial output SIOCLK. • Must be specified as the time to the beginning of output state change in open drain output mode. • See Fig. 6. (1/3)tCYC +0.05 μs 2.4 to 5.5 0.03 2.4 to 5.5 0.03 tSCKH(4) tSCK(4) tSCKL(4) SCK1(P15) • CMOS output selected • See Fig. 6. 1/2 tSCK 1/2 2.4 to 5.5 tSCKH(3) Symbol tSCK(3) tSCKL(3) Pin/Remarks SCK1(P15) Conditions VDD[V] • See Fig. 6. 2.4 to 5.5 min 2 1 tCYC 1 2 typ max unit Note 4-2-1: These specifications are theoretical values. Add margin depending on its use. Pulse Input Conditions at Ta=-30 to +70°C, VSS1=VSS2=VSS3=0V Specification Parameter High/low level pulse width Symbol tPIH(1) tPIL(1) Pin/Remarks INT0(P70) INT1(P71) INT2(P72) INT3(P73) INT4(P20 to P23) INT5(P24 to P27) tPIH(2) tPIL(2) tPIH(3) tPIL(3) tPIH(4) tPIL(4) tPIH(5) tPIL(5) tPIL(6) RES INT3(P73) when noise filter time constant is 1/1 INT3(P73) when noise filter time constant is 1/32 INT3(P73) when noise filter time constant is 1/128 NKIN(P72) • Interrupt source flag can be set. • Event inputs for timer 0 are enabled. • Interrupt source flag can be set. • Event inputs for timer 0 are enabled. • Interrupt source flag can be set. • Event inputs for timer 0 are enabled. • High speed clock counter countable • External reset input mode • Resetting is enabled 2.4 to 5.5 2.4 to 5.5 1/12 200 μs 2.4 to 5.5 256 2.4 to 5.5 64 2.4 to 5.5 2 tCYC Conditions VDD[V] • Interrupt source flag can be set. • Event inputs for timer 0 or 1 are enabled. 2.4 to 5.5 1 min typ max unit Serial clock No.A1935-18/28 LC87F2C64A AD Converter Characteristics at VSS1=VSS2=VSS3=0V Parameter Resolution Absolute accuracy Conversion time N ET tCAD Symbol Pin/Remarks AN0(P80) to AN7(P87) AN8(PB0) to AN15(PB7) (Note 6-1) • See Conversion time calculation formulas. (Note 6-2) Analog input voltage range Analog port input current IAINH IAINL • VAIN=VDD • VAIN=VSS VAIN 3.0 to 5.5 3.0 to 5.5 3.0 to 5.5 3.0 to 5.5 -1 64 VSS 115 VDD 1 Conditions VDD[V] 3.0 to 5.5 3.0 to 5.5 4.0 to 5.5 32 min Specification typ 12 ±16 115 μs max unit bit LSB V µA Parameter Resolution Absolute accuracy Conversion time N ET tCAD Symbol Pin/Remarks AN0(P80) to AN7(P87) AN8(PB0) to AN15(PB7) (Note 6-1) • See Conversion time calculation formulas. (Note 6-2) Analog input voltage range Analog port input current IAINH IAINL • VAIN=VDD • VAIN=VSS VAIN 3.0 to 5.5 3.0 to 5.5 3.0 to 5.5 3.0 to 5.5 -1 40 VSS 95 VDD 1 Conditions VDD[V] 3.0 to 5.5 3.0 to 5.5 4.0 to 5.5 20 min Specification typ 8 ±1.5 95 μs max unit bit LSB V μA Conversion time calculation formulas: 12bits AD Converter Mode : TCAD(Conversion time) = ((52/(AD division ratio))+2)×(1/3)×tCYC 8bits AD Converter Mode : TCAD(Conversion time) = ((32/(AD division ratio))+2)×(1/3)×tCYC External oscillation (FmCF) CF-12MHz CF-4MHz Operating supply voltage range (VDD) 4.0V to 5.5V 3.0V to 5.5V 3.0V to 5.5V System division ratio (SYSDIV) 1/1 1/1 1/1 Cycle time (tCYC) 250ns 250ns 750ns AD division ratio (ADDIV) 1/8 1/16 1/8 12bit AD 34.8μs 69.5μs 104.5μs AD conversion time (TCAD) 8bit AD 21.5μs 42.8μs 64.5μs Note 6-1: The quantization error (±1/2LSB) must be excluded from the absolute accuracy. The absolute accuracy must be measured in the microcontroller's state in which no I/O operations occur at the pins adjacent to the analog input channel. Note 6-2: The conversion time refers to the period from the time an instruction for starting a conversion process till the time the conversion results register(s) are loaded with a complete digital conversion value corresponding to the analog input value. The conversion time is 2 times the normal-time conversion time when: • The first AD conversion is performed in the 12-bit AD conversion mode after a system reset. • The first AD conversion is performed after the AD conversion mode is switched from 8-bit to 12-bit conversion mode. No.A1935-19/28 LC87F2C64A Power-on Reset (POR) Characteristics at Ta=-30 to +70°C, VSS1=VSS2=VSS3=0V Parameter POR release voltage Symbol PORRL Pin/Remarks Conditions Option selected voltage • Select from option. (Note 7-1) 1.67V 1.97V 2.07V 2.37V 2.57V 2.87V 3.86V 4.35V Detection voltage unknown state Power supply rise time PORIS POUKS • See Fig. 8. (Note 7-2) • Power supply rise time from 0V to x V. min Specification typ 1.67 1.97 2.07 2.37 2.57 2.87 3.86 4.35 0.7 0.95 100 ms V max unit Note7-1: The POR release level can be selected out of 7 levels only when the LVD reset function is disabled. Note7-2: POR is in an unknown state before transistors start operation. Low Voltage Detection Reset (LVD) Characteristics at Ta=-30 to +70°C, VSS1=VSS2=VSS3=0V Parameter LVD reset Voltage (Note 8-2) Symbol LVDET Pin/Remarks Conditions Option selected voltage • Select from option. (Note 8-1) (Note 8-3) • See Fig. 9. 1.91V 2.01V 2.31V 2.51V 2.81V 3.79V 4.28V LVD hysteresis width LVHYS 1.91V 2.01V 2.31V 2.51V 2.81V 3.79V 4.28V Detection voltage unknown state Low voltage detection minimum width (Reply sensitivity) TLVDW LVUKS • See Fig. 9. (Note 8-4) • LVDET-0.5V • See Fig. 10. 0.2 ms min Specification typ 1.91 2.01 2.31 2.51 2.81 3.79 4.28 55 55 55 55 60 65 65 0.7 0.95 V mV V max unit Note8-1: The LVD reset level can be selected out of 7 levels only when the LVD reset function is enabled. Note8-2: LVD reset voltage specification values do not include hysteresis voltage. Note8-3: LVD reset voltage may exceed its specification values when port output state changes and/or when a large current flows through port. Note8-4: LVD is in an unknown state before transistors start operation. No.A1935-20/28 LC87F2C64A Consumption Current Characteristics at Ta = -30°C to +70°C, VSS1 = VSS2 = VSS3 = 0V Parameter Current consumption during normal operation (Note 9-1) IDDOP(2) Symbol IDDOP(1) Pin/ Remarks VDD1 =VDD2 =VDD3 Conditions VDD[V] • FmCF=12MHz Ceramic resonator oscillation • FsX’tal=32.768kHz crystal oscillation • Frequency variable RC oscillation stopped. • Internal RC oscillation stopped. • System clock: CF oscillation 12MHz • Divider : 1/1 • FmCF=4MHz Ceramic resonator oscillation • FsX’tal=32.768kHz crystal oscillation • Frequency variable RC oscillation stopped. • Internal RC oscillation stopped. • System clock: CF oscillation 4MHz • Divider : 1/1 IDDOP(3) • FmCF=0Hz (No oscillation) • FsX’tal=32.768kHz crystal oscillation • FmVMRC=10MHz Frequency variable RC oscillation • Internal RC oscillation stopped. • System clock: Frequency variable RC oscillation 10MHz • Divider :1/1 IDDOP(4) • FmCF=0Hz (No oscillation) • FsX’tal=32.768kHz crystal oscillation • FmVMRC=4MHz Frequency variable RC oscillation • Internal RC oscillation stopped. • System clock: Frequency variable RC oscillation 4MHz • Divider :1/1 IDDOP(5) • FmCF=0Hz (No oscillation) • FsX’tal=32.768kHz crystal oscillation • Frequency variable RC oscillation stopped. • Internal RC oscillation=Fast RC oscillation • System clock: Fast RC oscillation • Divider :1/1 IDDOP(6) • FmCF=0Hz (No oscillation) • FsX’tal=32.768kHz crystal oscillation • Frequency variable RC oscillation stopped. • Internal RC oscillation stopped. • System clock: 32.768kHz • Divider :1/1 2.4 to 3.6 26.1 110.1 4.5 to 5.5 74 269.4 2.4 to 3.6 300 600 μA 4.5 to 5.5 400 1000 2.4 to 3.6 2.5 5.4 4.5 to 5.5 2.8 8.5 2.4 to 3.6 4.2 101 4.5 to 5.5 6.9 16.6 mA 2.4 to 3.6 2.8 6.3 4.5 to 5.5 3.5 10.0 3.0 to 3.6 4.9 12.1 4.5 to 5.5 8.4 22.1 min Specification typ max unit Note 9-1: Values of the consumption current do not include current that flows into the output transistors and internal pull-up resistors. Continued on next page. No.A1935-21/28 LC87F2C64A Continued from preceding page. Parameter Current consumption during HALT mode (Note 9-1) Symbol IDDHALT(1) Pin/ Remarks VDD1 = VDD2 = VDD3 HALT mode • FmCF=12MHz Ceramic resonator oscillation • FsX’tal=32.768kHz crystal oscillation • Frequency variable RC oscillation stopped. • Internal RC oscillation stopped. • System clock: CF oscillation 12MHz • Divider : 1/1 IDDHALT(2) HALT mode • FmCF=4MHz Ceramic resonator oscillation • FsX’tal=32.768kHz crystal oscillation • Frequency variable RC oscillation stopped. • Internal RC oscillation stopped. • System clock: CF oscillation 4MHz • Divider : 1/1 IDDHALT(3) HALT mode • FmCF=0Hz (No oscillation) • FsX’tal=32.768kHz crystal oscillation • FmVMRC=10MHz Frequency variable RC oscillation • Internal RC oscillation stopped. • System clock: Frequency variable RC oscillation 10MHz • Divider :1/1 IDDHALT(4) HALT mode • FmCF=0Hz (No oscillation) • FsX’tal=32.768kHz crystal oscillation • FmVMRC=4MHz Frequency variable RC oscillation • Internal RC oscillation stopped. • System clock: Frequency variable RC oscillation 4MHz • Divider :1/1 IDDHALT(5) HALT mode • FmCF=0Hz (No oscillation) • FsX’tal=32.768kHz crystal oscillation • Frequency variable RC oscillation stopped. • Internal RC oscillation=Fast RC oscillation • System clock: Fast RC oscillation • Divider :1/1 IDDHALT(6) HALT mode • FmCF=0Hz (No oscillation) • FsX’tal=32.768kHz crystal oscillation • Frequency variable RC oscillation stopped. • Internal RC oscillation stopped. • System clock: 32.768kHz • Divider :1/1 2.4 to 3.6 13.6 83.2 4.5 to 5.5 57.2 230.9 2.4 to 3.6 100 200 μA 4.5 to 5.5 200 500 2.4 to 3.6 0.5 1.3 4.5 to 5.5 1.0 2.5 2.4 to 3.6 1.3 3.2 4.5 to 5.5 2.3 5.8 mA 2.4 to 3.6 0.1 1.8 4.5 to 5.5 0.3 4.1 3.0 to 3.6 1.7 4.3 4.5 to 5.5 3.3 8.4 Conditions VDD[V] min Specification typ max unit Note 9-1: Values of the consumption current do not include current that flows into the output transistors and internal pull-up resistors. Continued on next page. No.A1935-22/28 LC87F2C64A Continued from preceding page Parameter Current consumption during HOLD mode (Note 9-1) Current consumption during Date/time clock HOLD mode (Note 9-1) IDDHOLD(4) IDDHOLD(3) Date/time clock HOLD mode • CF1=VDD or open (when using external clock) • FmX’tal=32.768kHz crystal oscillation • Normal mode Date/time clock HOLD mode • CF1=VDD or open (when using external clock) • FmX’tal=32.768kHz crystal oscillation • Power save mode 4.5 to 5.5 2.4 to 3.6 4.5 to 5.5 2.4 to 3.6 49.9 9.6 1.0 0.76 213 73.4 94.3 39.3 μA Symbol IDDHOLD(1) Pin/ Remarks VDD1 = VDD2 = VDD3 HOLD mode • CF1=VDD or open (when using external clock) 2.4 to 3.6 0.04 22 4.5 to 5.5 0.1 52 Conditions VDD[V] min Specification typ max unit Note9-1: Values of the consumption current do not include current that flows into the output transistors and internal pull-up resistors. F-ROM Programming Characteristics at Ta = +10°C to +55°C, VSS1 = VSS2 = VSS3 = 0V Parameter Onboard programming current Programming time tFW(1) tFW(2) • Erase time • Program time 3.0 to 5.5 20 40 30 60 ms μs Symbol IDDFW Pin/Remarks VDD1 Conditions VDD[V] • Current of the Flash module 3.0 to 5.5 5 10 mA min Specification typ max unit UART (Full Duplex) Operating Conditions at Ta = -30°C to +70°C, VSS1 = VSS2 = VSS3 = 0V Parameter Transfer rate Symbol UBR Pin/Remarks UTX1(P00), URX1(P01) UTX2(P02), URX2(P03) Conditions VDD[V] 2.4 to 5.5 min 16/3 Specification typ max 8192/3 unit tCYC Data length: Stop bits: Parity bits: 7, 8, and 9 bits (LSB first) 1 bit (2-bit in continuous data transmission) None Example of Continuous 8-bit Data Transmission Mode Processing (first transmit data=55H) Start bit Stop bit Transmit data (LSB first) End of transmission Start of transmission UBR Example of Continuous 8-bit Data Reception Mode Processing (first receive data=55H) Start bit Start of reception Receive data (LSB first) Stop bit End of reception UBR No.A1935-23/28 LC87F2C64A Characteristics of a Sample Main System Clock Oscillation Circuit Given below are the characteristics of a sample main system clock oscillation circuit that are measured using a SANYO-designated oscillation characteristics evaluation board and external components with circuit constant values with which the oscillator vendor confirmed normal and stable oscillation. Table1. Characteristics of a Sample Main System Clock Oscillator Circuit with a Ceramic Oscillator Nominal Frequency Circuit Constant Vendor Name Oscillator Name C1 [pF] C2 [pF] Rf [Ω] Rd [Ω] Operating Voltage Range [V] Oscillation Stabilization Time typ [ms] max [ms] Remarks The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized after VDD goes above the operating voltage lower limit (see Figure 4). Characteristics of a Sample Subsystem Clock Oscillator Circuit Given below are the characteristics of a sample subsystem clock oscillation circuit that are measured using a SANYOdesignated oscillation characteristics evaluation board and external components with circuit constant values with which the oscillator vendor confirmed normal and stable oscillation. Table2. Characteristics of a Sample Subsystem Clock Oscillator Circuit with a Crystal Oscillator Nominal Frequency 32.768kHz Vendor Name Oscillator Name C1 [pF] Circuit Constant C2 [pF] Rf [Ω] Rd [Ω] Operating Voltage Range [V] typ [s] Oscillation Stabilization Time max [s] Remarks The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized after the instruction for starting the subclock oscillation circuit is executed and to the time interval that is required for the oscillation to get stabilized after the HOLD mode is reset (see Figure 4). Note: The components that are involved in oscillation should be placed as close to the IC and to one another as possible because they are vulnerable to the influences of the circuit pattern. CF1 CF2 XT1 XT2 Rf1 Rd1 Rf2 Rd2 C1 CF C2 C3 X’tal C4 Figure 1 Ceramic Oscillation Circuit Figure 2 Crystal Oscillation Circuit 0.5VDD Figure 3 AC Timing Measurement Point No.A1935-24/28 LC87F2C64A VDD VDD limit 0V Reset time RES Power supply Internal RC oscillation tmsCF CF1, CF2 tmsXtal XT1, XT2 Operating mode Unfixed Reset Instruction execution Reset Time and Oscillation Stable Time HOLD release signal Without HOLD release signal HOLD release signal VALID Internal RC oscillation tmsCF CF1, CF2 tmsXtal XT1, XT2 Operation mode HOLD HALT HOLD Release Signal and Oscillation Stable Time Figure 4 Oscillation Stabilization Times No.A1935-25/28 LC87F2C64A VDD RRES RES CRES Note: External circuits for reset may vary depending on the usage of POR and LVD. Please refer to the user’s manual for more information. Figure 5 Reset Circuit SIOCLK: DATAIN: DI0 DI1 DI2 DI3 DI4 DI5 DI6 DI7 DI8 DATAOUT: DO0 DO1 DO2 DO3 DO4 DO5 DO6 DO7 Data RAM transmission period (SIO0) DO8 tSCK tSCKL SIOCLK: tsDI DATAIN: tdDO DATAOUT: Data RAM transmission period (SIO0) tSCKL SIOCLK: tsDI DATAIN: tdDO DATAOUT: thDI tSCKHA thDI tSCKH Figure 6 Serial I/O Output Waveforms tPIL tPIH Figure 7 Pulse Input Timing Signal Waveform No.A1935-26/28 LC87F2C64A POR release voltage(PORRL) (a) (b) VDD Reset period Unknown-state (POUKS) RES 100μs or longer Reset period Figure 8 Waveform observed when only POR is used (LVD not used) (RESET pin: Pull-up resistor RRES only) • The POR function generates a reset only when power is turned on starting at the VSS level. • No stable reset will be generated if power is turned on again when the power level does not go down to the VSS level as shown in (a). If such a case is anticipated, use the LVD function together with the POR function or implement an external reset circuit. • A reset is generated only when the power level goes down to the VSS level as shown in (b) and power is turned on again after this condition continues for 100μs or longer. LVD hysteresis width (LVHYS) LVD release voltage (LVDET+LVHYS) VDD Reset period Unknown-state (LVUKS) RES Reset period Reset period LVD reset voltage (LVDET) Figure 9 Waveform observed when both POR and LVD functions are used (RESET pin: Pull-up resistor RRES only) • Resets are generated both when power is turned on and when the power level lowers. • A hysteresis width (LVHYS) is provided to prevent the repetitions of reset release and entry cycles near the detection level. No.A1935-27/28 LC87F2C64A VDD LVD release voltage LVD reset voltage tLVDW VSS LVDET-0.5V Figure 10 Low voltage detection minimum width (Example of momentary power loss/Voltage variation waveform) SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein. SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO Semiconductor Co.,Ltd. products described or contained herein are controlled under any of applicable local export control laws and regulations, such products may require the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written consent of SANYO Semiconductor Co.,Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO Semiconductor Co.,Ltd. product that you intend to use. Upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third party. SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's intellctual property rights which has resulted from the use of the technical information and products mentioned above. This catalog provides information as of February, 2010. Specifications and information herein are subject to change without notice. PS No.A1935-28/28