LC87F40C8A

Ordering number : ENA0139 LC87F40C8A Overview CMOS IC Internal 128K-byte FROM (ROM/CGROM), 2048 byte RAM, 1024-byte CGRAM, and 704×10-bit CRT Display RAM 8-bit 1-chip Microcontroller The SANYO LC87F40C8A is a closed caption TV controlling 8-bit microcomputer that, centered around a CPU running at a minimum bus cycle time of 71ns, integrates on a single chip a number of hardware features such as 128K-byte flash ROM (size-variable program ROM and CGROM), 2048-byte RAM, 1024-byte CGRAM, 704×10-bit CRT display RAM, sophisticated 16-bit timers/counters (may be divided into 8-bit timers), a 16-bit timer/counter (may be divided into 8-bit timers/counters, two 8-bit timers with a prescaler, a base timer serving as a time-of-day clock, a high-speed clock counter, a synchronous SIO interface (with automatic block transmission/reception capabilities), two channels of asynchronous/ synchronous SIO interface (bus mode selectable), a UART interface (full duplex), an 8-bit 8-channel AD converter, one 14-bit PWM channel, three 8-bit PWM channels, a closed caption data slicer, closed caption compatible OSD, a system clock frequency divider, ROM correction function, an on-chip debugger, and onboard programming facilities. Features Flash ROM 128K bytes • 95K- to 110K-byte program ROM (size variable) • 16K- to 31K-byte character generator ROM (size variable) • Runs on a 5V single source and permits onboard programming. • Block erasable in 128 byte units. • Permits 100 programming operations. Internal RAM • General-purpose RAM: • Character generator RAM: • CRT display RAM: • ROM correction RAM: 2K bytes 1K bytes 704 × 10 bits 256 bytes * This product is licensed from Silicon Storage Technology, Inc. (USA), and manufactured and sold by SANYO Semiconductor Co., Ltd. Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment (home appliances, AV equipment, communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee thereof. If you should intend to use our products for applications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our customer shall be solely responsible for the use. Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer' s products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer' s products or equipment. Ver.1.08 D1306HKIM 20060911-S00004 No.A0139-1/26 LC87F40C8A Minimum Bus Cycle Time • 71 ns (14.1MHz) Note: The bus cycle time here refers to the ROM read speed. Minimum Instruction Cycle Time • 212 ns (14.1MHz) OSD • Screen size • Display RAM size Display area Control area • Font types : 36 characters × 16 lines : 704 words (1 word=10 bits) : 36 words × 16 lines : 8 words × 16 lines : 16 × 32 font, 512 types (16 CGRAM fonts, including 4 fixed fonts) An arbitrary number of characters can be generated as 16 × 17 or 8 × 9 font characters. • Display colors : 4096 colors Character text, background, borders, and full background can be displayed. • Display mode specifiable on a line basis. Normal, 4-color pixel map, 16-color pixel map, and caption text modes • Vertical display start line and horizontal display start position specifiable on a line basis. • Shutter function (specifying the display start or stop line) and scroll functions specifiable on a line basis. • Horizontal character spacing (9 to 16 dots)*1 and vertical character spacing (1 to 32 dots) specifiable on a line basis. • Character size selectable from 16 character sizes on a line basis*1. (Horizontal×Vertical) = (1×1), (1×2), (2×1), (2×2), (2×4) (4×2), (4×4), (4×8), (1.5×1), (1.5×2) (3×1), (3×2), (3×4), (6×2), (6×4), (6×8) • Cursor display function (4/16 pixel colors) • Multilayer display • Full screen display area specifiable. • OSD clock selectable (normal speed mode/high speed mode/external input) • Interlace/progressive scan selectable *1: The supported range varies depending on the active display mode. Refer to the user's guide for details. Data Slicer Function (closed caption format) • Extracts closed caption data and XDS data. • NTSC/PAL selectable and line specifiable. Ports • Normal withstand voltage I/O ports Ports whose I/O direction can be designated in 1-bit units 41 (P1n, P2n, P3n, P70 to P73, P8n, PC0 to PC4) Ports whose I/O direction can be designated in 4-bit units 8 (P0n) Timers • Timer 0: 16-bit timer/counter with a capture register. Mode 0: 8-bit timer with an 8-bit programmable prescaler (with an 8-bit capture register) × 2 channels Mode 1: 8-bit timer with an 8-bit programmable prescaler (with an 8-bit capture register) + 8-bit counter (with an 8-bit capture register) Mode 2: 16-bit timer with an 8-bit programmable prescaler (with a 16-bit capture register) Mode 3: 16-bit counter (with a 16-bit capture register) • Timer 1: 16-bit timer/counter that supports PWM/toggle outputs Mode 0: 8-bit timer with an 8-bit prescaler + with an 8-bit prescaler 8-bit timer/counter Mode 1: 6-bit timer/counter with an 8-bit prescaler • Timer 4: 8-bit timer with a 6-bit prescaler • Timer 5: 8-bit timer with a 6-bit prescaler • Base timer 1) The clock is selectable from the subclock (32.768kHz crystal oscillation), system clock, and timer 0 prescaler output. 2) Interrupts programmable in 5 different time schemes No.A0139-2/26 LC87F40C8A High-speed Clock Counter 1) Can count clocks with a maximum clock rate of 28.2MHz (at a main clock of 14.1MHz). 2) Can generate output real-time. SIO • SIO0: 8-bit synchronous serial interface 1) LSB first/MSB first mode selectable 2) Built-in 8-bit baudrate generator (maximum transfer clock cycle = 4/3 tCYC) 3) Automatic continuous data transmission (1 to 256 bits, specifiable in 1 bit units, suspension and resumption of data transmission possible in 1 byte units) • SIO1: 8-bit asynchronous/synchronous serial interface (bus mode 1 system) Mode 0: Synchronous 8-bit serial I/O (2- or 3-wire configuration, 2 to 512 tCYC transfer clocks) Mode 1: Asynchronous serial I/O (half-duplex, 8 data bits, 1 stop bit, 8 to 2048 tCYC baudrates) Mode 2: Bus mode 1 (start bit, 8 data bits, 2 to 512 tCYC transfer clocks) Mode 3: Bus mode 2 (start detect, 8 data bits, stop detect) • SIO6: 8-bit asynchronous/synchronous serial interface (bus mode 2 system) Mode 0: Synchronous 8-bit serial I/O (2- or 3-wire configuration, 2 to 512 tCYC transfer clocks) Mode 1: Asynchronous serial I/O (half-duplex, 8 data bits, 1 stop bit, 8 to 2048 tCYC baudrates) Mode 2: Bus mode 1 (start bit, 8 data bits, 2 to 512 tCYC transfer clocks) Mode 3: Bus mode 2 (start detect, 8 data bits, stop detect) UART • Full duplex • 7/8/9 data bits selectable • 1 stop bit • Built-in baudrate generator AD Converter: 8 bits × 8 channels PWM: 14-bit PWM × 1 channel 8-bit PWM × 3 channels Remote Control Receiver Circuit (sharing with P73, INT3, and T0IN pins) • Noise rejection function (noise filter time constant selectable from 1 tCYC, 32 tCYC, and 128 tCYC) Watchdog Timer • External RC watchdog timer • Interrupt and reset signals selectable High-speed Multiplication/Division Instructions • 16 bits × 8 bits (5 tCYC execution time) • 24 bits × 16 bits (12 tCYC execution time) • 16 bits ÷ 8 bits (8 tCYC execution time) • 24 bits ÷ 16 bits (12 tCYC execution time) No.A0139-3/26 LC87F40C8A Interrupts • 21 sources, 10 vector addresses 1) Provides three levels (low (L), high (H), and highest (X)) of multiplex interrupt control. Any interrupt requests of the level equal to or lower than the current interrupt are not accepted. 2) When interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest level takes precedence over the other interrupts. For interrupts of the same level, the interrupt into the smallest vector address takes precedence. No. 1 2 3 4 5 6 7 8 9 10 Vector Address 00003H 0000BH 00013H 0001BH 00023H 0002BH 00033H 0003BH 00043H 0004BH Level X or L X or L H or L H or L H or L H or L H or L H or L H or L H or L INT0 INT1 INT2/T0L INT3/base timer T0H T1L/T1H SIO0/UART1 receive SIO1/UART1 transmit/data slicer/SIO6 ADC/vertical sync (VS)/scan line Port 0/T4/T5 Interrupt Source • Priority levels X > H > L • Of interrupts of the same level, the one with the smallest vector address takes precedence. Subroutine Stack Levels: 1024 levels maximum (the stack is allocated in RAM.) Oscillation Circuits • RC oscillation circuit (internal) : For system clock • VCO oscillation circuit (internal) : For system clock generation and CRT display • Crystal oscillation circuit : For low-speed system clock, base timer, and PLL reference System Clock Divider Function • Can run on low current. • The minimum instruction cycle selectable from 212ns, 424ns, 848ns, 1.7µs, 3.4µs, 6.8µs, 13.6µs, 27.1µs, and 54.3µs (at a main clock rate of 14.1MHz). Standby Function • HALT mode: Halts instruction execution while allowing the peripheral circuits to continue operation. 1) Oscillation is not halted automatically. 2) Canceled by a system reset or occurrence of an interrupt • HOLD mode: Suspends instruction execution and the operation of the peripheral circuits. 1) The VCO, RC, and crystal oscillators automatically stop operation. 2) There are three ways of resetting the HOLD mode. (1) Setting the reset pin to the lower level. (2) Setting at least one of the INT0, INT1, and INT2 pins to the specified level (3) Having an interrupt source established at port 0 ROM Correction Function • Executes the correction program on detection of a match with the program counter value. • Correction program area size: 256 bytes (4 vector addresses) Onchip Debugger • Supports software debugging with the IC mounted on the target board Package Form • QIP64E(14×14): Lead-free type • DIP64S(600mil): Lead-free type Development Tools • Onchip debugger interface board: TCB87 (Type B) No.A0139-4/26 LC87F40C8A Package Dimensions unit : mm (typ) 3159A 17.2 14.0 48 49 33 32 14.0 64 1 0.8 (1.0) (2.7) 17 16 0.35 0.15 3.0max 0.1 SANYO : QIP64E(14X14) Package Dimensions unit : mm (typ) 3300 57.2 64 17.2 0.8 33 0.95 5.1max (4.25) 0.51min 3.8 1.78 (1.01) 0.5 SANYO : DIP64S(600mil) 0.2 1 32 15.24 13.8 No.A0139-5/26 LC87F40C8A Pin Assignments P26/OSDCKI P11/SI0/SB0 P21/SI1/SB1 P12/SCK0 P22/SCK1 P25/URX P24/UTX P10/SO0 P20/SO1 P27/BL2 VDD2 VSS2 P13 P07 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 P14/PWMA P15/PWMB P16/PWMC P17/PWMD BL1 B G R HSB VSB VSS1 XT1 XT2 VDD1 RESB FILT 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 1 CVIN 2 P70/INT0/TOLCP 3 P71/INT1/T0HCP 4 P72/INT2/T0IN 5 P73/INT3/T0IN 6 P80/AN0 7 P81/AN1 8 P82/AN2 9 10 11 12 13 14 15 16 P31/SI6/SB6 P32/SCK6 P30/SO6 P83/AN3 P84/AN4 P85/AN5 P86/AN6 P87/AN7 32 31 30 29 28 27 26 P05 P04 P03 P02 P01 P00 PC4 PC3 PC2 PC1 PC0 P37 P36 P35 P34/SCK6 P33/SB6 P06 25 24 23 22 21 20 19 18 17 LC87F40C8A P23 Top view SANYO : QIP64E(14×14) “Lead-free Type” No.A0139-6/26 LC87F40C8A HSB VSB VSS1 XT1 XT2 VDD1 RESB FILT CVIN P70/INT0/T0LCP P71/INT1/T0HCP P72/INT2/T0IN P73/INT3/T0IN P80/AN0 P81/AN1 P82/AN2 P83/AN3 P84/AN4 P85/AN5 P86/AN6 P87/AN7 P30/SO6 P31/SI6/SB6 P32/SCK6 P33/SB6 P34/SCK6 P35 P36 P37 PC0 PC1 PC2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 R G B BL1 P17/PWMD P16/PWMC P15/PWMB P14/PWMA P13 P12/SCK0 P11/SI0/SB0 P10/SO0 VDD2 VSS2 P27/BL2 P26/OSDCKI P25/URX P24/UTX P23 P22/SCK1 P21/SI1/SB1 P20/SO1 P07 P06 P05 P04 P03 P02 P01 P00 PC4 PC3 LC87F40C8A 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 Top view SANYO : DIP64S (600mil) “Lead-free Type” No.A0139-7/26 LC87F40C8A System Block Diagram Interrupt control IR PLA Standby control X'tal RC VCO ROM correct Flash ROM PLL PC SIO0 Bus interface Clock generator SIO1 Port 0 ACC SIO6 Port 1 B register Timer 0 Port 2 C register Timer 1 Port 3 ALU Timer 4 Port 7 Timer 5 Port 8 PSW Base timer Port C RAR PWM ADC RAM Data slicer INT0 to INT3 noise filter Stack pointer UART CGROM OSD VRAM Watchdog timer Onchip debugger No.A0139-8/26 LC87F40C8A Pin Description Pin Name VSS1 VSS2 VDD1 VDD2 Port 0 P00 to P07 I/O - power supply pin Description Option No I/O + power supply pin • 8-bit I/O port • I/O specifiable in 4-bit units • Pull-up resistors can be turned on and off in 4-bit units. • HOLD reset input • Port 0 interrupt input No Yes Port 1 P10 to P17 I/O • 8-bit I/O port • I/O specifiable in 1-bit units • Pull-up resistors can be turned on and off in 1-bit units. • Pin functions P10: SIO0 data output P11: SIO0 data input/bus I/O P12: SIO0 clock I/O P14: PWMA output P15: PWMB output P16: PWMC output P17: PWMD output Yes Port 2 P20 to P27 I/O • 8-bit I/O port • I/O specifiable in 1-bit units • Pull-up resistors can be turned on and off in 1-bit units. • Pin functions P20: SIO1 data output P21: SIO1 data input/bus I/O P22: SIO1 clock I/O P24: UART transmit P25: UART receive P26: External OSD clock input P27: Fast blanking 2 control signal output Yes Port 3 P30 to P37 I/O • 8-bit I/O port • I/O specifiable in 1-bit units • Pull-up resistors can be turned on and off in 1-bit units. • Pin functions P30: SIO6 data output P31: SIO6 data input/bus I/O P32: SIO6 clock I/O P33: SIO6 bus I/O P34: SIO6 clock I/O Onchip debugger pins: DBGP0 to DBGP2 (P35 to P37) Yes Continued on next page. No.A0139-9/26 LC87F40C8A Continued from preceding page. Pin Name Port 7 P70 to P73 I/O I/O • 4-bit I/O port • I/O specifiable in 1-bit units • Pull-up resistors can be turned on and off in 1-bit units. • Shared pins P70: INT0 input/HOLD reset input/timer 0L capture input/watchdog timer output P71: INT1 input/HOLD reset input/timer 0H capture input P72: INT2 input/HOLD reset input/timer 0 event input/timer 0L capture input P73: INT3 input (with noise filter input)/timer 0 event input/timer 0H capture input Interrupt acknowledge type Rising INT0 INT1 INT2 INT3 enable enable enable enable Falling enable enable enable enable Rising & Falling disable disable enable enable H Level enable enable disable disable L Level enable enable disable disable Description Option No Port 8 P80 to P87 I/O • 8-bit I/O port • I/O specifiable in 1-bit units • Shared pins AD converter input: AN0 (P80) to AN7 (P87) No Port C PC0 to PC4 RES XT1 XT2 FILT CVIN VS HS R G B BL1 I/O • 5-bit I/O port • I/O specifiable in 1-bit units • Pull-up resistors can be turned on and off in 1-bit units. Yes Input Input I/O Output Input Input Input Output Output Output Output Reset pin • 32.768kHz crystal oscillator input pin • 32.768kHz crystal oscillator output pin • Internal PL filter pin • Video input pin • Vertical sync input pin • Horizontal sync input pin • Red (R) RGB video output pin • Green (G) RGB video output pin • Blue (B) RGB video output pin • Fast blanking 1 control output pin No No No No No No No No No No No No.A0139-10/26 LC87F40C8A Port Output Types The table below lists the types of port outputs and the presence/absence of a pull-up resistor. Data can be read into any input port even if it is in the output mode. Port name P00 to P07 Option Selected in Units of 1 bit Option Type 1 2 P10 to P17 P20 to P27 P30 to P37 P70 P71 to P73 P80 to P87 PC0 to PC4 1 bit No No No 1 2 Nch-open drain CMOS Nch-open drain CMOS Nch-open drain Programmable Programmable No Programmable Programmable 1 bit 1 2 CMOS Nch-open drain CMOS Nch-open drain Output Type Pull-up Resistor Programmable (Note 1) No Programmable Programmable Note 1: Programmable pull-up resistors for port 0 are controlled in 4 bit units (P00 to 03, P04 to 07). *1 Connect the IC as shown below to minimize the noise input to the VDD1 pin. Be sure to electrically short the VSS1 and VSS2 pins. LSI VDD1 Power supply VDD2 VSS1 VSS2 On-board writing system The LC87F40C8A has the On-board writing system. The program is renewable by using SANYO Flash On-board System after the LSI has been installed on the application board. This system has to connect the 6 pins (VDD, VSS, RES, communication pins) with the interface board of SANYO Flash On-board System. It is necessary that the pins to be used for the rewriting system should be able to be separated from the application board properly. • The loader program must be written into the ROM to use On-board writing system. The loader program should be written into the ROM before the LSI has been installed on the board by the general purpose PROM programs. When the option setting selects the this system to use, the loader program automatically links on the user program linking. Please ask to our sales persons before using On-board writing system. No.A0139-11/26 LC87F40C8A Method of how to rewrite it in FLASH programmer/ SANYO FLASH writing tool (SFWS) When reading or writing data to the LC87F40C8A, FLASH programmer of our recommendation or SANYO FLASH writing tool (SFWS) is used. In both cases, exclusive conversion board (W87F40C8D, W87F40C8Q) is needed. (1) FLASH programmer of our recommendation Single word write Manufacture Flash Support Group co. (the former Ando Electric) Name of device AF9708 version Rev02.35 applicable device (code) SANYO LC87F40C8A (3B21C) Data protection setting after write operation Protected Write multiple words Manufacture Flash Support Group co. (the former Ando Electric) Name of device AF9723 + AF9833 Version Rev01.83 applicable device (code) SANYO LC87F40C8A (3B21C) Data protection setting after write operation Protected • The LC87F40C8A does not support a silicon signature feature. Do not use the feature (automatic device type selection) when programming this device. • To avoid erasing the program, confirm the setting of the protection for activating the written program before using. • It can’t be written with device code 29EE010 (2) SANYO FLASH writing tool (SFWS) PC is connected with writer unit (SKK) by USB cable and it uses it. (3) Exclusive writing conversion board • W87F40C8D: DIP64S purpose • W87F40C8Q: QIP64E purpose When using the conversion board, all of the jumper SW must be set to the OFF position. If set to the ON position, read/write operations will not perform correctly. Pin 1 of the conversion board should be located as indicated below. W87F40C8D: when viewing from the edge closest to jumper SW, pin 1 is located on the lower right of both the chip and conversion board. W87F40C8Q: when viewing from the edge closest to jumper SW, pin 1 of the chip is located on the upper right while pin 1 of the conversion board is located on the lower right. 1pin W87F40C8Q 1pin W87F40C8D No.A0139-12/26 LC87F40C8A Absolute Maximum Ratings at Ta = 25°C, VSS1 = VSS2 = 0V Parameter Maximum supply voltage Input voltage Output voltage Input/output voltage Peak output High level output current current (Note 1-1) IOPH(2) IOPH(3) Total output current ΣIOAH(1) ΣIOAH(2) ΣIOAH(3) Peak output Low level output current current (Note 1-1) IOPL(2) IOPL(3) Total output current ΣIOAL(1) ΣIOAL(2) ΣIOAL(3) Pd max IOPL(1) IOPH(1) VI(1) VO(1) VIO(1) XT1, RES, HS, VS, CVIN XT2, BL1, R, G, B FILT Ports 0, 1, 2, 3 Ports 7, 8 Port C Ports 0, 1, 2, 3, C BL Ports 71 to 73 R, G, B Port 7 Ports 0, 2, 3, C Ports 1 R, G, B, BL Ports 0, 1, 2, 3, C BL Ports 7, 8 R, G, B Ports 7, 8 Ports 0, 2, 3, C Ports 1 R, G, B, BL Allowable power dissipation Operating ambient temperature Storage ambient temperature Tstg Topr QIP64E(14×14) DIP64S(600mil) -10 -55 Ta=-10 to +70°C Per 1 applicable pin OSD is digital mode Per 1 applicable pin Total of all applicable pins Total of all applicable pins Total of all applicable pins Per 1 applicable pin CMOS output select Per 1 applicable pin Per 1 applicable pin OSD is digital mode Per 1 applicable pin Total of all applicable pins Total of all applicable pins Total of all applicable pins -10 -5 -10 -25 -25 -25 mA 20 10 20 20 45 45 390 880 +70 °C +125 -0.3 VDD+0.3 Symbol VDD max Pin/Remarks VDD1, VDD2 Conditions VDD[V] VDD1=VDD2 min -0.3 -0.3 -0.3 Specification typ max +6.5 VDD+0.3 VDD+0.3 V unit mW Note 1-1: The average current per applicable pit must not exceed 10mA. No.A0139-13/26 LC87F40C8A Allowable Operating Conditions at Ta = -10°C to +70°C, VSS1 = VSS2 = 0V Parameter Operating supply voltage Memory sustaining supply voltage High level input voltage VIH(1) Ports 0, 1, 2, 3 P71 to P73, 8, C P70 port input/ interrupt side HS, VS VIH(2) Port 70 watchdog timer side VIH(3) Low level input voltage VIL(1) XT1, RES Ports 0, 1, 2, 3 P71 to P73, 8, C P70 port input/ interrupt side HS, VS VIL(2) Port 70 watchdog timer side VIL(3) CVIN input amplitude Instruction cycle time tcyc(1) (Note 2-1) tcyc(2) (Note 2-1) External OSD clock frequency Oscillation frequency range (Note 2-2) FmRC FsX'tal XT1, XT2 Internal RC oscillator 32.768kHz crystal oscillation mode See Fig. 1. 4.5 to 5.5 4.5 to 5.5 FmVCO1 FmVCO2 FEXOS(1) FEXOS(2) P26/OSDCKI Except for OSD and data slicer functions DUTY50±5% of external OSD clock (Note 2-3) Internal VCO1 oscillator Internal VCO2 Oscillator (Note 2-3) CKSEL0=0 CKSEL0=1 4.5 to 5.5 4.5 to 5.5 SCON1=0 SCON1=1 4.5 to 5.5 28.56 14.08 14.28 28.56 0.3 14.15 14.75 29.5 1.0 32.768 30.88 14.22 15.44 30.88 2.0 kHz MHz All functions VCVIN XT1, RES CVIN 4.5 to 5.5 5.0 4.5 to 5.5 4.5 to 5.5 VSS 1Vp-p -3dB 0.211 0.211 14.28 4.5 to 5.5 VSS 0.15VDD +0.4 0.25VDD 1Vp-p 0.212 1Vp-p +3dB 0.213 200 15.44 MHz Vp-p µs µs 4.5 to 5.5 VSS 0.1VDD +0.4 4.5 to 5.5 0.75VDD VDD 4.5 to 5.5 0.9VDD VDD V 4.5 to 5.5 0.3VDD +0.7 VDD VHD VDD1=VDD2 RAM and register contents sustained in HOLD mode 2.0 5.5 Symbol VDD(1) Pin/Remarks VDD1=VDD2 Conditions VDD[V] 0.211µs≤tCYC≤200µs min 4.5 Specification typ max 5.5 unit Note 2-1: Relationship between tCYC and oscillation frequency is 3/FmVCO1 at a division ratio of 1/1 and 6/FmVCO1 at a division ratio of 1/2. Note 2-2: See Table 1 for the oscillation constants Note 2-3: SCAN1 is Hsync frequency switch bit. CKSEL0 is OSD clock frequency switch bit. (Refer to the LC874000 user's manual for details.) No.A0139-14/26 LC87F40C8A Electrical Characteristics at Ta = -10°C to +70°C, VSS1 = VSS2 = 0V Parameter High level input current Symbol IIH(1) Pin/Remarks Ports 0, 1, 2, 3 Ports 7, 8 Port C Conditions VDD[V] Output disabled Pull-up resistor off VIN=VDD (including output Tr's off leakage current) IIH(2) Low level input current IIL(1) RES, HS, VS Ports 0, 1, 2, 3 Ports 7, 8 Port C VIN=VDD Output disabled Pull-up resistor off VIN=VSS (including output Tr's off leakage current) IIL(2) High level output voltage VOH(2) VOH(3) VOH(4) Low level output voltage VOL(2) VOL(3) VOL(4) Pull-up resistance Hysteresis voltage Rpu VHYS VOL(1) VOH(1) RES, HS, VS Ports 0, 1, 2, 3, 8 Port C P71 to P73 R, G, B BL1, P27/BL2 Ports 0, 1, 2, 3, 8 Port C Port 7 R, G, B BL1, P27/BL2 Ports 0, 1, 2, 3, 7 Ports 8, C RES Ports 1, 2, 3, 7 HS, VS Bus terminal short circuit resistance for internal communication Pin capacitance CP All pins For pins other than that under test: VIN=VSS f=1MHz Ta=25°C 4.5 to 5.5 10 pF RBS • P31, P33 • P32, P34 130 300 Ω 4.5 to 5.5 0.35 V IOH=-0.4mA IOH=-5mA IOH=-5mA When BL2 is output IOL=10mA IOL=1.6mA IOL=1mA IOL=5mA IOL=5mA When BL2 is output VOH=0.9VDD VIN=VSS IOH=-1.0mA 4.5 to 5.5 4.5 to 5.5 4.5 to 5.5 4.5 to 5.5 4.5 to 5.5 4.5 to 5.5 4.5 to 5.5 4.5 to 5.5 4.5 to 5.5 4.5 to 5.5 4.5 to 5.5 15 40 -1 VDD-1 VDD-1 VDD-1 VDD-1 1.5 0.4 0.4 0.4 0.4 70 kΩ V 4.5 to 5.5 -1 4.5 to 5.5 1 µA 4.5 to 5.5 1 min Specification typ max unit No.A0139-15/26 LC87F40C8A Serial I/O Characteristics at Ta = -10°C to +70°C, VSS1 = VSS2 = 0V 1. SIO0 Serial I/O Characteristics (Note 4-1-1) Parameter Period Low level pulse width High level pulse width Input clock tSCKHA(1a) • Continuous data transmission/ reception mode • OSD inactive • See Fig. 5. • (Note4-1-2) tSCKHA(1b) Serial clock • Continuous data transmission/ reception mode • OSD active • See Fig. 5. • (Note4-1-2) Period Low level pulse width High level Output clock pulse width tSCKHA(2a) • Continuous data transmission/ reception mode • OSD inactive • See Fig. 5. tSCKHA(2b) • Continuous data transmission/ reception mode • OSD active • See Fig. 5. Data setup time Serial input tsDI(1) SI0(P11), SB0(P11) Data hold time thDI(1) • Must be specified with respect to rising edge of SIOCLK. • See Fig. 5. 4.5 to 5.5 0.03 Output Input clock delay time tdD0(2) tdD0(1) SO0(P10), SB0(P11), • Continuous data transmission/ reception mode • (Note4-1-3) • Synchronous 8-bit mode • (Note4-1-3) 4.5 to 5.5 Output clock tdD0(3) (Note4-1-3) (1/3)tCYC +0.05 0.03 tSCKH(2) +2tCYC 4.5 to 5.5 tSCKH(2) +2tCYC tSCKH(2) tSCK(2) tSCKL(2) SCK0(P12) • CMOS output selected • See Fig. 5. 4/3 1/2 tSCK 1/2 tSCKH(2) +(10/3) tCYC tCYC tSCKH(2) +(16/3) tCYC 6 4.5 to 5.5 4 tSCKH(1) Symbol tSCK(1) tSCKL(1) Pin/ Remarks SCK0(P12) See Fig. 5. Conditions VDD[V] min 2 1 1 Specification typ max unit tCYC (1/3)tCYC +0.05 1tCYC +0.05 µs Note4-1-1: This standard value is a theory value. Be sure to ensure the margin according to busy condition. Note4-1-2: When using the serial clock in continuous data transmission/reception mode, the time to the first falling edge of the serial clock after it sets SIORUN in “H” state is more extended than tSCLKHA. Note4-1-3: It is defined for the falling edge of SIOCLK. In open drain output, it is defined as the time to start the output change. See Fig. 5. Serial output No.A0139-16/26 LC87F40C8A 2. SIO1, 6 Serial I/O Characteristics (Note 4-2-1) Parameter Period Input clock Low level pulse width High level pulse width Period Output clock Low level pulse width High level pulse width Data setup time Serial input tsDI(2) SI1(P21), SB1(P21), SI6(P31), Data hold time thDI(2) SB6(P31, P33), • Must be specified with respect to rising edge of SIOCLK. • See Fig. 5. 4.5 to 5.5 0.03 Output delay time Serial output tdD0(4) SO1(P20), SB1(P21), SO6(P30), SB6(P31, P34) • Must be specified with respect to falling edge of SIOCLK. • Must be specified as the time to the beginning of output state change in open drain output mode. • See Fig. 5. 4.5 to 5.5 1/3tCYC +0.05 µs 0.03 tSCKH(4) tSCK(4) tSCKL(4) SCK1(P22), SCK6(P32, P34) • CMOS output selected • See Fig. 5. 4.5 to 5.5 tSCKH(3) Symbol tSCK(3) tSCKL(3) Pin/Remarks SCK1(P22), SCK6(P32, P34) 4.5 to 5.5 Conditions VDD[V] See Fig. 5. min 2 1 tCYC 1 2 1/2 tSCK 1/2 Specification typ max unit Note4-2-1: This standard value is a theory value. Be sure to ensure the margin according to busy condition. Serial clock No.A0139-17/26 LC87F40C8A Pulse Input Conditions at Ta = -10°C to +70°C, VSS1 = VSS2 = 0V Parameter High/low level pulse width Symbol tPIH(1) tPIL(1) tPIH(2) tPIL(2) tPIH(3) tPIL(3) tPIH(4) tPIL(4) tPIL(5) tPIH(6) tPIL(6) Pin/Remarks INT0(P70), INT1(P71), INT2(P72), INT3(P73) when noise filter time constant is 1/1 INT3(P73) when noise filter time constant is 1/32 INT3(P73) when noise filter time constant is 1/128 RES HS, VS Conditions VDD[V] • Interrupt source flag can be set. • Event inputs for timers 0 and 1 are enabled. • Interrupt source flag can be set. • Event inputs for timer 0 are enabled • Interrupt source flag can be set. • Event inputs for timer 0 are enabled. • Interrupt source flag can be set. • Event inputs for timer 0 are enabled. Resetting is enabled. • Display position controllable (Note) • The active edge of HS and VS must be apart at least 1 tCYC. • See Fig. 7. Falling time External OSD clock input frequency tTHL tOSCKI HS OSDCKI(P26) See Fig. 7. (Note 5-1) See Fig. 8. 4.5 to 5.5 10 ns 4.5 to 5.5 100 ns 4.5 to 5.5 200 µs 4.5 to 5.5 256 4.5 to 5.5 64 4.5 to 5.5 2 tCYC 4.5 to 5.5 1 min Specification typ max unit 4.5 to 5.5 1 Note 5-1: When the falling edge of HS is affected by the noise, the start position of OSD can slip off. Note that the signal lines with rapid state change or with large current should be allocated away from HS line. AD Converter Characteristics at Ta = -10°C to +70°C, VSS1 = VSS2 = 0V Parameter Resolution Absolute accuracy Conversion time TCAD AD conversion time=32× tCYC (when ADCR2=0) (Note 6-2) AD conversion time=64× tCYC (when ADCR2=1) (Note 6-2) Analog input voltage range Analog port input current IAINH IAINL VAIN=VDD VAIN=VSS VAIN 4.5 to 5.5 4.5 to 5.5 N ET Symbol Pin/Remarks AN0(P80) to AN7(P87) (Note 6-1) Conditions VDD[V] 4.5 to 5.5 4.5 to 5.5 13.50 (tCYC= 0.422µs) 13.50 (tCYC= 0.211µs) 4.5 to 5.5 4.5 to 5.5 4.5 to 5.5 -1 VSS min Specification typ 8 ±1.5 97.92 (tCYC= 3.06µs) 97.92 (tCYC= 1.53µs) VDD 1 V µA µs max unit bit LSB Note 6-1: The quantization error (±1/2LSB) is excluded from the absolute accuracy value. Note 6-2: The conversion time refers to the interval from the time the instruction for starting the converter is issued till the time the complete digital value corresponding to the analog input value is loaded in the required register. No.A0139-18/26 LC87F40C8A Analog mode RGB Characteristics at Ta = -10°C to +70°C, VSS1 = VSS2 = 0V Parameter Output resistance Analog output deflection Time seting VARO tST Symbol R, G, B R, G, B R, G, B Pin/Remarks Conditions min VDD=5.0V VDD=5.0V 70%DC level 10pf load Specification typ max 2.5 20 50 unit kΩ % ns 4/16(V) VARO 70%Vp-p Vp-p 30%Vp-p VARO tST 3/16(V) 2/16(V) 1/16(V) No.A0139-19/26 LC87F40C8A Consumption Current Characteristics at Ta = -10°C to +70°C, VSS1 = VSS2 = 0V Parameter Normal mode current drain (Note 7-1) Symbol IDDOP(1) Pin/ Remarks VDD1 =VDD2 Conditions VDD[V] • FmX'tal=32.768kHz crystal oscillation mode • System clock set to main clock VCO • OSD VCO active • Internal RC oscillator inactive • 1/1 frequency division ratio • OSD is analog mode • DSL active IDDOP(2) • FmX'tal=32.768kHz crystal oscillation mode • System clock set to main clock VCO • OSD VCO active • Internal RC oscillator inactive • 1/1 frequency division ratio • OSD is digital mode • DSL active IDDOP(3) • FmX'tal=32.768kHz crystal oscillation mode • System clock set to 32.768kHz • Main clock and OSD VCOs inactive • Internal RC oscillator inactive • 1/2 frequency division ratio HALT mode current drain (Note 7-1) IDDHALT(1) HALT mode • FmX'tal=32.768kHz crystal oscillation mode • System clock set to main clock VCO • OSD VCO active • Internal RC oscillator inactive • 1/1 frequency division ratio IDDHALT(2) HALT mode • FmX'tal=32.768kHz crystal oscillation mode • System clock set to internal RC oscillator • 1/1 frequency division ratio IDDHALT(3) HALT mode • FmX'tal=32.768kHz crystal oscillation mode • System clock set to 32.768kHz • Main and OSD VCOs inactive • Internal RC oscillator inactive • 1/2 frequency division ratio HOLD mode current drain IDDHOLD VDD1 HOLD mode • All oscillators inactive 4.5 to 5.5 0.05 20 µA 4.5 to 5.5 75 200 µA 4.5 to 5.5 600 1600 4.5 to 5.5 7 11 mA 4.5 to 5.5 100 300 µA 4.5 to 5.5 28 47 mA 4.5 to 5.5 36 58 mA min Specification typ Max unit Note 7-1: The current drain value includes none of the currents that flow into the output transistors and internal pull-up resistors. No.A0139-20/26 LC87F40C8A F-ROM Programming Characteristics Ta = +10 to +55°C, VSS1 = VSS2 = 0V Parameter Onboard programming current Programming time tFW(1) • 128-byte programming • Erasing current included • Time for setting up 128-byte data is excluded. 4.5 to 5.5 22.5 ms Symbol IDDFW(1) Pin/ Remarks VDD1 Conditions VDD[V] • 128-byte programming • Erasing current included 4.5 to 5.5 25 mA min Specification typ max unit UART (Full Duplex) Operating Conditions at Ta=-10 to +70°C, VSS1=VSS2=0V Parameter Transfer rate Symbol UBR Pin/ Remarks P24, P25 Conditions VDD[V] 4.5 to 5.5 min 16/3 Specification typ max 8192/3 unit tCYC Data length: Stop bits: Parity bits: 7/8/9 bits (LSB first) 1 bit None Example of Continuous 8-bit Data Reception Mode Processing (First Transmit Data=55H) Start bit Start of transmission Transmit data (LSB first) Stop bit End of transmission UBR Example of Continuous 8-bit Data Reception Mode Processing (First Receive Data=55H) Start bit Start of reception Receive data (LSB first) Stop bit End of reception UBR No.A0139-21/26 LC87F40C8A Recommended Oscillation Circuit and Sample Characteristics The sample oscillation circuit characteristics in the table below is based on the following conditions: • Recommended circuit parameters are verified by an oscillator manufacturer using a Sanyo provided oscillation evaluation board. • Sample characteristics are the result of the evaluation with the recommended circuit parameters connected externally. Table 1. Recommended oscillation circuit and sample characteristics (Ta = -10 to +70°C) Recommended circuit parameters Frequency Manufacturer Oscillator C1 [pF] 32.768kHz Seiko Epson C-002RX 18 C2 [pF] 18 Rf [Ω] OPEN Rd [Ω] 620k Operating supply voltage Range [V] 4.5 to 5.5 Oscillation Stabilizing time typ [s] 1.00 max [s] 1.50 Remarks Notes: The oscillation stabilizing time period is the time until the VCO oscillation for the internal system becomes stable after the following conditions. (See Figure 3.) 1. The VDD becomes higher than the minimum operating voltage after the power is supplied. 2. The HOLD mode is released. The sample oscillation circuit characteristics may differ applications. For further assistance, please contact with oscillator manufacturer with the following notes in your mind. • Since the oscillation frequency precision is affected by wiring capacity of the application board, etc., adjust the oscillation frequency on the production board. • The above oscillation frequency and the operating supply voltage range are based on the operating temperature of -10°C to +70°C. For the use with the temperature outside of the range herein, or in the application requiring high reliability such as car products, please consult with oscillator manufacturer. • When using the oscillator which is not shown in the sample oscillation circuit characteristics, please consult with Sanyo sales personnel. Since the oscillation circuit characteristics are affected by the noise or wiring capacity because the circuit is designed with low gain in order to reduce the power dissipation, refer to the following notices. • The distance between the clock I/O terminal (XT1 terminal XT2 terminal) and external parts should be as short as possible. • The capacitors’ VSS should be allocated close to the microcontroller’s GND terminal and be away from other GND. • The signal lines with rapid state change or with large current should be allocated away from the oscillation circuit. XT1 XT2 Rf Rd C1 X’tal C2 Figure 1 Recommended oscillation circuit 0.5VDD Figure 2 AC Timing Measurement Point No.A0139-22/26 LC87F40C8A VDD Operating VDD lower limit 0V Reset time RES Power supply Interna RC oscillation tmsVCO VCO1 tmsX’tal XT1, XT2 Operating mode Unpredictable Reset Instruction execution Reset Time and Oscillation Stabilization Time HOLD reset signal No HOLD reset signal HOLD reset signal valid Internal RC oscillation tmsVCO VCO1 tmsX’tal XT1, XT2 State HOLD HALT HOLD Reset Signal and Oscillation Stabilization Time Figure 3 Oscillation Stabilization Timing No.A0139-23/26 LC87F40C8A VDD RRES RES CRES Note: Determine the value of CRES and RRES so that the reset signal is present for a period of 200µs after the supply voltage goes beyond the lower limit of the IC’s operating voltage. Figure 4 Reset Circuit SIOCLK : DATAIN : DI0 DI1 DI2 DI3 DI4 DI5 DI6 DI7 DI8 DATAOUT : DO0 DO1 DO2 DO3 DO4 DO5 DO6 DO7 Data RAM transfer period (SIO0 only) DO8 tSCK tSCKL SIOCLK : tsDI DATAIN : tdDO DATAOUT : Data RAM transfer period (SIO0 only) tSCKL SIOCLK : tsDI DATAIN : tdDO DATAOUT : thDI tSCKHA thDI tSCKH Figure 5 Serial I/O Output Waveforms tPIL tPIH Figure 6 Pulse Input Timing Signal Waveform 1 No.A0139-24/26 LC87F40C8A tPIL(6) HS 0.75VDD 0.25VDD tTHL VS tPIL(6) more than ±1 tCYC Figure 7 Pulse Input Timing Signal Waveform 2 HS OSDCKI tOSCKI tOSCKI Note: Last transition of the t0SCKI must be saving constant. Figure 8 Pulse Input Timing Signal Waveform 3 Noise filter 1µF C-Video 200Ω 1000pF Coupling capacitor CVIN Note: The output impedance of the C-Video side as viewed from the input of the noise filter must be 100Ω or less. Figure 9 Recommended CVIN Circuit 100Ω FILT + 2.2µF - 1MΩ 33000pF Note: Place the components to be connected to the FILT pin so that their trace length is minimum. Figure 10 Recommended Filter Circuit No.A0139-25/26 LC87F40C8A SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein. SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO Semiconductor Co.,Ltd. products described or contained herein are controlled under any of applicable local export control laws and regulations, such products may require the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written consent of SANYO Semiconductor Co.,Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO Semiconductor Co.,Ltd. product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. Upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third party. SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's intellctual property rights which has resulted from the use of the technical information and products mentioned above. This catalog provides information as of December, 2006. Specifications and information herein are subject to change without notice. PS No.A0139-26/26