LC87F7932B

Ordering number : ENA1841 LC87F7932B Overview CMOS IC 32K-byte FROM and 2048-byte RAM integrated 8-bit 1-chip Microcontroller The SANYO LC87F7932B is an 8-bit microcomputer that, centered around a CPU running at a minimum bus cycle time of 250ns, integrates on a single chip a number of hardware features such as 32K-byte flash ROM (onboard programmable), 2048-byte RAM, an on-chip debugger, a LCD controller/driver, sophisticated 16-bit timer/counter (may be divided into 8-bit timers), a 16-bit timer/counter (may be divided into 8-bit timers/counters or 8-bit PWMs), four 8-bit timers with a prescaler, a real time clock function (RTC), a synchronous SIO interface (with automatic block transmission/reception capabilities), an asynchronous/synchronous SIO interface, a UART interface (full duplex), a 12bit/8-bit 7-channel AD converter, a high-speed clock counter, a system clock frequency divider, a power on reset function and a 21-source 10-vector interrupt feature. Features Flash ROM • Capable of on-board-programming with wide range, 3.0 to 5.5V, of voltage source. • Block-erasable in 128 byte units • 32768 × 8 bits RAM 2048 × 9 bits Minimum Bus Cycle • 250ns (4MHz) VDD=2.4V to 3.6V Note: The bus cycle time here refers to the ROM read speed. Minimum instruction cycle time • 750ns (4MHz) VDD=2.4 to 3.6V * This product is licensed from Silicon Storage Technology, Inc. (USA), and manufactured and sold by SANYO Semiconductor Co., Ltd. Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment (home appliances, AV equipment, communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee thereof. If you should intend to use our products for applications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our customer shall be solely responsible for the use. Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer' s products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer' s products or equipment. Ver.1.03 O0610HKIM 20100707-S00004 No.A1841-1/29 LC87F7932B Temperature range • -40°C to +85°C Ports • Input/output ports Data direction programmable for each bit individually: Other function Input ports (for debugger): LCD ports (segment output): • LCD ports & General I/O ports Segment output: Common output: Bias terminals for LCD driver Other functions Input/output ports: • Oscillator pins: • Reset pin: • Power supply: 21 (P0n, P1n, P30, P70-P73) 3 (DBGP0(P05)-DBGP2(P07)) 8 (P1n) 32 (S00-S31) 4 (COM0-COM3) 5 (V1-V3, CUP1, CUP2) 36 (LPAn, LPBn, LPCn, LPLn, P1n) 4 (CF1, CF2, XT1, XT2) 1 (RES) 5 (VSS1-2, VDD1-2, V2) LCD Controller (1) Seven display modes are available (2) Duty 1/3duty, 1/4duty (3) Bias 1/2bias, 1/3bias (4) Segment/common output can be switched to general purpose input/output ports. (5) LCD power range 1) 1/3bias V1 : 1.2V to 1.8V V2 : 2.4V to 3.6V V3 : 3.6V to 5.4V Please use the LCD panel for V2 (=VDD)× 1.5[V], when you select 1/3bias. For example, if the power supply voltage is 3.0V, the LCD panel must be 4.5V. 2) 1/2bias V1 : 1.2V to 1.8V V2 : 2.4V to 3.6V V3 : 2.4V to 3.6V (connect V2 and V3) Please use the LCD panel for V2 (=VDD)[V], when you select 1/3bias. For example, if the power supply voltage is 3.0V, the LCD panel must be 3.0V. Timers • Timer 0: 16 bit timer / counter with capture register Mode 0: 2 channel 8-bit timer with programmable 8 bit prescaler and 8 bit capture register Mode 1: 8 bit timer with 8 bit programmable prescaler and 8 bit capture register + 8 bit Counter with 8-bit capture register Mode 2: 16 bit timer with 8 bit programmable prescaler and 16 bit capture register Mode 3: 16 bit counter with 16 bit capture register • Timer 1: PWM / 16 bit timer/ counter with toggle output function Mode 0: 2 channel 8 bit timer/ counter (with toggle output) Mode 1: 2 channel 8 bit PWM Mode 2: 16 bit timer/ counter (with toggle output) Toggle output from lower 8 bits is also possible. Mode 3: 16 bit timer (with toggle output) Lower order 8 bits can be used as PWM. • Timer 4: 8-bit timer with 6-bit prescaler • Timer 5: 8-bit timer with 6-bit prescaler • Timer 6: 8-bit timer with 6-bit prescaler (with toggle output) • Timer 7: 8-bit timer with 6-bit prescaler (with toggle output) • Base Timer (1) The clock signal can be selected from any of the following: Sub-clock (32.768kHz crystal oscillator / Slow RC oscillation), system clock, and prescaler output from timer 0. (2) Interrupts of five different time intervals are possible. No.A1841-2/29 LC87F7932B High-speed Clock Counter (1) Can count clocks with a maximum clock rate of 8MHz (at a main clock of 4MHz). (2) Can generate output real-time. Serial-interface • SIO 0: 8 bit synchronous serial interface (1) Synchronous 8-bit serial I/O (2- or 3-wire system, clock rates of (4/3) to (512/3) tCYC) (2) Continuous data transmission/reception (Variable length data transmission in bit units from 1 to 256 bits, clock rates of (4/3) to (512/3) tCYC) (3) Bi-phase modulation (Manchester, Bi-phase-Space) data transmission (4) LSB first / MSB first is selectable (5) SPI_function: serial interface that can release HOLD/X’tal HOLD mode after receiving 1-byte (8-bit clock). • SIO 1: 8 bit asynchronous / synchronous serial interface Mode 0: Synchronous 8 bit serial IO (2-wire or 3-wire, transmit clock 2–512 tCYC) Mode 1: Asynchronous serial IO (half duplex, 8 data bits, 1 stop bit, baud rate 8–2048 tCYC) Mode 2: Bus mode 1 (start bit, 8 data bits, transmit clock 2–512 tCYC) Mode 3: Bus mode 2 (start detection, 8 data bits, stop detection) UART • Full duplex • 7/8/9 bit data bits selectable • 1 stop bit (2-bit in continuous data transmission) • Built-in baudrate generator • Operating mode: Programmable transfer mode, fixed-rate transfer mode • Transmission data conversion: Normal (NRZ), Manchester encoding AD converter: 12 bits/8 bits × 7 channels • 12 bits/8 bits AD converter resolution selectable Remote Control Receiver Circuit (Connected to P73 / INT3 / T0IN terminal) • Noise rejection function (Noise rejection filter’s time constant can be selected from 1 / 32 / 128 tCYC) Watchdog Timer • Watchdog timer can produce interrupt or system reset. • Watchdog timer has two types. (1) Use an external RC circuit (2) Use the microcontroller’s basetimer • Watchdog timer that used basetimer can select only one period (1 / 2 / 4 / 8 s) by the user option. Buzzer Output • The buzzer output can transmitted from P17 by using basetimer. Real Time Clock (RTC) (1) Used with a basetimer, it can be used as a century + year + month + day + hour + minute + second counter. (2) Calendar counts up to December 31, 2799 with automatic leap-year calculation. (3) Gregorian calendar capable of keeping GMT (Greenwich Mean Time). Internal Reset Function • Power-On-Reset (POR) function − POR resets the system when the power supply voltage is applied. No.A1841-3/29 LC87F7932B Interrupts: 21 sources, 10 vectors (1) Three priority (Low, high and highest) multiple interrupts are supported. During interrupt handling, an equal or lower priority interrupt request is postponed. (2) If interrupt requests to two or more vector addresses occur at once, the higher priority interrupt takes precedence. In the case of equal priority levels, the vector with the lowest address takes precedence. No. 1 2 3 4 5 6 7 8 9 10 Vector Address 00003H 0000BH 00013H 0001BH 00023H 0002BH 00033H 0003BH 00043H 0004BH Level X or L X or L H or L H or L H or L H or L H or L H or L H or L H or L INT0 INT1 INT2/T0L INT3/Base timer/RTC T0H T1L/T1H SIO0/UART1-receive SIO1/UART-send ADC/T6/T7/SPI Port 0/T4/T5 Interrupt Source • Priority levels X > H > L • For equal priority levels, vector with lowest address takes precedence Subroutine Stack Levels: 1024 levels max. Stack is located in RAM. High-speed Multiplication/Division Instructions • 16 bits × 8 bits (5 tCYC execution time) • 24 bits × 16 bits (12 tCYC execution time) • 16 bits ÷ 8 bits (8 tCYC execution time) • 24 bits ÷ 16 bits (12 tCYC execution time) Oscillation Circuits • On-chip fast RC oscillation (Typical: 500kHz) for system clock use. • On-chip slow RC oscillation (Typical: 50kHz) for system clock use. • CF oscillation (4MHz) for system clock use. (Rf built in, Rd external) • Crystal oscillation (32.768kHz) low speed system clock use. (Rf built in) • Frequency variable RC oscillation circuit (internal): For system clock. (1) Adjustable in ±4% (typ.) step from a selected center frequency. (2) Measures oscillation clock using a input signal from XT1 as a reference. System Clock Divider • Low power consumption operation is available. • Minimum instruction cycle time (750ns, 1.5μs, 3.0μs, 6.0μs, 12μs, 24μs, 48μs, 96μs, 192μs can be switched by program. (when using 4MHz main clock) System Clock Output • The system clock output can transmitted from P04. No.A1841-4/29 LC87F7932B Standby Function • HALT mode HALT mode is used to reduce power consumption. During the HALT mode, program execution is stopped but peripheral circuits keep operating (Some parts of serial transfer operation stop.) (1) Oscillation circuits are not stopped automatically. (2) Released by the system reset or interrupts. • HOLD mode HOLD mode is used to reduce power consumption. Program execution and peripheral circuits are stopped. (1) CF, RC and crystal oscillation circuits stop automatically. (2) Released by any of the following conditions. 1) Low level input to the reset pin 2) Watchdog timer interrupt 3) Specified level input to one of INT0, INT1, INT2 4) Port 0 interrupt 5) SPI interrupt by receiving 1-byte (8-bit clock) • X’tal HOLD mode X’tal HOLD mode is used to reduce power consumption. Program execution is stopped. All peripheral circuits except the base timer are stopped. (1) CF and RC oscillation circuits stop automatically. (2) Crystal oscillator operation is kept in its state at HOLD mode inception. (3) Released by any of the following conditions. 1) Low level input to the reset pin 2) Watchdog timer interrupt 3) Specified level input to one of INT0, INT1, INT2 4) Port 0 interrupt 5) Base-timer interrupt 6) RTC interrupt 7) SPI interrupt by receiving 1-byte (8-bit clock) Onchip debugger • Supports software debugging with the IC mounted on the target board. Shipping Form • QIP64E (14×14) (Lead-/Halogen-free type) • TQFP64J (7×7) (Lead-/Halogen-free type) • SQFP64 (10×10) (Lead-/Halogen-free type) Development Tools • On-chip debugger: TCB87 TypeB+LC87F7932B Flash ROM Programming Boards Package QIP64E (14×14) TQFP64J (7×7) SQFP64 (10×10) Programming boards W87F70256Q W87F70256TQ7 W87F79256SQ No.A1841-5/29 LC87F7932B Flash ROM Programmer Maker Single Flash Support Group, Inc. (FSG) Ganged Model AF9709/AF9709B/AF9709C (Including Ando Electric Co., Ltd. models) AF9723/AF9723B(main unit) (Including Ando Electric Co., Ltd. models) AF9833 (Unit) (Including Ando Electric Co., Ltd. models) Single/Ganged SANYO Onboard Single/Ganged SKK/SKK Type B (SANYO FWS) SKK-DBG Type B (SANYO FWS) Supported version Rev 03.04 or later Rev xx.xx or later Rev xx.xx or later Application Version 1.05A or later Chip Data Version 2.25 or later LC87F7932B Device LC87F2832A LC87F2832A LC87F2832A For information about AF-Series: Flash Support Group, Inc. TEL: +81-53-459-1050 E-mail: sales@j-fsg.co.jp No.A1841-6/29 LC87F7932B Package Dimensions unit : mm (typ) 3159A 17.2 14.0 48 49 33 32 Package Dimensions unit : mm (typ) 3289 9.0 0.8 7.0 48 49 33 32 7.0 14.0 17.2 64 17 1 16 0.4 0.16 0.125 64 1 0.8 (1.0) (2.7) 17 16 0.35 0.15 (0.5) 3.0max 1.2max 0.1 0.1 (1.0) SANYO : QIP64E(14X14) SANYO : TQFP64J(7X7) Package Dimensions unit : mm (typ) 3190A 12.0 48 49 33 32 0.5 10.0 64 1 0.5 (1.25) (1.5) 17 16 0.18 0.15 1.7max 0.1 SANYO : SQFP64(10X10) 10.0 12.0 9.0 No.A1841-7/29 0.5 LC87F7932B Pin Assignment S23/LPC7 S22/LPC6 S21/LPC5 S20/LPC4 S19/LPC3 S18/LPC2 S17/LPC1 S16/LPC0 S15/LPB7 S14/LPB6 S13/LPB5 S12/LPB4 S11/LPB3 S10/LPB2 S09/LPB1 S08/LPB0 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 P70/INT0/T0LCP/AN5 P71/INT1/T0HCP/AN6 P72/INT2/T0IN/NKIN P73/INT3/T0IN VDD2 VSS2 P10/SO0/S24 P11/SI0/SB0/S25 P12/SCK0/S26 P13/SO1/S27 P14/SI1/SB1/S28 P15/SCK1/S29 P16/T1PWML/S30 P17/T1PWMH/BUZ/S31 CUP1 CUP2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 RES XT1 XT2 VSS1 CF1 CF2 VDD1 P00/UTX1/AN0 P01/RTX1/AN1 P02/AN2 P03/AN3 P04/CKO/AN4 P05/DBGP0 P06/T6O/DBGP1 P07/T7O/DBGP2 P30 LC87F7932B 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 S07/LPA7 S06/LPA6 S05/LPA5 S04/LPA4 S03/LPA3 S02/LPA2 S01/LPA1 S00/LPA0 COM3/LPL3 COM2/LPL2 COM1/LPL1 COM0/LPL0 V3 V2 V1 VDC Top view SANYO: QIP64E (14×14) “Lead-/Halogen-free type” SANYO: TQFP64J (7×7) “Lead-/Halogen-free type” SANYO: SQFP64 (10×10) “Lead-/Halogen-free type” No.A1841-8/29 LC87F7932B PIN No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 NAME P70/INT0/T0LCP/AN5 P71/INT1/T0HCP/AN6 P72/INT2/T0IN/NKIN P73/INT3/T0IN VDD2 VSS2 P10/SO0/S24 P11/SI0/SB0/S25 P12/SCK0/S26 P13/SO1/S27 P14/SI1/SB1/S28 P15/SCK1/S29 P16/T1PWML/S30 P17/T1PWMH/BUZ/S31 CUP1 CUP2 VDC V1 V2 V3 COM0/LPL0 COM1/LPL1 COM2/LPL2 COM3/LPL3 S00/LPA0 S01/LPA1 S02/LPA2 S03/LPA3 S04/LPA4 S05/LPA5 S06/LPA6 S07/LPA7 PIN NO. 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 NAME S08/LPB0 S09/LPB1 S10/LPB2 S11/LPB3 S12/LPB4 S13/LPB5 S14/LPB6 S15/LPB7 S16/LPC0 S17/LPC1 S18/LPC2 S19/LPC3 S20/LPC4 S21/LPC5 S22/LPC6 S23/LPC7 RES XT1 XT2 VSS1 CF1 CF2 VDD1 P00/UTX1/AN0 P01/RTX1/AN1 P02/AN2 P03/AN3 P04/CKO/AN4 P05/DBGP0 P06/T6O/DBGP1 P07/T7O/DBGP2 P30 No.A1841-9/29 LC87F7932B System Block Diagram Interrupt Control IR PLA Stand-by Control ROM CF Clock Generator Fast RC Slow RC VMRC X’tal PC RES Reset control ACC WDT Reset circuit (POR) B Register C Register Bus Interface ALU SIO0 Port 0 SIO1 Port 1 PSW Timer 0 Port 3 RAR Timer 1 Port 7 RAM Base Timer UART1 Stack Pointer LCD Controller ADC Watch Dog Timer INT0 - 3 Noise Rejection Filter RTC On Chip Debugger Timer 4 Timer 6 Timer 5 Timer 7 No.A1841-10/29 LC87F7932B Pin Assignment Pin name VSS1, VSS2 VDD1, VDD2, V2 VDC CUP1, CUP2 PORT0 P00 to P07 I/O I/O • Power supply (-) • Power supply (+) • Internal voltage • Capacitor connecting terminals for step-up/step-down • 8bit input/output port • Data direction programmable for each bit • Use of pull-up resistor can be specified for each bit individually • Input for HOLD release • Input for port 0 interrupt • Other pin functions P00: UART1-send P01: UART1-receive P04: System clock output (CKO) P05: DBGP0 (LC87F7932B) P06: T6O/DBGP1 (LC87F7932B) P07: T7O/DBGP2 (LC87F77932B) AD converter input ports: AN0 (P00) – AN4 (P04) PORT1 P10/S24 to P17/S31 I/O • 8bit input/output port • Data direction programmable for each bit • Use of pull-up resistor can be specified for each bit individually • Other pin functions P10: SIO0 data output P11: SIO0 data input or bus input/output P12: SIO0 clock input/output P13: SIO1 data output P14: SIO1 data input or bus input/output P15: SIO1 clock input/output P16: Timer 1 PWML output P17: Timer 1 PWMH output/Buzzer output Segment output for LCD: S24 (P10) – S31 (S17) PORT3 P30 PORT7 P70 to P73 I/O I/O • 1bit Input/output port • Data direction programmable • Use of pull-up resistor can be specified • 4bit Input/output port • Data direction can be specified for each bit • Use of pull-up resistor can be specified for each bit individually • Other functions P70: INT0 input/HOLD release input/Timer0L capture input/output for watchdog timer P71: INT1 input/HOLD release input/Timer0H capture input P72: INT2 input/HOLD release input/timer 0 event input/Timer0L capture input/NKIN P73: INT3 input (noise rejection filter attached)/timer 0 event input/Timer0H capture input AD converter input ports: AN5 (P70), AN6 (P71) • Interrupt detection selection Rising INT0 INT1 INT2 INT3 enable enable enable enable Falling enable enable enable enable Rising and falling disable disable enable enable H level enable enable disable disable L level enable enable disable disable No Yes Yes Function Option No No No No Yes Continued on next page. No.A1841-11/29 LC87F7932B Continued from preceding page. Pin name S00/LPA0 to S07/LPA7 S08/LPB0 to S15/LPB7 S16/LPC0 to S23/LPC7 COM0/LPL0 to COM3/LPL3 V1 to V3 RES XT1 I/O I I/O I/O I/O I/O I/O I/O • Segment output for LCD • Can be used as general purpose input/output port (LPA) • Segment output for LCD • Can be used as general purpose input/output port (LPB) • Segment output for LCD • Can be used as general purpose input/output port (LPC) • Common output for LCD • Can be used as general purpose input/output port (LPL) • LCD output bias power supply • Reset terminal • Input for 32.768kHz crystal oscillation • When not in use, connect to VDD1 XT2 CF1 CF2 I/O I O • Output for 32.768kHz crystal oscillation • When not in use, set to oscillation mode and leave open • Input terminal for ceramic oscillator • When not in use, connect to VDD1 • Output terminal for ceramic oscillator • When not in use, leave open No No No No No No No No No Function description Option No Port Configuration Port form and pull-up resistor options are shown in the following table. Port status can be read even when port is set to output mode. Terminal P00 to P07 Option applies to: each bit Options 1 2 P10 to P17 each bit 1 2 P30 1 2 P70 P71 to P73 S00(LPA0) to S23(LPC7) None None None CMOS Nch-open drain CMOS Nch-open drain CMOS Nch-open drain Nch-open drain CMOS CMOS P-ch Open Drain N-ch Open Drain COM0(LPL0) to COM3(LPL3) None CMOS P-ch Open Drain N-ch Open Drain XT1 XT2 None None Input only 32.768kHz crystal oscillator output Nch-open drain when selected as normal port None None None Output Form Pull-up resistor Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable None No.A1841-12/29 LC87F7932B User Option Table Option name Port output type Option to be applied on P00 to P07 1 bit P10 to P17 1 bit P30 1 bit Basetimer watchdog timer Watchdog period timer Mask version *1 Flash-ROM version CMOS Nch-open drain CMOS Nch-open drain CMOS Nch-open drain 1s 2s 4s 8s Program start address *2 00000h 07E00h Option Selected in units of Option selction *1: Mask option selection-No change possible after mask is completed. *2: Program start address of the mask version is 00000h. *Note 1: Connect as follows to reduce noise on VDD. VSS1 and VSS2 must be connected together and grounded. *Note 2: The power supply for the internal memory is V2. VDD1, VDD2 and V2 are used as the power supply for ports. When VDD1 and VDD2 are not backed up, the port level does not become “H” even if the port latch is in the “H” level. Therefore, when VDD1 and VDD2 are not backed up and the port latch is “H” level, the port level is unstable in the HOLD mode, and the back up time becomes shorter because the through current runs from VDD to GND in the input buffer. If VDD1 and VDD2 are not backed up, output “L” by the program or pull the port to “L” by the external circuit in the HOLD mode so that the port level becomes “L” level and unnecessary current consumption is prevented. Back up capacitors LSI VDD1 Power supply VDD2 V1 V2 V3 VDC CUP1 CUP2 VSS1 VSS2 No.A1841-13/29 LC87F7932B Circuit Example (1)1/3bias, 1/4duty L CD pan el 2 4SEG×4C OM S00 COM0 COM3 S23 I/O P00 P01 P02 P03 P04 P05 P06 P07 P10 P11 P12 P13 P14 P15 P16 P17 P70 P71 P72 P73 P30 CUP1 CUP2 VDC V1 V2 V3 C1 LC87F7932B C2 C3 C4 C5 I/O 2.4V to 3.6V VDD1 VDD2 RRES + CDEN RES CRES VSS1 VSS2 I/O I/O XT2 CF2 CF1 XT1 CF CDC CGC *2 X'tal CDX CGX *1 *1: Crystal oscillator *2: Ceramic oscillator X'tal CGX CDX CF CGC CDC C1 to C5 CDEN CRES RRES Crystal oscillation Trimmer capacitor Capacitor for crystal oscillation Ceramic oscillation Capacitor for ceramic oscillation Capacitor for ceramic oscillation Capacitor Electrolytic capacitor Capacitor for RES Resistor for RES Refer to Page 26 (Characteristic of clock oscillator circuit) Refer to Page 26 (Characteristic of clock oscillator circuit) 0.1μF Back up Refer to User’s manual “RESET Function” No.A1841-14/29 LC87F7932B (2)1/2bias, 1/3duty L CD pan el 2 4SEG×3C OM S00 COM0 COM2 S23 I/O P00 P01 P02 P03 P04 P05 P06 P07 P10 P11 P12 P13 P14 P15 P16 P17 P70 P71 P72 P73 P30 CUP1 CUP2 VDC V1 V2 V3 C1 LC87F7932B C2 C3 C4 I/O 2.4V to 3.6V VDD1 VDD2 RRES + CDEN RES CRES VSS1 VSS2 I/O I/O XT2 CF2 CF1 XT1 CF CDC CGC *2 X'tal CDX CGX *1 *1: Crystal oscillator *2: Ceramic oscillator X'tal CGX CDX CF CGC CDC C1 to C4 CDEN CRES RRES Crystal oscillation Trimmer capacitor Capacitor for crystal oscillation Ceramic oscillation Capacitor for ceramic oscillation Capacitor for ceramic oscillation Capacitor Electrolytic capacitor Capacitor for RES Resistor for RES Refer to Page 26 (Characteristic of clock oscillator circuit) Refer to Page 26 (Characteristic of clock oscillator circuit) 0.1μF Back up Refer to User’s manual “RESET Function” No.A1841-15/29 LC87F7932B Absolute Maximum Ratings at Ta=25°C and VSS1=VSS2=0V Parameter Supply voltage Supply voltage For LCD Symbol VDD max VLCD Pins VDD1, VDD2, V2 V1 V2 V3 Input voltage Input/Output voltage Peak output current High level output current IOPH(2) IOPH(3) IOPH(4) Total output current ∑IOAH(1) ∑IOAH(2) ∑IOAH(3) ∑IOAH(4) ∑IOAH(5) Peak output Low level output current current IOPL(1) IOPL(2) IOPL(3) IOPL(4) Total output current Port 3 LPA, LPB, LPC LPL Port71 to P73 Port 0 Port 3, 7 Port 1 Port 1, 3, 7 LPA, LPB, LPC, LPL Port 0, 1 Port 3 Port 7 LPA, LPB, LPC, LPL Port 0 Port 3, 7 Port 1 Port 1, 3, 7 LPA, LPB, LPC, LPL Maximum power consumption SQFP64 (10×10) Operating temperature range Storage temperature range Tstg -55 125 Topr -40 85 °C Pd max QIP64E (14×14) TQFP64J (7×7) Ta = -40 to +85°C Current at each pin Current at each pin Current at each pin Current at each pin Total of all pins Total of all pins Total of all pins Total of all pins Total of all pins IOPH(1) VI VIO(1) XT1, CF1, RES • Port0, 1, 3, 7 • LPA, LPB, LPC • LPL, XT2 Port 0, 1 • CMOS output selected • Current at each pin • CMOS output selected • CMOS output selected • Current at each pin • Current at each pin Total of all pins Total of all pins Total of all pins Total of all pins Total of all pins -10 -20 -4 -5 -20 -30 -20 -45 -30 20 30 10 6 40 50 40 65 60 267 152 192 mW -0.3 VDD+0.3 Conditions VDD[V] VDD1=VDD2 min -0.3 -0.3 -0.3 -0.3 -0.3 Specification typ max +4.3 1/2VDD VDD 2/3VDD VDD+0.3 V unit mA ΣIOAL(1) ΣIOAL(2) ΣIOAL(3) ΣIOAL(4) ΣIOAL(5) Note 1-1: The mean output current is a mean value measured over 100ms. No.A1841-16/29 LC87F7932B Allowable Operating Conditions at Ta=-40 to +85°C, VSS1=VSS2=0V Parameter Operating supply voltage (Note 2-1) Memory sustaining supply voltage High level input voltage VIH(2) VIH(1) Port 0, 3 LPA, LPB, LPC, LPL Port 1 Port 71 to 73 P70 port input / interrupt side VIH(3) VIH(4) VIH(5) Low level input voltage VIL(2) VIL(1) P71 interrupt side P70 watchdog timer Side XT1, XT2, CF1, RES Port 0, 3 LPA, LPB, LPC, LPL Port 1 Port 71 to 73 P70 port input / interrupt side VIL(3) VIL(4) VIL(5) Instruction cycle time (Note 2-2) External system clock frequency FEXCF(1) CF1 • CF2 pin open • System clock frequency division ratio = 1/1 • External system clock duty = 50±5% • CF2 pin open • System clock frequency division ratio = 1/2 Oscillation frequency range (Note 2-3) FmRC(1) FsRC(1) FsX’tal XT1, XT2 FmCF(1) CF1, CF2 • 4MHz ceramic oscillation • See Fig. 1. Internal Fast RC oscillation Internal Slow RC oscillation • 32.768kHz crystal oscillation • See Fig. 2. Frequency variable RC oscillation usable range Frequency variable RC oscillation adjustment range VmADJ(2) Each step of VMFAJn (Small range) 2.4 to 3.6 1 4 8 VmADJ(1) Each step of VMRAJn (Wide range) 2.4 to 3.6 8 24 64 % OpVMRC(2) When VMSL4M=1 OpVMRC(1) When VMSL4M=0 3.0 to 3.6 2.4 to 3.6 8 3.5 10 4 12 MHz 4.5 2.4 to 3.6 32.768 2.4 to 3.6 2.4 to 3.6 2.4 to 3.6 250 25 4 500 50 750 75 kHz MHz 2.4 to 3.6 0.2 8 2.4 to 3.6 0.1 4 MHz tCYC 2.4 to 3.6 200 μs P71 interrupt side P70 watchdog timer side XT1, XT2, CF1, RES • Output disabled • When INT1VTSL=1 2.4 to 3.6 2.4 to 3.6 2.4 to 3.6 VSS VSS VSS 0.45VDD 0.8VDD -1.0 0.25VDD • Output disabled • When INT1VTSL=0 (P71 only) 2.4 to 3.6 VSS 0.2VDD Output disabled • Output disabled • When INT1VTSL=1 Output disabled 2.4 to 3.6 2.4 to 3.6 2.4 to 3.6 2.4 to 3.6 0.85VDD 0.9VDD 0.75VDD VSS VDD V VDD VDD 0.2VDD • Output disabled • When INT1VTSL=0 (P71 only) 2.4 to 3.6 0.3VDD +0.7 VDD Output disabled 2.4 to 3.6 0.3VDD +0.7 VDD VHD VDD1=VDD2=V2 RAM and register contents sustained in HOLD mode. 2.2 3.6 Symbol VDD(1) Pin/Remarks VDD1=VDD2=V2 Conditions VDD[V] 0.75μs≤tCYC≤200μs Normal mode 2.4 3.6 min Specification typ max unit Note 2-1: VDD must be held greater than or equal to 3.0V in the flash ROM onboard programming mode. Note 2-2: Relationship between tCYC and oscillation frequency is 3/FmCF at a division ratio of 1/1 and 6/FmCF at a division ratio of 1/2. Note 2-3: See Tables 1 and 2 for the oscillation constants. No.A1841-17/29 LC87F7932B Electrical Characteristics at Ta=-40 to +85°C, VSS1=VSS2=0V Parameter High level input current Symbol IIH(1) Pin/Remarks Port 0, 1, 3, 7 LPA, LPB, LPC LPL Conditions VDD[V] • Output disabled • Pull-up resistor off • VIN=VDD (Including output Tr's off leakage current) IIH(2) IIH(3) IIH(4) Low level input current IIL(1) RES XT1, XT2 CF1 Port 0, 1, 3, 7 LPA, LPB, LPC LPL VIN=VDD • For input port specification • VIN=VDD VIN=VDD • Output disabled • Pull-up resistor off • VIN=VSS (Including output Tr's off leakage current) IIL(2) IIL(3) IIL(4) High level output voltage VOH(1) VOH(2) VOH(3) VOH(4) VOH(5) VOH(6) VOH(7) Low level output voltage VOL(1) VOL(2) VOL(3) VOL(4) VOL(5) VOL(6) VOL(7) LCD output voltage regulation VODLS Port 7 XT2 LPA, LPB, LPC LPL S00 to S31 • IO=0mA • V1, V2, V3 LCD level output • See Fig. 8. VODLC COM0 to COM3 • IO=0mA • V1, V2, V3 LCD level output • See Fig. 8. Resistance of pullup MOS Tr. Hysterisis voltage Pin capacitance VHYS(1) CP Port 1, 7 RES All pins • For pins other than that under test: VIN=VSS • f=1MHz • Ta=25°C 2.4 to 3.6 10 pF Rpu(1) Port 0, 1, 3, 7 VOH=0.9VDD 2.4 to 3.6 2.4 to 3.6 18 50 0.1VDD 150 kΩ V Port 3 LPA, LPB, LPC LPL Port 0, 1 IOL=1.6mA IOL=1mA IOL=5mA IOL=2.5mA IOL=1.6mA IOL=1mA IOL=0.1mA Port 71 to 73 Port 3 RES XT1, XT2 CF1 Port 0, 1 VIN=VSS • For input port specification • VIN=VSS VIN=VSS IOH=-0.4mA IOH=-0.2mA IOH=-1.6mA IOH=-1mA IOH=-0.4mA IOH=-0.2mA IOH=-0.1mA 2.4 to 3.6 2.4 to 3.6 2.4 to 3.6 3.0 to 3.6 2.4 to 3.6 3.0 to 3.6 2.4 to 3.6 3.0 to 3.6 2.4 to 3.6 2.4 to 3.6 3.0 to 3.6 2.4 to 3.6 3.0 to 3.6 2.4 to 3.6 3.0 to 3.6 2.4 to 3.6 2.4 to 3.6 -1 -1 -15 VDD-0.4 VDD-0.4 VDD-0.4 VDD-0.4 VDD-0.4 VDD-0.4 VDD-0.4 0.4 0.4 0.4 0.4 0.4 0.4 0.4 V 2.4 to 3.6 -1 2.4 to 3.6 2.4 to 3.6 2.4 to 3.6 1 1 15 μA 2.4 to 3.6 1 min Specification typ max unit 2.4 to 3.6 0 ±0.2 2.4 to 3.6 0 ±0.2 No.A1841-18/29 LC87F7932B Serial I/O Characteristics at Ta = -40°C to +85°C, VSS1 = VSS2 = 0V 1. SIO0 Serial I/O Characteristics (Note 4-1-1) Parameter Frequency Low level pulse width Input clock High level pulse width tSCKH(1) tSCKHA(1) • Continuous data transmission/reception mode Serial clock • See Fig. 6. • (Note 4-1-2) Frequency Low level pulse width Output clock High level pulse width tSCKHA(2) • Continuous data transmission/reception mode • CMOS output selected • See Fig. 6. Data setup time Serial input tsDI(1) SB0(P11), SI0(P11) Data hold time thDI(1) • Must be specified with respect to rising edge of SIOCLK. • See Fig. 6. 2.4 to 3.6 Output delay Input clock time tdD0(1) SO0(P10), SB0(P11) • Continuous data transmission/reception mode • (Note 4-1-3) tdD0(2) tdD0(3) • Synchronous 8-bit mode • (Note 4-1-3) Output clock (Note 4-1-3) 2.4 to 3.6 (1/3)tCYC +0.15 2.4 to 3.6 1tCYC +0.05 2.4 to 3.6 (1/3)tCYC +0.05 μs 0.03 2.4 to 3.6 0.03 tSCKH(2) +2tCYC tSCKH(2) +(10/3) tCYC tCYC tSCKH(2) 2.4 to 3.6 tSCK(2) tSCKL(2) SCK0(P12) • CMOS output selected • See Fig. 6. 1/2 tSCK 1/2 4/3 4 2.4 to 3.6 tCYC Symbol tSCK(1) tSCKL(1) Pin/Remarks SCK0(P12) Conditions VDD[V] See Fig. 6. min 2 1 1 Specification typ max unit Note 4-1-1: These specifications are theoretical values. Add margin depending on its use. Note 4-1-2: To use serial-clock-input in continuous trans/rec mode, a time from SI0RUN being set when serial clock is "H" to the first negative edge of the serial clock must be longer than tSCKHA. Note 4-1-3: Must be specified with respect to falling edge of SIOCLK. Must be specified as the time to the beginning of output state change in open drain output mode. See Fig. 6. Serial output No.A1841-19/29 LC87F7932B 2. SIO1 Serial I/O Characteristics (Note 4-2-1) Parameter Frequency Input clock Low level pulse width High level pulse width Output clock Frequency Low level pulse width High level pulse width Data setup time Serial input tsDI(2) SB1(P14), SI1(P14) Data hold time thDI(2) • Must be specified with respect to rising edge of SIOCLK. • See Fig. 6. 2.4 to 3.6 Output delay time Serial output tdD0(4) SO1(P13), SB1(P14) • Must be specified with respect to falling edge of SIOCLK. • Must be specified as the time to the beginning of output state change in open drain output mode. • See Fig. 6. 2.4 to 3.6 (1/3)tCYC +0.05 0.03 2.4 to 3.6 0.03 tSCKH(4) tSCK(4) tSCKL(4) SCK1(P15) • CMOS output selected • See Fig. 6. 2.4 to 3.6 1/2 tSCK 1/2 tSCKH(3) Symbol tSCK(3) tSCKL(3) 2.4 to 3.6 Pin/Remarks SCK1(P15) Conditions VDD[V] See Fig. 6. min 2 1 tCYC 1 2 Specification typ max unit Serial clock μs Note 4-2-1: These specifications are theoretical values. Add margin depending on its use. Pulse Input Conditions at Ta = -40°C to +85°C, VSS1 = VSS2 = 0V Parameter High/low level pulse width Symbol tPIH(1) tPIL(1) tPIH(2) tPIL(2) tPIH(3) tPIL(3) tPIH(4) tPIL(4) tPIL(5) Pin/Remarks INT0(P70), INT1(P71), INT2(P72) INT3(P73) when noise filter time constant is 1/1 INT3(P73) when noise filter time constant is 1/32 INT3(P73) when noise filter time constant is 1/128 RES Conditions VDD[V] • Interrupt source flag can be set. • Event inputs for timer 0 or 1 are enabled. • Interrupt source flag can be set. • Event inputs for timer 0 are enabled. • Interrupt source flag can be set. • Event inputs for timer 0 are enabled. • Interrupt source flag can be set. • Event inputs for timer 0 are enabled. Resetting is enabled. 2.4 to 3.6 200 μs 2.4 to 3.6 256 2.4 to 3.6 64 2.4 to 3.6 2 tCYC 2.4 to 3.6 1 min Specification typ max unit No.A1841-20/29 LC87F7932B AD Converter Characteristics at VSS1 = VSS2 = 0V Parameter Resolution Absolute accuracy Conversion time TCAD N ET Symbol Pin/Remarks AN0(P00) to AN4(P04), AN5(P70) to AN6(P71) • See Conversion time calculation formulas. (Note 6-2) Analog input voltage range Analog port input current IAINH IAINL VAIN=VDD VAIN=VSS VAIN 3.0 to 3.6 3.0 to 3.6 3.0 to 3.6 -1 VSS VDD 1 V μA 3.0 to 3.6 64 115 μs (Note 6-1) Conditions VDD[V] 3.0 to 3.6 3.0 to 3.6 min Specification typ 12 ±16 max unit bit LSB Parameter Resolution Absolute accuracy Conversion time TCAD N ET Symbol Pin/Remarks AN0(P00) to AN4(P04), AN5(P70) to AN6(P71) • See Conversion time calculation formulas. (Note 6-2) Analog input voltage range Analog port input current IAINH IAINL VAIN=VDD VAIN=VSS VAIN 3.0 to 3.6 3.0 to 3.6 3.0 to 3.6 -1 VSS VDD 1 V μA 3.0 to 3.6 40 90 μs (Note 6-1) Conditions VDD[V] 3.0 to 3.6 3.0 to 3.6 min Specification typ 8 ±1.5 max Unit bit LSB Conversion Time Calculation Formulas: 12bits AD Converter Mode : TCAD(Conversion time) = ((52/(division ratio))+2)×(1/3)×tCYC 8bits AD Converter Mode : TCAD(Conversion time) = ((32/(division ratio))+2)×(1/3)×tCYC External oscillation (FmCF) CF-4MHz Operating supply voltage range (VDD) 3.0V to 3.6V System division ratio (SYSDIV) 1/1 Cycle time (tCYC) 750ns AD division ratio (ADDIV) 1/8 12bit AD 104.5μs AD conversion time (TCAD) 8bit AD 64.5μs Note 6-1: The quantization error (±1/2LSB) must be excluded from the absolute accuracy. The absolute accuracy must be measured in the microcontroller's state in which no I/O operations occur at the pins adjacent to the analog input channel. Note 6-2: The conversion time refers to the period from the time an instruction for starting a conversion process till the time the conversion results register(s) are loaded with a complete digital conversion value corresponding to the analog input value. The conversion time is 2 times the normal-time conversion time when: • The first AD conversion is performed in the 12-bit AD conversion mode after a system reset. • The first AD conversion is performed after the AD conversion mode is switched from 8-bit to 12-bit conversion mode. No.A1841-21/29 LC87F7932B Current Consumption Characteristics at Ta = -40°C to +85°C, VSS1 = VSS2 = 0V Parameter Current consumption during normal operation (Note 7-1) IDDOP(2) Symbol IDDOP(1) Pin VDD1= VDD2=V2 Conditions VDD[V] • FmCF=4MHz Ceramic resonator oscillation • FsX’tal=32.768kHz crystal oscillation • System clock: CF 4MHz oscillation • Internal RC oscillation stopped. • Divider: 1/1 • FmCF=0Hz (No oscillation) • FsX’tal=32.768kHz crystal oscillation • System clock: Fast RC oscillation • Divider:1/1 IDDOP(3) • FmCF=0Hz (No oscillation) • FsX’tal=32.768kHz crystal oscillation • System clock: Slow RC oscillation • Divider:1/1 IDDOP(4) • FmCF=0Hz (No oscillation) • FsX’tal=32.768kHz crystal oscillation • Internal RC oscillation stopped. • System clock: VMRC oscillation (4MHz) • Divider :1/1 IDDOP(5) • FmCF=0Hz (No oscillation) • FsX’tal=32.768kHz crystal oscillation • Internal RC oscillation stopped. • System clock: VMRC oscillation (500KHz) • Divider: 1/1 IDDOP(6) • FmCF=0Hz (No oscillation) • FsX’tal=32.768kHz crystal oscillation • System clock: 32.768kHz • Internal RC oscillation stopped. • Divider: 1/1 • Normal XT Amp mode IDDOP(7) • FmCF=0Hz (No oscillation) • FsX’tal=32.768kHz crystal oscillation • System clock: 32.768kHz • Internal RC oscillation stopped. • Divider: 1/1 • Low XT Amp mode 2.4 to 3.6 15 72 2.4 to 3.6 20 86 μA 2.4 to 3.6 250 900 2.4 to 3.6 2.0 5.4 mA 2.4 to 3.6 30 120 2.4 to 3.6 250 900 μA 2.4 to 3.6 2.0 4.2 mA min Specification typ max unit Note 7-1: The currents through the output transistors and the pull-up MOS transistors are ignored. Continued on next page. No.A1841-22/29 LC87F7932B Continued from preceding page. Parameter Current consumption during HALT mode (Note 7-1) Symbol IDDHALT(1) Pin VDD1= VDD2=V2 HALT mode • FmCF=4MHz Ceramic resonator oscillation • FsX’tal=32.768kHz crystal oscillation • System clock : CF 4MHz oscillation • Internal RC oscillation stopped • Divider: 1/1 IDDHALT(2) HALT mode • FmCF=0Hz (No oscillation) • FsX’tal=32.768kHz crystal oscillation • System clock: Fast RC oscillation • Divider: 1/1 IDDHALT(3) HALT mode • FmCF=0Hz (No oscillation) • FsX’tal=32.768kHz crystal oscillation • System clock: Slow RC oscillation • Divider: 1/1 IDDHALT(4) HALT mode • FmCF=0Hz (No oscillation) • FsX’tal=32.768kHz crystal oscillation • Internal RC oscillation stopped • System clock: VMRC oscillation (4MHz) • Divider: 1/1 IDDHALT(5) HALT mode • FmCF=0Hz (No oscillation) • FsX’tal=32.768kHz crystal oscillation • Internal RC oscillation stopped. • System clock: VMRC oscillation (500kHz) • Divider: 1/1 IDDHALT(6) HALT mode • FmCF=0Hz (Oscillation stop) • FsX’tal=32.768kHz crystal oscillation • System clock : 32.768kHz • Internal RC oscillation stopped. • Divider: 1/1 • Normal XT Amp mode IDDHALT(7) HALT mode • FmCF=0Hz (Oscillation stop) • FsX’tal=32.768kHz crystal oscillation • System clock : 32.768kHz • Internal RC oscillation stopped. • Divider: 1/1 • Low XT Amp mode 2.4 to 3.6 4 50 2.4 to 3.6 8 70 2.4 to 3.6 68 280 μA 2.4 to 3.6 650 1460 2.4 to 3.6 7 85 2.4 to 3.6 68 280 2.4 to 3.6 0.55 1.55 mA Conditions VDD[V] min Specification typ max unit Note 7-1: The currents through the output transistors and the pull-up MOS transistors are ignored. Continued on next page. No.A1841-23/29 LC87F7932B Continued from preceding page. Parameter Current consumption during HOLD mode Current consumption during Date/time clock HOLD mode IDDHOLD(2) Date/time clock HOLD mode • CF1=VDD or open (when using external clock) • FmX’tal=32.768kHz crystal oscillation • LCD display off • Normal XT Amp mode IDDHOLD(3) Date/time clock HOLD mode • CF1=VDD or open (when using external clock) • FmX’tal=32.768kHz crystal oscillation • LCD display off • Low XT Amp mode IDDHOLD(4) Date/time clock HOLD mode • CF1=VDD or open (when using external clock) • FsRC=Slow RC oscillation (Typ.50kHz) • LCD display off 2.4 to 3.6 1.5 70 2.4 to 3.6 0.45 46 μA 2.4 to 3.6 6.5 67 Symbol IDDHOLD(1) Pin VDD1= VDD2=V2 HOLD mode • CF1=VDD or open (when using external clock) 2.4 to 3.6 0.05 30 Conditions VDD[V] min Specification typ max unit No.A1841-24/29 LC87F7932B F-ROM Programming Characteristics at Ta = +10°C to +55°C, VSS1 = VSS2 = 0V Parameter Onboard programming current Programming time tFW(1) • Erasing time • Programming time 3.0 to 5.5 20 45 30 60 ms μs Symbol IDDFW(1) Pin/Remarks VDD1 Conditions VDD[V] • 128-byte programming • Erasing current included 3.0 to 5.5 5 10 mA min Specification typ max unit UART (Full Duplex) Operating Conditions at Ta = -40°C to +85°C, VSS1 = VSS2 = 0V Parameter Transfer rate Symbol UBR Pin/Remarks UTX(P00), URX(P01) Conditions VDD[V] 2.4 to 3.6 min 16/3 Specification typ max 8192/3 unit tCYC Data length: Stop bits : Parity bits: 7/8/9 bits (LSB first) 1 bit (2-bit in continuous data transmission) None Example of 8-bit Data Transmission Mode Processing (Transmit Data=55H) Start bit Stop bit Transmit data (LSB first) End of transmission Start of transmission UBR Example of 8-bit Data Reception Mode Processing (Receive Data=55H) Start bit Start of reception Receive data (LSB first) Stop bit End of reception UBR No.A1841-25/29 LC87F7932B Characteristics of a Sample Main System Clock Oscillation Circuit Given below are the characteristics of a sample main system clock oscillation circuit that are measured using a SANYO-designated oscillation characteristics evaluation board and external components with circuit constant values with which the oscillator vendor confirmed normal and stable oscillation. Table 1 Characteristics of a Sample Main System Clock Oscillator Circuit with a Ceramic Oscillator Nominal Frequency Vendor Name Circuit Constant Oscillator Name C1 [pF] 4.00MHz Murata CSTCR4M00G53-R0 CSTLS4M00G53-B0 (15) (15) C2 [pF] (15) (15) Rf1 [Ω] Open Open Rd1 [Ω] 1k 1k Operating Voltage Range [V] 2.4 to 3.6 2.4 to 3.6 Oscillation Stabilization Time typ [ms] 0.03 0.02 max [ms] 0.15 0.15 Internal C1, C2 Remarks The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized after VDD goes above the operating voltage lower limit (see Figure 4). • Till the oscillation gets stabilized after the instruction for starting the main clock oscillation circuit is executed. • Till the oscillation gets stabilized after the HOLD mode reset. • Till the oscillation gets stabilized after the HOLD mode reset with CFSTOP(the OCR register bit0)=0. Characteristics of a Sample Subsystem Clock Oscillator Circuit Given below are the characteristics of a sample subsystem clock oscillation circuit that are measured using a SANYOdesignated oscillation characteristics evaluation board and external components with circuit constant values with which the oscillator vendor confirmed normal and stable oscillation. Table 2 Characteristics of a Sample Subsystem Clock Oscillator Circuit with a Crystal Oscillator Nominal Frequency Vendor Name Circuit Constant Oscillator Name C3 [pF] 9 32.768KHz Epson Toyocom MC-306 3 3 0 2.4 to 3.6 2 6 C4 [pF] 9 Rf2 [Ω] Rd2 [Ω] 330k Operating Voltage Range [V] 2.4 to 3.6 Oscillation Stabilization Time typ [s] 1 max [s] 3 CL=7.0pF Normal mode CL=7.0pF Low Amp mode Remarks The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized after the instruction for starting the subclock oscillation circuit is executed and to the time interval that is required for the oscillation to get stabilized after the HOLD mode with EXTOSC (the OCR register bit6)=1 is reset (see Figure 4). Note: The components that are involved in oscillation should be placed as close to the IC and to one another as possible because they are vulnerable to the influences of the circuit pattern. CF1 Rf1 CF2 XT1 Rf2 XT2 Rd1 Rd2 C1 CF C2 C3 X’tal C4 Figure 1 CF Oscillator Circuit Figure 2 XT Oscillator Circuit 0.5VDD Figure 3 AC Timing Measurement Point No.A1841-26/29 LC87F7932B VDD Power supply VDD limit 0V Reset time RES Internal RC Resonator oscillation tmsCF CF1, CF2 tmsX’tal XT1, XT2 Execute oscillation enable command Operating mode Unfixed Reset Instruction execution mode Reset Time and Oscillation Stabilizing Time HOLD reset signal Without HOLD Release HOLD reset signal VALID Internal RC Resonator oscillation tmsCF CF1, CF2 tmsX’tal XT1, XT2 Operation mode HOLD HALT HOLD Release Signal and Oscillation Stable Time Note: External oscillation circuit is selected. Figure 4 Oscillation Stabilization Times No.A1841-27/29 LC87F7932B VDD RRES RES CRES Note: External circuits for reset may vary depending on the usage of POR. Please refer to the user’s manual for more information. Figure 5 Reset Circuit SIOCLK: DATAIN: DI0 DI1 DI2 DI3 DI4 DI5 DI6 DI7 DI8 DATAOUT: DO0 DO1 DO2 DO3 DO4 DO5 DO6 DO7 Data RAM transmission period (SIO0 only) DO8 tSCK tSCKL SIOCLK: tsDI DATAIN: tdDO DATAOUT: Data RAM transmission period (SIO0 only) tSCKL SIOCLK: tsDI DATAIN: tdDO DATAOUT: thDI tSCKHA thDI tSCKH Figure 6 Serial Input/Output Wave Form tPIL tPIH Figure 7 Pulse Input No.A1841-28/29 LC87F7932B POR release voltage (PORRL) (a) (b) VDD Reset period Unknown-state (POUKS) RES 1000μs or longer Reset period Figure 8 Waveform observed when POR is used (RESET pin: Pull-up resistor RRES only) • The POR function generates a reset only when power is turned on starting at the VSS level. • No stable reset will be generated if power is turned on again when the power level does not go down to the VSS level as shown in (a). • A reset is generated only when the power level goes down to the VSS level as shown in (b) and power is turned on again after this condition continues for 1000μs or longer. SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein. SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO Semiconductor Co.,Ltd. products described or contained herein are controlled under any of applicable local export control laws and regulations, such products may require the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written consent of SANYO Semiconductor Co.,Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO Semiconductor Co.,Ltd. product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. Upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third party. SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's intellectual property rights which has resulted from the use of the technical information and products mentioned above. T his catalog provides information as of July, 2010. Specifications and information herein are subject to change without notice. PS No.A1841-29/29