LC87F7J32A

Ordering number : ENA0886 LC87F7J32A Overview CMOS IC FROM 32K byte, RAM 1024 byte on-chip 8-bit 1-chip Microcontroller The SANYO LC87F7J32A is an 8-bit microcomputer that, centered around a CPU running at a minimum bus cycle time of 83.3ns, integrates on a single chip a number of hardware features such as 32K-byte flash ROM (onboard programmable), 1024-byte RAM, an on-chip debugger, a LCD controller/driver, sophisticated 16-bit timer/counter (may be divided into 8-bit timers), a 16-bit timer/counter (may be divided into 8-bit timers/counters or 8-bit PWMs), four 8-bit timers with a prescaler, a 16-bit timer with a prescaler (may be divided into 8-bit timers), a base timer serving as a timeof-day clock, a day and time counter, a synchronous SIO interface (with automatic block transmission/reception capabilities), an asynchronous/synchronous SIO interface, a UART interface (full duplex), two 12-bit PWM channels, a 12-bit/8-bit 10-channel AD converter, remote control receive function, a high-speed clock counter, a system clock frequency divider, an internal reset and a 25-source 10-vector interrupt feature. Features Flash ROM • Capable of on-board-programming with wide range, 3.0 to 5.5V,of voltage souce • Block-erasable in 128-byte units • 32768 × 8 bits RAM • 1024 × 9 bits Minimum Bus Cycle Time • 83.3ns (12MHz) VDD=3.0 to 5.5V • 125ns (8MHz) VDD=2.5 to 5.5V • 250ns (4MHz) VDD=2.2 to 5.5V Note: The bus cycle time here refers to the ROM read speed. Minimum Instruction Cycle Time (tCYC) • 250ns (12MHz) VDD=3.0 to 5.5V • 375ns (8MHz) VDD=2.5 to 5.5V • 750ns (4MHz) VDD=2.2 to 5.5V * This product is licensed from Silicon Storage Technology, Inc. (USA), and manufactured and sold by SANYO Semiconductor Co., Ltd. Ver1.00 O1707HKIM 20071009-S00002 No.A0886-1/29 LC87F7J32A Ports • Normal withstand voltage I/O ports Ports whose I/O direction can be designated in 1 bit units 15 (P1n, P30 to P31, P70 to P73, XT2) Ports whose I/O direction can be designated in 4 bit units 8 (P0n) (When N-channel open drain output is selected, data can be input in bit units.) • Normal withstand voltage input port 1 (XT1) • LCD ports Segment output 24 (S00 to S23) Common output 4 (COM0 to COM3) Bias terminals for LCD driver 3 (V1 to V3) Other functions Input/output ports 24 (PAn, PBn, PCn,) Input ports 7 (PLn) • Dedicated oscillator ports 2 (CF1, CF2) • Reset pin 1 (RES) • Power pins 6 (VSS1 to VSS3, VDD1 to VDD3) LCD Controller 1) Seven display modes are available (static, 1/2, 1/3, 1/4 duty × 1/2, 1/3 bias) 2) Segment output and common output can be switched to general-purpose input/output ports Timers • Timer 0: 16-bit timer/counter with two capture registers. Mode 0: 8-bit timer with an 8-bit programmable prescaler (with two 8-bit capture registers) × 2 channels Mode 1: 8-bit timer with an 8-bit programmable prescaler (with two 8-bit capture registers) + 8-bit counter (with two 8-bit capture registers) Mode 2: 16-bit timer with an 8-bit programmable prescaler (with two 16-bit capture registers) Mode 3: 16-bit counter (with two 16-bit capture registers) • Timer 1: 16-bit timer that supports PWM/toggle outputs Mode 0: 8-bit timer with an 8-bit prescaler (with toggle outputs) + 8-bit timer/counter with an 8-bit prescaler (with toggle outputs) Mode 1: 8-bit PWM with an 8-bit prescaler × 2 channels Mode 2: 16-bit timer/counter with an 8-bit prescaler (with toggle outputs) (toggle outputs also possible from the lower-order 8 bits) Mode 3: 16-bit timer with an 8-bit prescaler (with toggle outputs) (The lower-order 8 bits can be used as PWM.) • Timer 4: 8-bit timer with a 6-bit prescaler • Timer 5: 8-bit timer with a 6-bit prescaler • Timer 6: 8-bit timer with a 6-bit prescaler (with toggle output) • Timer 7: 8-bit timer with a 6-bit prescaler (with toggle output) • Timer 8: 16-bit timer Mode 0: 8-bit timer with an 8-bit prescaler × 2 channels (with toggle output) Mode 1: 16-bit timer with an 8-bit prescaler (with toggle output) • Base timer 1) The clock is selectable from the subclock (32.768kHz crystal oscillation), system clock, and timer 0 prescaler output. 2) Interrupts programmable in 5 different time schemes • Day and time counter 1) Using with a base timer,it can be used as 65000 day + minute + second counter. High-speed Clock Counter 1) Can count clocks with a maximum clock rate of 20MHz (at a main clock of 10MHz). 2) Can generate output real-time. No.A0886-2/29 LC87F7J32A SIO • SIO0: 8-bit synchronous serial interface 1) LSB first/MSB first mode selectable 2) Built-in 8-bit baudrate generator (maximum transfer clock cycle = 4/3 tCYC) 3) Automatic continuous data transmission (1 to 256 bits specifiable in 1-bit units, suspension and resumption of data transmission possible in 1-byte units) • SIO1: 8-bit asynchronous/synchronous serial interface Mode 0: Synchronous 8-bit serial I/O (2- or 3-wire configuration, 2 to 512 tCYC transfer clocks) Mode 1: Asynchronous serial I/O (half-duplex, 8-data bits, 1-stop bit, 8 to 2048 tCYC baudrates) Mode 2: Bus mode 1 (start bit, 8-data bits, 2 to 512 tCYC transfer clocks) Mode 3: Bus mode 2 (start detect, 8-data bits, stop detect) UART • Full duplex • 7/8/9 bit data bits selectable • 1 stop bit (2-bit in continuous data transmission) • Built-in baudrate generator AD Converter: 12-bits/8-bits × 12 channels • 12 bits/8 bits AD converter resolution selectable PWM: Multi frequency 12-bit PWM × 2 channels Infrared Remote Control Receiver Circuit 1) Noise reduction function (noise filter time constant: Approx. 120μs, when the 32.768kHz crystal oscillator is selected as the reference voltage source.) 2) Supports data encoding systems such as PPM (Pulse Position Modulation) and Manchester encoding 3) X’tal HOLD mode release function Watchdog Timer • External RC watchdog timer • Basetimer watchdog timer • Interrupt and reset signals selectable Clock Output Function 1) Able to output selected oscillation clock 1/1, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64 as system clock. 2) Able to output oscillation clock of sub clock. No.A0886-3/29 LC87F7J32A Interrupts • 25 sources, 10 vector addresses 1) Provides three levels (low (L), high (H), and highest (X)) of multiplex interrupt control. Any interrupt requests of the level equal to or lower than the current interrupt are not accepted. 2) When interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest level takes precedence over the other interrupts. For interrupts of the same level, the interrupt into the smallest vector address takes precedence. No. 1 2 3 4 5 6 7 8 9 10 Vector Address 00003H 0000BH 00013H 0001BH 00023H 0002BH 00033H 0003BH 00043H 0004BH Level X or L X or L H or L H or L H or L H or L H or L H or L H or L H or L INT0 INT1 INT2/T0L/INT4/remote control receiver INT3/INT5/BT0/BT1 T0H T1L/T1H SIO0/UART1 receive SIO1/UART1 transmit ADC//T6/T7/PWM4/PWM5 Port 0/T4/T5 Interrupt Source • Priority levels X > H > L • Of interrupts of the same level, the one with the smallest vector address takes precedence. • IFLG (List of interrupt source flag function) 1) Shows a list of interrupt source flags that caused a branching to a particular vector address (shown in the diagram above). Subroutine Stack Levels: 512 levels (The stack is allocated in RAM.) High-speed Multiplication/Division Instructions • 16 bits × 8 bits (5 tCYC execution time) • 24 bits × 16 bits (12 tCYC execution time) • 16 bits ÷ 8 bits (8 tCYC execution time) • 24 bits ÷ 16 bits (12 tCYC execution time) Oscillation Circuits • RC oscillation circuit (internal): For system clock • CF oscillation circuit: For system clock, with internal Rf • Crystal oscillation circuit: For low-speed system clock, with internal Rf • Frequency variable RC oscillation circuit (internal): For system clock 1) Adjustable in ±4% (typ) step from a selected center frequency. 2) Measures oscillation clock using a input signal from XT1 as a reference. System Clock Divider Function • Can run on low current. • The minimum instruction cycle selectable from 300ns, 600ns, 1.2μs, 2.4μs, 4.8μs, 9.6μs, 19.2μs, 38.4μs, and 76.8μs (at a main clock rate of 10MHz). Internal Reset Function • Power-On-Reset (POR) function 1) POR resets the system when the power supply voltage is applied. 2) POR release level is selectable from 4 levels (2.07V, 2.37V, 2.87V, 4.35V) by option. • Low Voltage Detection reset (LVD) function 1) LVD used with POR resets the system when the supply voltage is applied and when it is lowered. 2) LVD function is selectable from enable/disable and the reset level is selectable from 3 levels (2.31V, 2.81V, 4.28V) by option. No.A0886-4/29 LC87F7J32A Standby Function • HALT mode: Halts instruction execution while allowing the peripheral circuits to continue operation. (Some parts of the serial transfer function stops operation) 1) Oscillation is not halted automatically. 2) Canceled by a system reset or occurrence of an interrupt • HOLD mode: Suspends instruction execution and the operation of the peripheral circuits. 1) The CF, RC, X’tal, and frequency variable RC oscillators automatically stop operation. 2) There are three ways of resetting the HOLD mode. (1) Setting the reset pin to the low level (2) Setting at least one of the INT0, INT1, INT2, INT4, and INT5, pins to the specified level (3) Having an interrupt source established at port 0 • X'tal HOLD mode: Suspends instruction execution and the operation of the peripheral circuits except the base timer and the remote control circuit. 1) The CF, RC, and frequency variable RC oscillators automatically stop operation 2) The state of crystal oscillation established when the X'tal HOLD mode is entered is retained. 3) There are five ways of resetting the X'tal HOLD mode. (1) Setting the reset pin to the low level (2) Setting at least one of the INT0, INT1, INT2, INT4,and INT5 pins to the specified level (3) Having an interrupt source established at port 0 (4) Having an interrupt source established in the base timer circuit (5) Having an interrupt source established in the infrared remote control receiver circuit On-chip Debugger • Supports software debugging with the IC mounted on the target board. Package Form • QIP64E(14×14): • TQFP64J(10×10): Lead-free type Lead-free type Development Tools • On-chip debugger: TCB87-TypeB + LC87F7J32A Flash ROM Programming Board Package QIP64E(14×14) TQFP64J(10×10) Programming boards W87F50256Q W87F57256SQ Flash ROM Programmer Maker Single Flash Support Group, Inc. (Formerly Ando Electric Co., Ltd.) Gang Model AF9708/AF9709/ AF9709B AF9723 (Main body) AF9833 (Unit) SANYO SKK (SANYO FWS) Supported Version (Note) After 0x.xx After 0x.xx After 0x.xx After x.xxA LC87F7J32A Device Note: Please check the latest version. Same Package and Pin Assignment as Mask ROM Version. 1) LC877J00 series options can be set by using flash ROM data. Thus the board used for mass production can be used for debugging and evaluation without modifications. 2) If the program for the mask ROM version is used, the usable ROM/RAM capacity is the same as the mask ROM version. No.A0886-5/29 LC87F7J32A Package Dimensions unit : mm (typ) 3159A 17.2 14.0 48 49 33 32 14.0 64 1 0.8 (1.0) (2.7) 17 16 0.35 0.15 3.0max 0.1 SANYO : QIP64E(14X14) Package Dimensions unit : mm (typ) 3310 12.0 48 49 33 32 10.0 64 1 0.5 (1.25) 16 0.18 17 12.0 0.125 1.2 MAX 0.1 (1.0) SANYO : TQFP64J(10X10) 0.5 10.0 17.2 0.8 No.A0886-6/29 LC87F7J32A Pin Assignment COM3/PL3 COM2/PL2 COM1/PL1 COM0/PL0 S23/PC7 S22/PC6 S21/PC5 S20/PC4 S19/PC3 S18/PC2 S17/PC1 S16/PC0 S15/PB7 VDD3 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 P70/INT0/T0LCP/AN8 P71/INT1/T0HCP/AN9 P72/INT2/T0IN/NKIN P73/INT3/T0IN/RMIN RES XT1/AN10 XT2/AN11 VSS1 CF1 CF2 VDD1 V1/PL4/AN0/DBGP0 V2/PL5/AN1/DBGP1 V3/PL6/AN2/DBGP2 P10/SO0 P11/SI0/SB0 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 1 P12/SCK0 2 P13/SO1 3 P14/SI1/SB1 4 P15/SCK1 5 P16/ T1PWML 6 P17/T1PWMH/BUZ 7 P30/INT4/T1IN/T0LCP/PWM4 8 P31/INT5/T1IN/T0HCP/PWM5 9 10 11 12 13 14 15 16 VDD2 VSS2 P00/AN3 P01/AN4 P02/AN5 P03/AN6 P04/AN7 P05/CKO 32 31 30 29 28 27 26 S13/PB5 S12/PB4 S11/PB3 S10/PB2 S9/PB1 S8/PB0 S7/PA7 S6/PA6 S5/PA5 S4/PA4 S3/PA3 S2/PA2 S1/PA1/URX1 S0/PA0/UTX1 P07/T7O P06/T6O VSS3 S14/PB6 25 24 23 22 21 20 19 18 17 LC87F7J32A Top view SANYO: QIP64E(14×14) SANYO: TQFP64J(10×14) “Lead-free Type” “Lead-free Type” No.A0886-7/29 LC87F7J32A PIN No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 NAME P12/SCK0 P13/SO1 P14/SI1/SB1 P15/SCK1 P16/T1PWML P17/T1PWMH/BUZ P30/INT4/T1IN/T0LCP1/PWM4 P31/INT5/T1IN/T0HCP1/PWM5 VDD2 VSS2 P00/AN3 P01/AN4 P02/AN5 P03/AN6 P04/AN7 P05/CKO P06/T6O P07/T7O S0/PA0/UTX1 S1/PA1/URX1 S2/PA2 S3/PA3 S4/PA4 S5/PA5 S6/PA6 S7/PA7 S8/PB0 S9/PB1 S10/PB2 S11/PB3 S12/PB4 S13/PB5 PIN No. 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 NAME S14/PB6 S15/PB7 VSS3 VDD3 S16/PC0 S17/PC1 S18/PC2 S19/PC3 S20/PC4 S21/PC5 S22/PC6 S23/PC7 COM0/PL0 COM1/PL1 COM2/PL2 COM3/PL3 P70/INT0/T0LCP/AN8 P71/INT1/T0HCP/AN9 P72/INT2/T0IN P73/INT3/T0IN RES XT1/AN10 XT2/AN11 VSS1 CF1 CF2 VDD1 V1/PL4/AN0/DBGP0 V2/PL5/AN1/DBGP1 V3/PL6/AN2/DBGP2 P10/SO0 P11/SI0/SB0 No.A0886-8/29 LC87F7J32A System Block Diagram Interrupt control IR PLA Standby control Flash ROM CF RC VMRC X’tal RES Reset control ACC Clock generator PC WTD Reset circuit (LVD/POR) B register C register SIO0 Bus interface ALU SIO1 Port 0 Base timer Port 1 PSW Timer 0 (High speed clock counter) ADC RAR Timer 1 Port 3 RAM Timer 6 Port 7 Stack pointer Timer 7 Watchdog timer INT0 to 5 Noise Rejection Filter On-chip debugger LCD Controller PWM4 PWM5 UART1 Timer 4 Remote control receiver circuit Day and time counter Timer 5 No.A0886-9/29 LC87F7J32A Pin Description Pin Name VSS1 VSS2 VSS3 VDD1 VDD2 VDD3 PORT0 P00 to P07 I/O • 8-bit I/O port • I/O specifiable in 4-bit units • Pull-up resistors can be turned on and off in 4-bit units. • Input for HOLD release • Input for port 0 interrupt • Shared pins P00 to P04: AD converter input (AN3 to AN7) P05: Clock output (system clock/can selected from sub clock) P06: Timer 6 toggle output P07: Timer 7 toggle output PORT1 P10 to P17 I/O • 8-bit I/O port • I/O specifiable in 1-bit units • Pull-up resistors can be turned on and off in 1-bit units. • Shared pins P10: SIO0 data output P11: SIO0 data input/bus I/O P12: SIO0 clock I/O P13: SIO1 data output P14: SIO1 data input/bus I/O P15: SIO1 clock I/O P16: Timer 1PWML output P17: Timer 1PWMH output/beeper output PORT3 P30 to P31 I/O • 2-bit I/O port • I/O specifiable in 1-bit units • Pull-up resistors can be turned on and off in 1-bit units. • Shared pins P30: INT4 input/HOLD release input/timer 1 event input/timer 0L capture input/PWM4 P31: INT5 input/HOLD release input/timer 1 event input/timer 0L capture input/PWM5 • Interrupt acknowledge type Rising INT4 INT5 PORT7 P70 to P73 I/O • 4-bit I/O port • I/O specifiable in 1-bit units • Pull-up resistors can be turned on and off in 1-bit units. • Shared pins P70: INT0 input/HOLD release input/timer 0L capture input/watchdog timer output P71: INT1 input/HOLD release input/timer 0H capture input P72: INT2 input/HOLD release input/timer 0 event input/timer 0L capture input/ high speed clock counter input P73: INT3 input (with noise filter)/timer 0 event input/timer 0H capture input/ remote control receiver input AD converter input ports: AN8 (P70), AN9 (P71) • Interrupt acknowledge type Rising INT0 INT1 INT2 INT3 enable enable enable enable Falling enable enable enable enable Rising & Falling disable disable enable enable H level enable enable disable disable L level enable enable disable disable enable enable Falling enable enable Rising & Falling enable enable H level disable disable L level disable disable No Yes Yes Yes I/O - power supply pin Description Option No - + power supply pin No Continued on next page. No.A0886-10/29 LC87F7J32A Continued from preceding page. Pin Name S0/PA0 to S7/PA7 S8/PB0 to S15/PB7 S16/PC0 to S23/PC7 COM0/PL0 to COM3/PL3 V1/PL4 to V3/PL7 I/O I/O I/O I/O I/O I/O • Segment output for LCD • Can be used as general-purpose I/O port (PA) • Segment output for LCD • Can be used as general-purpose I/O port (PB) • Segment output for LCD • Can be used as general-purpose I/O port (PC) • Common output for LCD • Can be used as general-purpose input port (PL) • LCD output bias power supply • Can be used as general-purpose input port (PL) • Shared pins AD converter input ports: AN0 (V1) to AN2 (V3) On-chip debugger pins: DBGP0 (V1) to DBGP2 (V3) RES XT1 Input Input Reset pin • 32.768kHz crystal oscillator input pin • Shared pins General-purpose input port AD converter input port: AN10 Must be connected to VDD1 if not to be used. XT2 I/O • 32.768kHz crystal oscillator output pin • Shared pins General-purpose I/O port AD converter input port: AN11 Must be set for oscillation and kept open if not to be used. CF1 CF2 Input Output Ceramic resonator input pin Ceramic resonator output pin No No No No No No No No No Description Option No No.A0886-11/29 LC87F7J32A Port Output Types The table below lists the types of port outputs and the presence/absence of a pull-up resistor. Data can be read into any input port even if it is in the output mode. Port Name P00 to P07 Option Selected in Units of 1 bit Option Type 1 2 P10 to P17 1 bit 1 2 P30 to P31 1 bit 1 2 P70 P71 to P73 S0/PA0 to S23/PC7 COM0/PL0 to COM3/PL3 V1/PL4 to V3/PL6 XT1 XT2 No No No No No No No CMOS N-channel open drain CMOS N-channel open drain CMOS N-channel open drain N-channel open drain CMOS CMOS Input only Input only Input for 32.768 kHz crystal oscillator (Input only) Output for 32.768kHz crystal oscillator (Nch-open drain when in general-purpose output mode) Output Type Pull-up Resistor Programmable (Note) No Programmable Programmable Programmable Programmable Programmable Programmable Programmable No No No No Note1: Programmable pull-up resistors for port 0 are controlled in 4 bit units (P00 to 03, P04 to 07). *1 Connect the IC as shown below to minimize the noise input to the VDD1 pin. Be sure to electrically short the VSS1, VSS2, and VSS3 pins. LSI VDD1 Power supply For backup VDD2 VDD3 VSS1 VSS2 VSS3 *2 The internal memory is sustained by VDD1. If none of VDD2 and VDD3 are backed up, the high level output at the ports are unstable in the HOLD backup mode, allowing through current to flow into the input buffer and thus shortening the backup time. Make sure that the port outputs are held at the low level in the HOLD backup mode. No.A0886-12/29 LC87F7J32A Absolute Maximum Ratings at Ta = 25°C, VSS1 = VSS2 = VSS3 = 0V Parameter Maximum supply voltage supply voltage for LCD Input voltage Input/output voltage Peak output current IOPH(2) IOPH(3) Mean output current High level output current (Note 1-1) IOMH(2) IOMH(3) Total output current ΣIOAH(1) ΣIOAH(2) ΣIOAH(3) ΣIOAH(4) ΣIOAH(5) ΣIOAH(6) ΣIOAH(7) ΣIOAH(8) ΣIOAH(9) Peak output current IOPL(2) IOPL(3) Mean output current Low level output current (Note 1-1) IOML(2) IOML(3) Total output current ΣIOAL(1) ΣIOAL(2) ΣIOAL(3) ΣIOAL(4) ΣIOAL(5) ΣIOAL(6) ΣIOAL(7) ΣIOAL(8) ΣIOAL(9) Power dissipation Pd max IOML(1) IOPL(1) IOMH(1) IOPH(1) VI(1) VIO(1) VLCD Symbol VDD max Pin/Remarks VDD1, VDD2, VDD3 V1/PL4, V2/PL5, V3/PL6 Port L XT1, CF1, RES Port 0, 1, 3, 7 Port A, B, C XT2 Ports 0, 1 Ports A, B, C Port 3 Port 71 to 73 Ports 0, 1 Ports A, B, C Port 3 Ports 71 to 73 Ports 71 to 73 Port 1 Ports 1, 71 to 73 Port 3 Port 0 Ports 0, 3 Ports A, B Port C Ports A, B, C Ports 0, 1 Ports A, B, C Port 3 Ports 7, XT2 Ports 0, 1 Ports A, B, C Port 3 Ports 7, XT2 Ports 7, XT2 Ports 1 Ports 1, 7, XT2 Port 3 Port 0 Ports 0, 3 Ports A, B Port C Ports A, B, C QIP64E(14×14) TQFP64J(10×10) Operating ambient temperature Storage ambient temperature Tstg Topr Current at each pin Current at each pin Total of all pins Total of all pins Total of all pins Total of all pins Total of all pins Total of all pins Total of all pins Total of all pins Total of all pins Ta=-40 to +85°C Ta=-40 to +85°C -40 -55 +85 °C +125 Current at each pin Current at each pin Current at each pin • CMOS output selected • Current at each pin • CMOS output selected • Current at each pin Current at each pin • CMOS output selected • Current at each pin • CMOS output selected • Current at each pin Current at each pin Total of all pins Total of all pins Total of all pins Total of all pins Total of all pins Total of all pins Total of all pins Total of all pins Total of all pins Current at each pin -10 -20 -5 -7.5 -15 -3 -5 -20 -20 -25 -20 -40 -25 -20 -10 20 30 10 15 20 7.5 15 40 50 45 40 80 45 40 80 298 mW mA -0.3 VDD+0.3 Conditions VDD[V] VDD1=VDD2=VDD3 VDD1=VDD2=VDD3 min -0.3 -0.3 -0.3 Specification typ max +6.5 VDD VDD+0.3 V unit Note 1-1: The mean output current is a mean value measured over 100ms. No.A0886-13/29 LC87F7J32A Allowable Operating Condtions at Ta = -40°C to +85°C, VSS1 = VSS2 = VSS3 = 0V Parameter Operating supply voltage (Note 2-1) Memory sustaining supply voltage High level input voltage VIH(2) VIH(1) • Ports 0, 3 • Ports A, B, C • Port L • Port 1 • Ports 71 to 73 • Port 70 port input/ interrupt side VIH(3) VIH(4) VIH(5) Low level input voltage VIL(1) Port 71 interrupt side Port 70 watchdog timer side XT1, XT2, CF1, RES • Ports 0, 3 • Ports A, B, C • Port L VIL(2) • Port 1 • Ports 71 to 73 • Port 70 port input/interrupt side VIL(3) VIL(4) VIL(5) Instruction cycle time (Note 2-2) External system clock frequency FEXCF(1) CF1 • CF2 pin open • System clock frequency division ratio=1/1 • External system clock DUTY=50±5% • CF2 pin open • System clock frequency division ratio=1/2 2.2 to 5.5 3.0 to 5.5 2.5 to 5.5 2.2 to 5.5 0.1 0.2 0.2 0.2 4 24.4 16 8 MHz 2.5 to 5.5 0.1 8 tCYC Port 71 interrupt side Port 70 watchdog timer side XT1, XT2, CF1, RES • Output disabled • When INT1VTSL=1 • Output disabled • When INT1VTSL=0 (P71 only) Output disabled • Output disabled • When INT1VTSL=1 Output disabled 2.2 to 5.5 2.2 to 5.5 2.2 to 5.5 4.0 to 5.5 2.2 to 4.0 4.0 to 5.5 2.2 to 4.0 2.2 to 5.5 2.2 to 5.5 2.2 to 5.5 3.0 to 5.5 2.5 to 5.5 2.2 to 5.5 3.0 to 5.5 0.85VDD 0.9VDD 0.75VDD VSS VSS VSS VSS VSS VSS VSS 0.237 0.356 0.712 0.1 VDD VDD VDD 0.15VDD +0.4 0.2VDD 0.1VDD +0.4 0.2VDD 0.45VDD 0.8VDD -1.0 0.25VDD 200 200 200 12 μs V • Output disabled • When INT1VTSL=0 (P71only) 2.2 to 5.5 0.3VDD +0.7 VDD Output disabled 2.2 to 5.5 0.3VDD +0.7 VDD VHD VDD1=VDD2=VDD3 Symbol VDD(1) Pin/Remarks VDD1=VDD2=VDD3 Conditions VDD[V] 0-237μs≤tCYC≤200μs 0-356μs≤tCYC≤200μs 0-712μs≤tCYC≤200μs RAM and register contents sustained in HOLD mode 2.0 5.5 min 3.0 2.5 2.2 Specification typ max 5.5 5.5 5.5 unit Note 2-1: VDD must be held greater than or equal to 3.0V in the flash ROM onboard programming mode. Note 2-2: Relationship between tCYC and oscillation frequency is 3/FmCF at a division ratio of 1/1 and 6/FmCF at a division ratio of 1/2. Continued on next page. No.A0886-14/29 LC87F7J32A Continued from preceding page. Parameter Oscillation frequency range (Note 2-3) FmCF(3) FmRC FmVMRC(1) CF1, CF2 FmCF(2) CF1, CF2 Symbol FmCF(1) Pin/Remarks CF1, CF2 Conditions VDD[V] • 12MHz ceramic oscillation • See figure 1. • 8MHz ceramic oscillation • See figure 1. • 4MHz ceramic oscillation • See figure 1. Internal RC oscillation • Frequency variable RC source oscillation • When VMRAJ2 to 0=4, VMFAJ2 to 0=0, VMSL4M=0 FmVMRC(2) • Frequency variable RC source oscillation • When VMRAJ2 to 0=4, VMFAJ2 to 0=0, VMSL4M=1 FsX’tal Frequency variable RC oscillation usable range Frequency variable RC oscillation adjustment range VmADJ(2) VmADJ(1) Each step of VMRAJn (Wide range) Each step of VMFAJn (Small range) 2.2 to 5.5 1 4 8 2.2 to 5.5 8 24 64 % OpVMRC(1) OpVMRC(2) XT1, XT2 • 32.768kHz crystal oscillation • See figure 2. When VMSL4M=0 When VMSL4M=1 2.2 to 5.5 3.5 4 4.5 2.2 to 5.5 2.2 to 5.5 8 32.768 10 12 MHz kHz 2.2 to 5.5 4 MHz 2.2 to 5.5 10 3.0 to 5.5 2.5 to 5.5 2.2 to 5.5 2.2 to 5.5 0.3 min Specification typ 12 8 4 1.0 2.0 max unit Note 2-3: See Tables 1 and 2 for the oscillation constants. Electrical Characteristics at Ta = -40°C to +85°C, VSS1 = VSS2 = VSS3 = 0V Parameter High level input current Symbol IIH(1) Pin/Remarks • Ports 0, 1, 3, 7 • Ports A, B, C • Port L Conditions VDD[V] • Output disabled • Pull-up resistor off • VIN=VDD (including output Tr's off leakage current) IIH(2) IIH(3) IIH(4) Low level input current IIL(1) RES XT1, XT2 VIN=VDD • For input port specification • VIN=VDD CF1 • Ports 0, 1, 3, 7 • Ports A, B, C • Port L VIN=VDD • Output disabled • Pull-up resistor off • VIN=VSS (including output Tr's off leakage current) IIL(2) IIL(3) IIL(4) RES XT1, XT2 VIN=VSS • For input port specification • VIN=VSS CF1 VIN=VSS 2.2 to 5.5 2.2 to 5.5 -1 -15 2.2 to 5.5 -1 2.2 to 5.5 -1 2.2 to 5.5 2.2 to 5.5 2.2 to 5.5 1 1 15 2.2 to 5.5 1 min Specification typ max unit μA Continued on next page. No.A0886-15/29 LC87F7J32A Continued from preceding page. Parameter High level output voltage Symbol VOH(1) VOH(2) VOH(3) VOH(4) VOH(5) VOH(6) VOH(7) VOH(8) VOH(9) VOH(10) VOH(11) Low level output voltage VOL(1) VOL(2) VOL(3) VOL(4) VOL(5) VOL(6) VOL(7) VOL(8) VOL(9) VOL(10) LCD output voltage deviation VODLS S0 to S23 Ports 0, 1 Ports 3 (PWM function output mode) Ports 3 (Port function output mode) • Port 7 • XT2 Ports A, B, C Ports A, B, C Ports 71 to 73 Ports 30, 31 Pin/Remarks Ports 0, 1 IOH=-1mA IOH=-0.4mA IOH=-0.2mA IOH=-10mA IOH=-1.6mA IOH=-1mA IOH=-0.4mA IOH=-0.2mA IOH=-1mA IOH=-0.4mA IOH=-0.2mA IOL=10mA IOL=1.6mA IOL=1mA IOL=30mA IOL=5mA IOL=2.5mA IOL=1.6mA IOL=1mA IOH=1.6mA IOL=1mA • IO=0mA • VLCD, 2/3VLCD, 1/3VLCD level output • See Fig. 8. VODLC COM0 to COM3 • IO=0mA • VLCD, 2/3VLCD, 1/2VLCD, 1/3VLCD level output • See Fig. 8. LCD bias resistor RLCD(1) RLCD(2) Resistance per one bias resister Resistance per one bias resister 1/2R mode Resistance of pull-up MOS Tr. Hysteresis voltage Pin capacitance Rpu(1) Rpu(2) VHYS(1) CP Ports 0, 1, 3, 7 Ports A, B, C Ports 1, 7 RES All pins For pins other than that under test: VIN=VSS f=1MHz Ta=25°C 2.2 to 5.5 10 pF VOH=0-9VDD 4.5 to 5.5 2.2 to 5.5 2.2 to 5.5 15 18 35 50 0.1VDD 80 150 V See Fig. 8. 2.2 to 5.5 40 kΩ See Fig. 8. 2.2 to 5.5 80 Conditions VDD[V] 4.5 to 5.5 3.0 to 5.5 2.2 to 5.5 4.5 to 5.5 3.0 to 5.5 2.2 to 5-5 3.0 to 5.5 2.2 to 5.5 4.5 to 5.5 3.0 to 5.5 2.2 to 5.5 4.5 to 5.5 3.0 to 5.5 2.2 to 5.5 4.5 to 5.5 3.0 to 5.5 2.2 to 5.5 3.0 to 5.5 2.2 to 5.5 3.0 to 5.5 2.2 to 5.5 min VDD-1 VDD-0.4 VDD-0.4 VDD-1.5 VDD-0.4 VDD-0.4 VDD-0.4 VDD-0.4 VDD-1 VDD-0.4 VDD-0.4 1.5 0.4 0.4 1.5 0.4 0.4 0.4 0.4 0.4 0.4 V Specification typ max unit 2.2 to 5.5 0 ±0.2 2.2 to 5.5 0 ±0.2 No.A0886-16/29 LC87F7J32A Serial I/O Characteristics at Ta = -40°C to +85°C, VSS1 = VSS2 = VSS3 = 0V 1. SIO0 Serial I/O Characteristics (Note 4-1-1) Parameter Frequency Low level Input clock pulse width High level pulse width tSCKHA(1) • Continuous data transmission/reception mode Serial clock • See Fig. 6. • (Note 4-1-2) Frequency Low level Output clock pulse width High level pulse width tSCKHA(2) • Continuous data transmission/reception mode • CMOS output selected • See Fig. 6. Data setup time Serial input tsDI(1) SB0(P11), SI0(P11) Data hold time thDI(1) • Must be specified with respect to rising edge of SIOCLK • See Fig. 6. 2.2 to 5.5 Output Input clock delay time tdDO(2) tdDO(1) SO0(P10), SB0(P11) • Continuous data transmission/reception mode • (Note 4-1-3) • Synchronous 8-bit mode • (Note 4-1-3) tdDO(3) (Note 4-1-3) 2.2 to 5.5 (1/3)tCYC +0.15 2.2 to 5.5 2.2 to 5.5 0.03 2.2 to 5.5 0.03 tSCKH(2) +2tCYC tSCKH(2) 2.2 to 5.5 tSCK(2) tSCKL(2) SCK0(P12) • CMOS output selected • See Fig. 6. 4/3 1/2 tSCK 1/2 tSCKH(2) +(10/3) tCYC tCYC 4 tSCKH(1) 2.2 to 5.5 Symbol tSCK(1) tSCKL(1) Pin/Remarks SCK0(P12) See Fig. 6. Conditions VDD[V] min 2 1 1 tCYC Specification typ max unit (1/3)tCYC +0.05 1tCYC +0.05 μs Serial output Note 4-1-1: These specifications are theoretical values. Add margin depending on its use. Note 4-1-2: To use serial-clock-input in continuous trans/rec mode, a time from SI0RUN being set when serial clock is "H" to the first negative edge of the serial clock must be longer than tSCKHA. Note 4-1-3: Must be specified with respect to falling edge of SIOCLK. Must be specified as the time to the beginning of output state change in open drain output mode. See Fig. 6. Output clock No.A0886-17/29 LC87F7J32A 2. SIO1 Serial I/O Characteristics (Note 4-2-1) Parameter Frequency Input clock Low level pulse width High level pulse width Frequency Output clock Low level pulse width High level pulse width Serial input Data setup time tsDI(2) SB1(P14), SI1(P14) Data hold time Output delay Serial output time thDI(2) tdDO(4) SO1(P13), SB1(P14) • Must be specified with respect to rising edge of SIOCLK. • See Fig. 6. 2.2 to 5.5 • Must be specified with respect to falling edge of SIOCLK. • Must be specified as the time to the beginning of output state change in open drain output mode. • See Fig. 6. 2.2 to 5.5 (1/3)tCYC +0.05 μs 0.03 2.2 to 5.5 0.03 tSCKH(4) tSCK(4) tSCKL(4) SCK1(P15) • CMOS output selected • See Fig. 6. 2.2 to 5.5 tSCKH(3) Symbol tSCK(3) tSCKL(3) Pin/Remarks SCK1(P15) See Fig.6. Conditions VDD[V] min 2 2.2 to 5.5 1 tCYC 1 2 1/2 tSCK 1/2 Specification typ max unit Note 4-2-1: These specifications are theoretical values. Add margin depending on its use. Pulse Input Conditions at Ta = -40°C to +85°C, VSS1 = VSS2 = VSS3 = 0V Parameter High/low level pulse width Symbol tPIH(1) tPIL(1) Pin/Remarks INT0(P70), INT1(P71), INT2(P72) INT4(P30), INT5(P31) tPIH(2) tPIL(2) tPIH(3) tPIL(3) tPIH(4) tPIL(4) tPIH(5) tPIL(5) tPIL(6) RES INT3(P73) when noise filter time constant is 1/1 INT3(P73) when noise filter time constant is 1/32 INT3(P73) when noise filter time constant is 1/128 RMIN(P73) • Interrupt source flag can be set. • Event inputs for timer 0 are enabled. • Interrupt source flag can be set. • Event inputs for timer 0 are enabled. • Interrupt source flag can be set. • Event inputs for timer 0 are enabled. Recognized by the infrared remote controller receiver circuit as a signal. Resetting is enabled. 2.2 to 5.5 200 2.2 to 5.5 4 RMCK (Note5-1) μs 2.2 to 5.5 256 2.2 to 5.5 64 2.2 to 5.5 2 tCYC Conditions VDD[V] • Interrupt source flag can be set. • Event inputs for timer 0 or 1 are enabled. 2.2 to 5.5 1 min Specification typ max unit Note 5-1: Represents the period of the reference clock (1tCYC to 128tCYC or the source frequency of the subclock) for the infrared remote controller receiver circuit Serial clock No.A0886-18/29 LC87F7J32A AD Converter Characteristics at VSS1 = VSS2 = VSS3 =0V Parameter Resolution Absolute accuracy Conversion time Analog input voltage range Analog port input current IAINH IAINL VAIN TCAD N ET Symbol Pin/Remarks AN0(V1) to AN2(V3), AN3(P00) to AN7(P04), AN8(P70), AN9(P71), AN10(XT1), AN11(XT2) VAIN=VDD VAIN=VSS 3.0 to 5.5 3.0 to 5.5 3.0 to 5.5 -1 VSS VDD 1 V μA • See Conversion time calculation formulas. (Note 6-2) 3.0 to 5.5 64 115 (Note 6-1) Conditions VDD[V] 3.0 to 5.5 3.0 to 5.5 4.0 to 5.5 32 min Specification typ 12 ±16 115 max unit bit LSB μs Parameter Resolution Absolute accuracy Conversion time Analog input voltage range Analog port input current IAINH IAINL VAIN TCAD N ET Symbol Pin/Remarks AN0(V1) to AN2(V3), AN3(P00) to AN7(P04), AN8(P70), AN9(P71), AN10(XT1), AN11(XT2) VAIN=VDD VAIN=VSS 3.0 to 5.5 3.0 to 5.5 3.0 to 5.5 -1 VSS VDD 1 V μA • See Conversion time calculation formulas. (Note 6-2) 3.0 to 5.5 40 90 (Note 6-1) Conditions VDD[V] 3.0 to 5.5 3.0 to 5.5 4.0 to 5.5 20 min Specification typ 8 ±1.5 90 μs max unit bit LSB Conversion time calculation formulas: 12bits AD Converter Mode: TCAD(Conversion time)=((52/(division ratio)) + 2) × (1/3) ×tCYC 8bits AD Converter Mode: TCAD(Conversion time)=((32/(division ratio)) + 2) × (1/3) ×tCYC External oscillation (FmCF) CF-12MHz Operating supply voltage range (VDD) 4.0V to 5.5V 3.0V to 5.5V CF-8MHz CF-4MHz 4.0V to 5.5V 3.0V to 5.5V 3.0V to 5.5V System division ratio (SYSDIV) 1/1 1/1 1/1 1/1 1/1 Cycle time (tCYC) 250ns 250ns 375ns 375ns 750ns AD division ratio (ADDIV) 1/8 1/16 1/8 1/16 1/8 12bit AD 34.8μs 69.5μs 52.2μs 104.3μs 104.5μs AD conversion time (TCAD) 8bit AD 21.5μs 42.8μs 32.3μs 64.2μs 64.5μs Note 6-1: The quantization error (±1/2LSB) must be excluded from the absolute accuracy. The absolute accuracy must be measured in the microcontroller's state in which no I/O operations occur at the pins adjacent to the analog input channel. Note 6-2: The conversion time refers to the period from the time an instruction for starting a conversion process till the time the conversion results register(s) are loaded with a complete digital conversion value corresponding to the analog input value. The conversion time is 2 times the normal-time conversion time when: • The first AD conversion is performed in the 12-bit AD conversion mode after a system reset. • The first AD conversion is performed after the AD conversion mode is switched from 8-bit to 12-bit conversion mode. No.A0886-19/29 LC87F7J32A Power-on reset (POR) Characteristics at Ta=-40 to +85°C, VSS1=VSS2=VSS3=0V Specification Parameter POR release voltage Symbol PORR Pin/Remarks Conditions • Select from option. (Note 7-1) Option selected voltage 2.07V 2.37V 2.87V 4.35V Detection voltage unknown state Power supply rise time PORIS POUKS • See Fig. 7. (Note 7-2) • Power supply rise time from 0V to 2.0V. min 1.95 2.25 2.75 4.21 typ 2.07 2.37 2.87 4.35 0.7 max 2.19 2.49 2.99 4.49 0.95 100 ms V unit Note7-1: The POR release level can be selected out of 4 levels only when the LVD reset function is disabled. Note7-2: POR is in an unknown state before transistors start operation. Low voltage detection reset (LVD) Characteristics at Ta=-40 to +85°C, VSS1=VSS2=VSS3=0V Specification Parameter LVD reset voltage (Note 8-2) Symbol LVDET Pin/Remarks Conditions • Select from option. (Note 8-1) (Note 8-3) • See Fig. 8. LVD hysteresys width LVHYS Option selected voltage 2.31V 2.81V 4.28V 2.31V 2.81V 4.28V Detection voltage unknown state Low voltage dtection minimum width (Reply sensitivity) TLVDW LVUKS • See Fig. 8. (Note 8-4) • See Fig. 9. 0.2 ms 0.7 0.95 V min. 2.21 2.71 4.18 typ. 2.31 2.81 4.28 55 60 65 mV max. 2.41 2.91 4.38 V unit Note8-1: The LVD reset level can be selected out of 3 levels only when the LVD reset function is enabled. Note8-2: LVD reset voltage specification values do not include hysteresis voltage. Note8-3: LVD reset voltage may exceed its specification values when port output state changes and/or when a large current flows through port. Note8-4: LVD is in an unknown state before transistors start operation. No.A0886-20/29 LC87F7J32A Consumption Current Characteristics at Ta = -40°C to +85°C, VSS1 = VSS2 = VSS3 = 0V Parameter Normal mode consumption current (Note 9-1) IDDOP(2) Symbol IDDOP(1) Pin/ Remarks VDD1 =VDD2 =VDD3 Conditions VDD[V] • FmCF=12MHz ceramic oscillation mode • FmX’tal=32.768kHz crystal oscillation mode • System clock set to 12MHz side • Internal RC oscillation stopped. • Frequency variable RC oscillation stopped. • 1/1 frequency division ratio IDDOP(3) IDDOP(4) IDDOP(5) IDDOP(6) IDDOP(7) IDDOP(8) IDDOP(9) IDDOP(10) IDDOP(11) IDDOP(12) • FmCF=8MHz ceramic oscillation mode • FmX’tal=32.768kHz crystal oscillation mode • System clock set to 8MHz side • Internal RC oscillation stopped. • Frequency variable RC oscillation stopped. • 1/1 frequency division ratio • FmCF=4MHz ceramic oscillation mode • FmX’tal=32.768kHz crystal oscillation mode • System clock set to 4MHz side • Internal RC oscillation stopped. • Frequency variable RC oscillation stopped. • 1/2 frequency division ratio • FmCF=0Hz (oscillation stopped) • FmX’tal=32.768kHz crystal oscillation mode • System clock set to internal RC oscillation • Frequency variable RC oscillation stopped. • 1/2 frequency division ratio • FmCF=0Hz (oscillation stopped) • FmX’tal=32.768kHz crystal oscillation mode • Internal RC oscillation stopped. IDDOP(13) • System clock set to 10MHz wifh frequency variable RC oscillation • 1/1 frequency division ratio IDDOP(14) IDDOP(15) • FmCF=0Hz (oscillation stopped) • FmX’tal=32.768kHz crystal oscillation mode • Internal RC oscillation stopped. • System clock set to 4MHz wifh frequency IDDOP(16) IDDOP(17) IDDOP(18) IDDOP(19) HALT mode consumption current (Note 9-1) IDDHALT(2) IDDHALT(1) variable RC oscillation • 1/1 frequency division ratio • FmCF=0Hz (oscillation stopped) • FmX’tal=32.768kHz crystal oscillation mode • System clock set to 32.768kHz side • Internal RC oscillation stopped. • Frequency variable RC oscillation stopped. • 1/2 frequency division ratio • HALT mode • FmCF=12MHz ceramic oscillation mode • FmX’tal=32.768kHz crystal oscillation mode • System clock set to 12MHz side • Internal RC oscillation stopped. • Frequency variable RC oscillation stopped. • 1/1 frequency division ratio IDDHALT(3) • HALT mode • FmCF=8MHz ceramic oscillation mode IDDHALT(4) • FmX’tal=32.768kHz crystal oscillation mode • System clock set to 8MHz side • Internal RC oscillation stopped. IDDHALT(5) • Frequency variable RC oscillation stopped. • 1/1 frequency division ratio 2.5 to 3.0 1.1 3.1 3.0 to 3.6 1.4 3.9 4.5 to 5.5 2.8 7.7 3.0 to 3.6 2.0 5.0 mA 4.5 to 5.5 3.8 9.2 2.2 to 3.0 13 53 2.2 to 3.0 4.5 to 5.5 3.0 to 3.6 1.8 35 18 5.5 120 72 μA 3.0 to 3.6 2.8 7.7 4.5 to 5.5 3.6 10 3.0 to 3.6 4.5 12 4.5 to 5.5 7.8 21 2.2 to 3.0 0.3 1.5 3.0 to 3.6 0.4 1.9 2.2 to 3.0 4.5 to 5.5 1.1 0.7 3.2 3.3 mA 3.0 to 3.6 1.3 3.5 2.5 to 3.0 4.5 to 5.5 3.1 2.4 8.8 6.6 3.0 to 3.6 3.9 11 4.5 to 5.5 6.9 19 3.0 to 3.6 4.8 13 4.5 to 5.5 8.5 23 min Specification typ max unit Note 9-1: The consumption current value includes none of the currents that flow into the output Tr and internal pull-up resistors. Continued on next page. No.A0886-21/29 LC87F7J32A Continued from preceding page. Parameter HALT mode consumption current (Note 9-1) IDDHALT(7) Symbol IDDHALT(6) Pin/ Remarks VDD1 =VDD2 =VDD3 • HALT mode • FmCF=4MHz ceramic oscillation mode • FmX’tal=32.768kHz crystal oscillation mode • System clock set to 4MHz side • Internal RC oscillation stopped. IDDHALT(8) • Frequency variable RC oscillation stopped. • 1/2 frequency division ratio IDDHALT(9) IDDHALT(10) IDDHALT(11) IDDHALT(12) • HALT mode • FmCF=0Hz (oscillation stopped) • FmX’tal=32.768kHz crystal oscillation mode • System clock set to internal RC oscillation • Frequency variable RC oscillation stopped. • 1/2 frequency division ratio • HALT mode • FmCF=0Hz (oscillation stopped) • FmX’tal=32.768kHz crystal oscillation mode IDDHALT(13) • Internal RC oscillation stopped. • System clock set to 10MHz wifh frequency variable RC oscillation • 1/1 frequency division ratio IDDHALT(14) • HALT mode • FmCF=0Hz (oscillation stopped) IDDHALT(15) • FmX’tal=32.768kHz crystal oscillation mode • Internal RC oscillation stopped. • System clock set to 4MHz wifh frequency IDDHALT(16) variable RC oscillation • 1/1 frequency division ratio IDDHALT(17) • HALT mode • FmCF=0Hz (oscillation stopped) IDDHALT(18) • FmX’tal=32.768kHz crystal oscillation mode • System clock set to 32.768kHz side • Internal RC oscillation stopped. IDDHALT(19) • Frequency variable RC oscillation stopped. • 1/2 frequency division ratio HOLD mode consumption current IDDHOLD(1) IDDHOLD(2) IDDHOLD(3) IDDHOLD(4) IDDHOLD(5) IDDHOLD(6) Timer HOLD mode consumption current IDDHOLD(7) IDDHOLD(8) IDDHOLD(9) VDD1 VDD1 • HOLD mode • CF1=VDD or open (External clock mode) • HOLD mode • CF1=VDD or open (External clock mode) • LVD option selected • Timer HOLD mode • CF1=VDD or open (External clock mode) • FmX’tal=32.768kHz crystal oscillation mode 2.2 to 3.0 4.5 17 2.2 to 3.0 4.5 to 5.5 3.0 to 3.6 2.0 19 7.0 10 65 31 4.5 to 5.5 3.0 to 3.6 2.2 to 3.0 4.5 to 5.5 3.0 to 3.6 0.05 0.03 0.02 3.5 2.2 22 13 9 25 15 μA 2.2 to 3.0 6 26 3.0 to 3.6 9 33 μA 4.5 to 5.5 22 82 2.2 to 3.0 0.6 1.7 3.0 to 3.6 0.8 2.2 4.5 to 5.5 1.7 4.6 3.0 to 3.6 1.6 4.4 4.5 to 5.5 3.3 9.0 2.2 to 3.0 4.5 to 5.5 3.0 to 3.6 2.2 to 3.0 0.4 0.40 0.20 0.15 1.2 1.89 0.83 0.69 mA 3.0 to 3.6 0.6 1.7 4.5 to 5.5 1.2 3.3 Conditions VDD[V] min Specification typ max unit Note 9-1: The consumption current value includes none of the currents that flow into the output Tr and internal pull-up resistors. F-ROM Programming Characteristics at Ta = +10°C to +55°C, VSS1 = VSS2 = VSS3 = 0V Parameter Onboard programming current Programming time tFW(1) • Erasing time 3.0 to 5.5 • Programming time 20 40 30 60 ms μs Symbol IDDFW(1) Pin/Remarks VDD1 Conditions VDD[V] • 128-byte programming • Erasing current included 3.0 to 5.5 5 10 mA min Specification typ max unit No.A0886-22/29 LC87F7J32A UART (Full Duplex) Operating Conditions at Ta = -40 to +85°C, VSS1 = VSS2 = VSS3 = 0V Parameter Transfer ate Symbol UBR Pin/Remarks UTX(S0), URX(S1) Conditions VDD[V] 2.2 to 5.5 min 16/3 Specification typ max 8192/3 unit tCYC Data length: 7/8/9 bits (LSB first) Stop bits: 1 bit (2-bit in continuous data transmission) Parity bits: None Example of 8-bit Data Transmission Mode Processing (Transmit Data=55H) Start bit Start of transmission Transmit data (LSB first) Stop bit End of transmission UBR Example of 8-bit Data Reception Mode Processing (Receive Data=55H) Stop bit Receive data (LSB first) End of reception Start bit Start of reception UBR Characteristics of a Sample Main System Clock Oscillation Circuit Given below are the characteristics of a sample main system clock oscillation circuit that are measured using a SANYO-designated oscillation characteristics evaluation board and external components with circuit constant values with which the oscillator vendor confirmed normal and stable oscillation. Table 1 Characteristics of a Sample Main System Clock Oscillator Circuit with a Ceramic Oscillator Nominal Frequency Vendor Name Circuit Constant Oscillator Name C1 [pF] 12MHz MURATA CSTCE12M0G52-R0 CSTCE8M00G52-R0 CSTLS8M00G53-B0 4MHz MURATA CSTCR4M00G53-R0 CSTLS4M00G53-B0 (10) (10) (15) (15) (15) C2 [pF] (10) (10) (15) (15) (15) Rf1 [Ω] Open Open Open Open Open Rd1 [Ω] 470 2.2k 680 3.3k 3.3k Operating Voltage Range [V] 3.0 to 5.5 2.7 to 5.5 2.5 to 5.5 2.2 to 5.5 2.2 to 5.5 Oscillation Stabilization Time typ [ms] 0.05 0.05 0.05 0.05 0.05 max [ms] 0.15 0.15 0.15 0.15 0.15 Internal C1, C2 Internal C1, C2 Internal C1, C2 Remarks 8MHz MURATA The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized after VDD goes above the operating voltage lower limit (see Figure 4). No.A0886-23/29 LC87F7J32A Characteristics of a Sample Subsystem Clock Oscillator Circuit Given below are the characteristics of a sample subsystem clock oscillation circuit that are measured using a SANYOdesignated oscillation characteristics evaluation board and external components with circuit constant values with which the oscillator vendor confirmed normal and stable oscillation. Table 2 Characteristics of a Sample Subsystem Clock Oscillator Circuit with a Crystal Oscillator Nominal Frequency Vendor Name Oscillator Name C3 [pF] 32.768kHz EPSON TOYOKOMU MC-306 18 Circuit Constant C4 [pF] 18 Rf2 [Ω] Open Rd2 [Ω] 560 Operating Voltage Range [V] Oscillation Stabilization Time typ [s] 1.4 max [s] Applicable 2.2 to 5.5 3.0 CL value= 12.5pF Remarks The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized after the instruction for starting the subclock oscillation circuit is executed and to the time interval that is required for the oscillation to get stabilized after the HOLD mode is reset (see Figure 4). Note: The components that are involved in oscillation should be placed as close to the IC and to one another as possible because they are vulnerable to the influences of the circuit pattern. CF1 CF2 XT1 XT2 Rf1 Rd1 Rf2 Rd2 C1 CF C2 C3 X’tal C4 Figure 1 CF Oscillator Circuit Figure 2 XT Oscillator Circuit 0.5VDD Figure 3 AC Timing Measurement Point No.A0886-24/29 LC87F7J32A Power supply VDD Operating VDD lower limit 0V Reset time RES Internal RC oscillation tmsCF CF1, CF2 tmsX’tal XT1, XT2 Operating mode Unpredictable Reset Instruction execution Reset Time and Oscillation Stabilization Time HOLD reset signal HOLD reset signal absent HOLD release signal VALID Internal RC oscillation tmsCF CF1, CF2 tmsX’tal XT1, XT2 State HOLD HALT HOLD Reset Signal and Oscillation Stabilization Time Figure 4 Oscillation Stabilization Times No.A0886-25/29 LC87F7J32A VDD RRES RES CRES Note: External circuits for reset may vary depending on the usage of POR and LVD. Please refer to the user’s manual for more information. Figure 5 Reset Circuit SIOCLK: DATAIN: DI0 DI1 DI2 DI3 DI4 DI5 DI6 DI7 DI8 DATAOUT: DO0 DO1 DO2 DO3 DO4 DO5 DO6 DO7 Data RAM transfer period (SIO0 only) DO8 tSCK tSCKL SIOCLK: tsDI DATAIN: tdDO DATAOUT: Data RAM transfer period (SIO0 only) tSCKL SIOCLK: tsDI DATAIN: tdDO DATAOUT: thDI tSCKHA thDI tSCKH Figure 6 Serial I/O Waveforms tPIL tPIH Figure 7 Pulse Input Timing Signal Waveform No.A0886-26/29 LC87F7J32A VDD SW : ON/OFF (programmable) RLCD RLCD RLCD RLCD VLCD RLCD RLCD 2/3VLCD RLCD 1/2VLCD RLCD 1/3VLCD RLCD RLCD GND SW: ON (VLCD=VDD) Figure 8 LCD Bias Resistors (a) (b) POR release voltage (PORRL) VDD Reset period Unknown-state (POUKS) 100μs or longer Reset period RES Figure 9 Waveform observed when only POR is used (LVD not used) (RESET pin: Pull-up resistor RRES only) • The POR function generates a reset only when power is turned on starting at the VSS level. • No stable reset will be generated if power is turned on again when the power level does not go down to the VSS level as shown in (a). If such a case is anticipated, use the LVD function together with the POR function or implement an external reset circuit. • A reset is generated only when the power level goes down to the VSS level as shown in (b) and power is turned on again after this condition continues for 100μs or longer. No.A0886-27/29 LC87F7J32A LVD hysteresis width (LVHYS) LVD release voltage (LVDET+LVHYS) VDD Reset period Unknown-state (LVUKS) Reset period Reset period LVD reset voltage (LVDET) RES Figure 10 Waveform observed when both POR and LVD functions are used (RESET pin: Pull-up resistor RRES only) • Resets are generated both when power is turned on and when the power level lowers. • A hysteresis width (LVHYS) is provided to prevent the repetitions of reset release and entry cycles near the detection level. VDD LVD release voltage LVD reset voltage TLVDW VSS LVDET-0.5V Figure 11 Low voltage detection minimum width (Example of momentary power loss/Voltage variation waveform) No.A0886-28/29 LC87F7J32A Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment (home appliances, AV equipment, communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee thereof. If you should intend to use our products for applications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our customer shall be solely responsible for the use. Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer' s products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer' s products or equipment. SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein. SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO Semiconductor Co.,Ltd. products described or contained herein are controlled under any of applicable local export control laws and regulations, such products may require the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written consent of SANYO Semiconductor Co.,Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO Semiconductor Co.,Ltd. product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. Upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third party. SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's intellctual property rights which has resulted from the use of the technical information and products mentioned above. This catalog provides information as of May, 2007. Specifications and information herein are subject to change without notice. PS No.A0886-29/29