LC88F40D0PA

Ordering number : ENA1853A LC88F40H0PA/PAU LC88F40F0PA/PAU LC88F40D0PA/PAU Overview CMOS LSI For Car Audio Systems 16-bit ETR Microcontroller (ALL FLASH) The LC88F40H0PA/PAU, LC88F40F0PA/PAU and LC88F40D0PA/PAU are 16-bit microcontrollers which are ideally suited as a system controller in car audio applications for the control of “MP3 and WMA and other compression decoders through CD/USB,” “CD mechanisms and CD DSPs,” “displays,” and “DSP tuners.” They are configured around a CPU that operates at a high speed, and incorporate an internal flash ROM (All Flash, onboard programmable) and RAM. These 16-bit microcontrollers integrate on a single chip such principal functions as on-chip debugging, 16-bit timer/counter (may be divided into 8-bit timers/counters), synchronous SIO (also used as the I2C bus interface), UART (full duplex), 12-bit PWM, 12-bit resolution (8-bit resolution selectable) × 13-channel A/D converter, and 16 vector interrupts. Microcontroller model line-up (list of ROM and RAM sizes) Type No. LC88F40H0PA/PAU LC88F40F0PA/PAU LC88F40D0PA/PAU Flash ROM (byte) 512K 384K 256K RAM (byte) 30K 20K 12K Features ■Power supply voltage • Main power supply voltage (VDDCPU) • I/O power supply (VDDPORT) 3.3V±0.3V VDDCPU to 5.5V * This product is licensed from Silicon Storage Technology, Inc. (USA), and manufactured and sold by SANYO Semiconductor Co., Ltd. Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment (home appliances, AV equipment, communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee thereof. If you should intend to use our products for applications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our customer shall be solely responsible for the use. Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer' s products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer' s products or equipment. Ver.1.23 D1510HKPC 20101005-S00001, S00002, S00003, S00004, S00005, S00006 No.A1853-1/32 LC88F40H0PA/H0PAU/F0PA/F0PAU/D0PA/D0PAU ■Flash ROM (ALL FLASH) • Single 3.3V power supply, on-board writeable • Block erase in 512 byte units • 83.3ns ■Minimum instruction cycle time (Tcyc) ■Ports • Normal withstand voltage I/O ports Ports whose I/O direction can be designated in 1 bit units : 86 (P0n, P1n, P2n, P3n, P4n, P5n, P6n, P7n PAn, PB0 to PB6, PC0, PD0 to PD5) • Dedicated pin for low-pass filter connection : 1 (LPFO) • Regulator pins : 1 (VREG) • Reset pins : 1 (RESB) • TEST pins : 1 (TEST) • Dedicated pins for crystal oscillator : 2 (XT1, XT2) • Power pins : 2 (VDDCPU, VSS1: Main power, I/O power supply) : 4 (VDDPORT1 to 2, VSS2 to 3: I/O power supply) : 2 (VDDPLL, VSS4: PLLVCO power) ■SIO: 6 channels (4 channels are also used as I2C bus.) • SIO0: 8 bit synchronous SIO 1) LSB first/MSB first mode selectable 2) Built-in 8-bit baudrate generator (4 to 512 transfer clock cycle) 3) Automatic and continuous data transfer function to and from the RAM (max. 4096 bytes) • SIO1: 8 bit synchronous SIO 1) LSB first/MSB first mode selectable 2) Built-in 8-bit baudrate generator (4 to 512 transfer clock cycle) 3) Automatic and continuous data transfer function to and from the RAM (max. 4096 bytes) • SMIIC0: Single master I2C/8-bit synchronous SIO Mode 0: Single-master mode communication Mode 1: Synchronous 8-bit serial I/O (MSB first) • SMIIC1: Single master I2C/8-bit synchronous SIO Mode 0: Single-master mode communication Mode 1: Synchronous 8-bit serial I/O (MSB first) • SMIIC2: Single master I2C/8-bit synchronous SIO Mode 0: Single-master mode communication Mode 1: Synchronous 8-bit serial I/O (MSB first) • SMIIC3: Single master I2C/8-bit synchronous SIO Mode 0: Single-master mode communication Mode 1: Synchronous 8-bit serial I/O (MSB first) ■UART: 4 channels 1) Data length : 8 bits (LSB first) 2) Stop bits : 1 bit 3) Parity bits : None/even parity/odd parity 4) Transfer rate : 8 to 4096 cycle 5) Baudrate source clock : System clock/XT clock/VCO clock 5) Wakeup function 6) Full duplex communication No.A1853-2/32 LC88F40H0PA/H0PAU/F0PA/F0PAU/D0PA/D0PAU ■Timers • Timer 0: 16-bit timer that supports PWM/toggle outputs 1) 5-bit prescaler 2) 8-bit PWM × 2, 8-bit timer + 8-bit PWM mode selectable 3) Clock source selectable from system clock, XT clock, VCO clock, and internal RC oscillator • Timer 1: 16-bit timer with capture registers 1) 5-bit prescaler 2) May be divided into 2 channels of 8-bit timer 3) Clock source selectable from system clock, XT clock, VCO clock, and internal RC oscillator • Timer 2: 16-bit timer with capture registers 1) 4-bit prescaler 2) May be divided into 2 channels of 8-bit timer 3) Clock source selectable from system clock, XT clock, VCO clock, and external events • Timer 3: 16-bit timer that supports PWM/toggle outputs 1) 8-bit prescaler 2) 8-bit PWM × 2ch or 8-bit timer + 8-bit PWM mode selectable 3) Clock source selectable from system clock, XT clock, VCO clock, and external events • Timer 4: 16-bit timer that supports toggle outputs 1) Clock source selectable from system clock and prescaler 0 • Timer 5: 16-bit timer that supports toggle outputs 1) Clock source selectable from system clock and prescaler 0 • Timer 6: 16-bit timer that supports toggle outputs 1) Clock source selectable from system clock and prescaler 1 • Timer 7: 16-bit timer that supports toggle outputs 1) Clock source selectable from system clock and prescaler 1 * Prescaler 0 and 1 are consisted of 4 bits and can choose their clock source from XT clock or VCO clock. • Timer 8 1) Clock source may be selected from XT clock (32.768kHz) and frequency-divided output of clock. 2) Interrupts can be generated in 8 timing schemes. • Watch timer 1) Clock may be selected from XT clock (32.768kHz) 2) Interrupts can be generated in 4 timing schemes. ■Day, minute and second counters 1) Count-up of clocks output from watch timer 2) Configured with day counter, minute counter, second counter 3) Continues operation when in HOLDX mode. ■AD converter 1) 12/8 bits resolution selectable 2) Analog input: 13 channels 3) Comparator mode 4) Automatic reference voltage generation No.A1853-3/32 LC88F40H0PA/H0PAU/F0PA/F0PAU/D0PA/D0PAU ■PWM: Multifrequency 12-bit PWM × 4 channels • PWM0: Multifrequency 12-bit PWM × 2 channels (PWM0A and PWM0B) • PWM1: Multifrequency 12-bit PWM × 2 channels (PWM1A and PWM1B) 1) 2-channel pairs controlled independently of one another 2) Clock source selectable from system clock or VCO clock 3) 8-bit prescaler: TPWMR0 = (prescaler value + 1) × clock period 4) 8-bit fundamental wave PWM generator circuit + 4-bit additional pulse generator circuit 5) Fundamental wave PWM mode Fundamental wave period : 16 TPWMR0 to 256 TPWR0 High pulse width : 0 to (Fundamental wave period - TPWMR0) 6) Fundamental wave + additional pulse mode Fundamental wave period : 16 TPWR0 to 256 TPWR0 Overall period : Fundamental wave period × 16 High pulse width : 0 to (Overall period - TPWR0) ■Watchdog Timer: 1 channel ■Interrupts • Driven by the timer 8 + internal watchdog timer dedicated counter • Interrupt or reset mode selectable • 63 sources, 16 vector addresses 1) Provides three levels of multiplex interrupt control. Any interrupt requests of the level equal to or lower than the current interrupt are not accepted. 2) When interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest level takes precedence over the other interrupts. For interrupts of the same level, the interrupt into the smallest vector address takes precedence. No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Vector Address 08000H 08004H 08008H 0800CH 08010H 08014H 08018H 0801CH 08020H 08024H 08028H 0802CH 08030H 08034H 08038H 0803CH PWM0 (1)/PWM1 (1)/SMIIC2 (1) ADC (1)/timer 5 (1)/SMIIC3 (1) INT6 (1)/timer 6 (1)/UART 3 (3) INT7 (1)/timer 7 (1)/SIO0 (2)/UART 4 (3) Port 0 (3)/Port 5 (8)/UART 5 (3) INT1 (1) INT2 (1)/timer 1 (2)/UART 2 (3) INT3 (1)/timer 2 (3)/SMIIC0 (1) INT4 (1)/timer 3 (2)/SMIIC1 (1)/IR Remote control receive (4) INT5 (1)/timer 4 (1)/SIO1 (2) WDT (1) Timer 8 (2)/Watch timer (1) Timer 0 (2) INT0 (1) Interrupt Source • 3 priority levels selectable. • Of interrupts of the same level, the one with the smallest vector address takes precedence. • A number enclosed in parentheses denotes the number of sources. ■Subroutine Stack: Entire maximum RAM space (The stack is allocated in RAM.) • Subroutine calls that automatically save PSW, interrupt vector calls: 6 bytes • Subroutine calls that do not automatically save PSW: 4 bytes • 16 bits × 16 bits • 16 bits ÷ 16 bits • 32 bits ÷ 16 bits ■High-speed Multiplication/division instructions No.A1853-4/32 LC88F40H0PA/H0PAU/F0PA/F0PAU/D0PA/D0PAU ■Infrared remote controller receive functions 1) Noise rejection function 2) PPM(Pulse Position Modulation), compatible with Manchester and other data encoding systems. 3) HOLDX mode release function ■Oscillation circuits • RC oscillator circuit (internal): For system clock • XT oscillator circuit: For system clock • VCO oscillator circuit (internal): For system clock • HALT mode: Halts instruction execution while allowing the peripheral circuits to continue operation. • HOLD mode: Suspends instruction execution and the operation of the peripheral circuits. • HOLDX mode: Suspends instruction execution and operation of all the peripheral circuits except the modules run on the XT clock. ■Low power consumption ■System clock divider function • Can run on low current. • 1/1 to 1/128 of the system clock frequency can be set. No.A1853-5/32 LC88F40H0PA/H0PAU/F0PA/F0PAU/D0PA/D0PAU ■Standby Function • HALT mode: Halts instruction execution while allowing the peripheral circuits to continue operation. 1) Both the XT oscillator and internal RC oscillator retain the state established when the standby mode is entered. 2) Both the XT and VCO clocks retain the state established when the standby mode is entered. 3) There are the two ways of releasing the HALT mode. (1) Generating a reset condition (2) Generating an interrupt • HOLD mode: Suspends instruction execution and the operation of the peripheral circuits. 1) Both the XT oscillator and internal RC oscillator automatically stop operation. 2) XT clock and VCO clock oscillators automatically stop. 3) There are the six ways of releasing the HOLD mode. (1) Generating a reset condition (2) Setting at least one of the INT0, INT1, INT2, INT4, INT5, INT6, and INT7 pins to the specified level (3) Having an interrupt source established at port 0 (4) Having an interrupt source established at port 5 (5) Having an interrupt request generated in UART2, UART3, UART4, or UART5 (6) Having an interrupt request generated in SIO0 or SIO1 • HOLDX mode: Suspends instruction execution and operation of all the peripheral circuits except the modules run on the XT clock. 1) The internal RC oscillator automatically stops operation. 2) The XT clock retains the state established when the HOLDX mode is entered and the VCO clock automatically stops. 3) There are nine ways of resetting the HOLDX mode. (1) Generating a reset condition (2) Setting at least one of the INT0, INT1, INT2, INT4, INT5, INT6, and INT7 pins to the specified level (3) Having an interrupt source established at port 0 (4) Having an interrupt source established at port 5 (5) Having an interrupt request generated in UART2, UART3, UART4, or UART5 (6) Having an interrupt request generated in SIO0 or SIO1 (7) Having an interrupt source established in the timer 8 circuit (8) Having an interrupt source established in the infrared remote controller receive circuit (9) Having an interrupt source established in the clock timer circuit ■Reset • External reset • Voltage drop detection type of reset circuit (VDET circuit) incorporated 1) Normal mode detection voltage: 2.85V ±0.15V 2) HOLD mode detection voltage: 1.42V ±0.15V • Supports software debugging with the IC mounted on the target board. • Supports source line debugging and tracing functions, and breakpoint setting and real time monitor. • Single-wire communication • QIP100E (Lead free product) ■On-chip debugger function ■Shipping Form No.A1853-6/32 LC88F40H0PA/H0PAU/F0PA/F0PAU/D0PA/D0PAU Package Dimensions unit : mm (typ) 3151A 23.2 80 81 51 50 0.8 14.0 20.0 100 1 0.65 (0.58) (2.7) 31 30 0.3 0.15 3.0max 0.1 SANYO : QIP100E(14X20) 17.2 No.A1853-7/32 LC88F40H0PA/H0PAU/F0PA/F0PAU/D0PA/D0PAU Pin Assignment P07/T0PWMH P06/T0PWML P15/T3OUTH P14/T3OUTL P05/P05INT P04/P04INT VDDPORT2 P03/P0INT P02/P0INT P01/P0INT P00/P0INT P34/U3RX P16/U2RX P12/SCK0 P35/U3TX P17/U2TX P11/SIO0 P33/INT3 P32/INT2 P31/INT1 P30/INT0 P40/INT6 P10/SO0 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 P43/SO1 P37/T7O P36/T6O VSS3 P13 P41 P42 PA0/SM1CK PA1/SM1DA PA2/SM1DO PA3/SM2CK PA4/SM2DA PA5/SM2DO PA6/U5RX PA7/U5TX PB0/PWM10 PB1/PWM11 PB2 PB3 PB4 PB5/INT7 PB6 VDDPLL VSS4 LPFO P50/P5INT0 P51/P5INT1 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 50 49 48 47 46 45 44 43 P44/SIO1 P45/SCK1 P46/PWM00 P47/PWM01 VSS2 VDDPORT1 P27/RMIN P26/T5O P25/T4O P24/SM0DO P23/SM0DA P22/SM0CK P21/INT5 P20/INT4 PD5 PD4 PD3 PD2 PD1/U4TX PD0/U4RX LC88F40H0PA/PAU LC88F40F0PA/PAU LC88F40D0PA/PAU 42 41 40 39 38 37 36 35 34 33 32 31 TEST VDDCPU VREG P77/SM3DO RESB P75/SM3CK P76/SM3DA XT1 VSS1 PC0 XT2 P60/AN0 P61/AN1 P62/AN2 P63/AN3 P64/AN4 P65/AN5 P66/AN6 P67/AN7 P70/AN8 P71/AN9 P72/AN10 P73/AN11 P52/P5INT2 P53/P5INT3 P54/P5INT4 P55/P5INT5 P56/P5INT6 P57/P5INT7 P74/AN12 Top view No.A1853-8/32 LC88F40H0PA/H0PAU/F0PA/F0PAU/D0PA/D0PAU System Block Diagram RC Timer 8 X’tal Watchdog timer CPU FLASH ROM Watch timer RAM Day, minute and second counter On-chip debugger Timer 0 Port 0 Timer 1 Port 1 Timer 2 Port 2 Timer 3 Port 3 Timer 4 Port 4 Timer 5 Port 5 Timer 6 Port 6 Timer 7 Port 7 SIO0 SIO1 Port A Port B Port C SMIIC0 Port D SMIIC1 SMIIC2 SMIIC3 PWM0 PWM1 UART2 UART3 UART4 UART5 ADC Infrared remote controller receive INT0 to INT7 Clock generator No.A1853-9/32 LC88F40H0PA/H0PAU/F0PA/F0PAU/D0PA/D0PAU Pin Description Name VDDCPU VDDPORT1 VDDPORT2 VDDPLL VSS1 VSS2 VSS3 VSS4 Port 0 P00 to P07 I/O I/O + Power sources 3.3V power supply (3.0 to 3.6V) + Power sources I/O power supply (VDDCPU to 5.5V) + Power sources I/O power supply (VDDCPU to 5.5V) + Power sources PLLVCO power supply (3.0 to 3.6V) - Power sources - Power sources - Power sources - Power sources • 8-bit I/O port • I/O specifiable in 1-bit units • Pull-up resistors can be turned on and off in 1 bit units • Port 0 interrupt input (P00 to P05) • HOLD release input (P00 to P05) • Pin functions P06: Timer 0L output P07: Timer 0H output Port 1 P10 to P17 I/O • 8-bit I/O port • I/O specifiable in 1-bit units • Pull-up resistors can be turned on and off in 1 bit units • Pin functions P10: SIO0 data output P11: SIO0 data input/output P12: SIO0 clock input/output P14: Timer 3L output P15: Timer 3H output P16: UART2 receive P17: UART2 transmit Port 2 P20 to P27 I/O • 8-bit I/O port • I/O specifiable in 1-bit units • Pull-up resistors can be turned on and off in 1 bit units • Pin functions P20: INT4 input/HOLD release input/timer 3 event input/timer 2L capture input/ timer 2H capture input P21: INT5 input/HOLD release input/timer 3 event input/timer 2L capture input/ timer 2H capture input P22: SMIIC0 clock input/output P23: SMIIC0 data bus input/output P24: SMIIC0 data (used in 3-wire SIO mode) P25: Timer 4 output P26: Timer 5 output P27: Remote control receive • Interrupt acknowledge type INT4, INT5: H level, L level, H edge, L edge, both edges Port 3 P30 to P37 I/O • 8-bit I/O port • I/O specifiable in 1-bit units • Pull-up resistors can be turned on and off in 1 bit units • Pin functions P30: INT0 input/HOLD release input/timer 2L capture input P31: INT1 input/HOLD release input/timer 2H capture input P32: INT2 input/HOLD release input/timer 2 event input/timer 2L capture input P33: INT3 input/HOLD release input/timer 2 event input/timer 2H capture input P34: UART3 receive P35: UART3 transmit P36: Timer 6 output P37: Timer 7 output • Interrupt acknowledge type INT0 to INT3: H level, L level, H edge, L edge, both edges Supply voltage from VDDPORT2 used (VDDCPU to 5.5V) Supply voltage from VDDPORT1 used (VDDCPU to 5.5V) Supply voltage from VDDPORT2 used (VDDCPU to 5.5V) Supply voltage from VDDPORT1 used (VDDCPU to 5.5V) Description Continued on next page. No.A1853-10/32 LC88F40H0PA/H0PAU/F0PA/F0PAU/D0PA/D0PAU Continued from preceding page. Name Port 4 P40 to P47 I/O I/O • 8-bit I/O port • I/O specifiable in 1-bit units • Pull-up resistors can be turned on and off in 1 bit units • Pin functions P40: INT6 input/HOLD release input P43: SIO1 data output P44: SIO1 data input/output P45: SIO1 clock input/output P46: PWM00 output P47: PWM01 output • Interrupt acknowledge type INT6: H level, L level, H edge, L edge, both edges Port 5 P50 to P57 I/O • 8-bit I/O port • I/O specifiable in 1-bit units • Pull-up resistors can be turned on and off in 1 bit units • Pin functions • Port 5 interrupt function • HOLD release input Port 6 P60 to P67 I/O • 8-bit I/O port • I/O specifiable in 1-bit units • Pull-up resistors can be turned on and off in 1 bit units • Pin functions AN0 (P60) to AN7 (P67): AD converter input port Port 7 P70 to P77 I/O • 8-bit I/O port • I/O specifiable in 1-bit units • Pull-up resistors can be turned on and off in 1 bit units • Pin functions AN8 (P70) to AN12 (P74): AD converter input port P75: SMIIC3 clock input/output P76: SMIIC3 data bus input/output P77: SMIIC3 data (used in 3-wire SIO mode) Port A PA0 to PA7 I/O • 8-bit I/O port • I/O specifiable in 1-bit units • Pull-up resistors can be turned on and off in 1 bit units • Pin functions PA0: SMIIC1 clock input/output PA1: SMIIC1 data bus input/output PA2: SMIIC1 data (used in 3-wire SIO mode) PA3: SMIIC2 clock input/output PA4: SMIIC2 data bus input/output PA5: SMIIC2 data (used in 3-wire SIO mode) PA6: UART5 receive PA7: UART5 transmit Port B PB0 to PB6 I/O • 7-bit I/O port • I/O specifiable in 1-bit units • Pull-up resistors can be turned on and off in 1 bit units • Pin functions PB0: PWM10 output PB1: PWM11 output PB5: INT7 input/HOLD release input • Interrupt acknowledge type INT7: H level, L level, H edge, L edge, both edges Port C PC0 Port D PD0 to PD5 I/O I/O • 1-bit I/O port • I/O specifiable in 1-bit units • Pull-up resistors can be turned on and off in 1 bit units • 6-bit I/O port • I/O specifiable in 1-bit units • Pull-up resistors can be turned on and off in 1 bit units • Pin functions PD0: UART4 receive PD1: UART4 transmit Supply voltage from VDDCPU used (3.0 to 3.6V) Supply voltage from VDDPORT1 used (VDDCPU to 5.5V) Supply voltage from VDDPORT2 used (VDDCPU to 5.5V) Supply voltage from VDDPORT1 used (VDDCPU to 5.5V) Supply voltage from VDDPORT2 used (VDDCPU to 5.5V) Supply voltage from VDDCPU used (3.0 to 3.6V) Supply voltage from VDDCPU used (3.0 to 3.6V) Supply voltage from VDDCPU used (3.0 to 3.6V) Description Supply voltage from VDDPORT1 used (VDDCPU to 5.5V) Continued on next page. No.A1853-11/32 LC88F40H0PA/H0PAU/F0PA/F0PAU/D0PA/D0PAU Continued from preceding page. Name XT1 XT2 RESB TEST I/O I O I I/O • Input terminal for 32.768kHz X'tal oscillation • Output terminal for 32.768kHz X'tal oscillation • Reset pin • This must be set to low for 50μs or longer when the power is turned on and when a reset is required. • TEST pin • Used to communicate with on-chip debugger • 100kΩ pull-down LPFO VREG O O • LPF connection pin for PLLVCO • Regulator output pin Connect a bypass capacitor to this pin Description No.A1853-12/32 LC88F40H0PA/H0PAU/F0PA/F0PAU/D0PA/D0PAU Port Output Types The port output type and pull-up resistance must be set using the registers. The pin data can be read regardless of the I/O setting of the port. The port output type (CMOS output or N-channel open drain output) and use/disuse of the pull-up resistor can be configured separately for each port. * Make the following connection to minimize the noise input to the VDDCPU pin and prolong the backup time. Be sure to electrically short the VSS1, VSS2, VSS3 and VSS4 pins. Example 1: When data is being backed up in the HOLD mode, the H level signals to the output ports are fed by the backup capacitors. (VDDCPU = VDDPORT1 = VDDPORT2 = VDDPLL) LSI Power supply VDDCPU For buckup VDDPORT1 LPFO VDDPORT2 VDDPLL VREG VSS1 VSS2 VSS3 VSS4 Example 2: When data is being backed up in the HOLD mode, the H level output at any ports is not sustained and is unpredictable. (VDDCPU = VDDPORT1 = VDDPORT2 = VDDPLL) LSI Power supply VDDCPU For buckup VDDPORT1 LPFO VDDPORT2 VDDPLL VREG VSS1 VSS2 VSS3 VSS4 No.A1853-13/32 LC88F40H0PA/H0PAU/F0PA/F0PAU/D0PA/D0PAU Absolute Maximum Ratings at Ta = 25°C, VSS1 = VSS2 = VSS3 = VSS4 = 0V Parameter Maximum Supply voltage VDD max(2) Input voltage Input/Output voltage VI(1) VIO(1) Symbol VDD max(1) Applicable Pin /Remarks VDDCPU VDDPLL VDDPORT1 VDDPORT2 RESB, XT1 Ports 5, 6 P70 to 74 Ports C XT2 VIO(2) Ports 0, 1, 2, 3, 4 P75 to P77 Ports A, B, D Peak output current IOPH(1) Ports 0, 1, 2, 3, 5 Ports 6, 7, A, C, D P40 to P45 PB2 to PB6 IOPH(2) Average output current (Note 1-1) IOMH(2) Total output current ΣIOAH(2) ΣIOAH(3) ΣIOAH(1) IOMH(1) P46, P47 PB0, PB1 Ports 0, 1, 2, 3, 5 Ports 6, 7, A, C, D P40 to P45 PB2 to PB6 High level output current P46, P47 PB0, PB1 Ports 5 Ports C Ports 6 P70 to P74 Ports 5, 6 P70 to P74 Ports C ΣIOAH(4) ΣIOAH(5) ΣIOAH(6) ΣIOAH(7) ΣIOAH(8) ΣIOAH(9) Ports 2, D P75 to P77 Ports 0, 4 Ports 0, 2, 4, D P75 to P77 Ports 1, 3 Ports A, B Ports 1, 3, A, B Total of all applicable pins Total of all applicable pins Total of all applicable pins Total of all applicable pins Total of all applicable pins Total of all applicable pins -25 -25 -45 -25 -25 -45 Total of all applicable pins -20 Total of all applicable pins Total of all applicable pins Per 1 application pin -10 -15 mA -15 CMOS output selected Per 1 application pin -7.5 Per 1 application pin -20 CMOS output selected Per 1 application pin -10 -0.3 VDD(2)+0.3 -0.3 VDD(1)+0.3 Conditions min VDDCPU=VDDPORT1 =VDDPORT2=VDDPLL VDDPORT1=VDDPORT2 -0.3 -0.3 -0.3 Specification typ max +4.6 +6.5 VDD(1)+0.3 V unit Note 1-1: Average output current is average of current in 100ms interval. Continued on next page. No.A1853-14/32 LC88F40H0PA/H0PAU/F0PA/F0PAU/D0PA/D0PAU Continued from preceding page. Parameter Peak output current Symbol IOPL(1) Applicable Pin /Remarks Ports 0, 1, 3 Ports 4, 5, 6 Ports B, C, D P20, P21 P24 to P27 P70 to P74, P77 PA2, PA5 to PA7 IOPL(2) P22, P23 P75, P76 PA0, PA1 PA3, PA4 Average output current (Note 1-1) IOML(1) Ports 0, 1, 3 Ports 4, 5, 6 Ports B, C, D P20, P21 Low level output current P24 to P27 P70 to P74, P77 PA2, PA5 to PA7 IOML(2) P22, P23 P75, P76 PA0, PA1 PA3, PA4 Total output current ΣIOAL(2) ΣIOAL(3) ΣIOAL(1) Ports 5 Ports C Ports 6 P70 to P74 Ports 5, 6 P70 to P74 Ports C ΣIOAL(4) ΣIOAL(5) ΣIOAL(6) ΣIOAL(7) ΣIOAL(8) ΣIOAL(9) Allowable power dissipation Operating temperature range Storage temperature range Tstg Topr -40 -45 Pd max Ports 2, D P75 to P77 Ports 0, 4 Ports 0, 2, 4, D P75 to P77 Ports 1, 3 Ports A, B Ports 1, 3, A, B QIP100E Total of all applicable pins Total of all applicable pins Total of all applicable pins Ta = -40 to +85°C Total of all applicable pins Total of all applicable pins Total of all applicable pins 25 25 45 25 25 45 400 +85 +125 mW °C °C Total of all applicable pins 20 Total of all applicable pins Total of all applicable pins 15 15 Per 1 application pin. 15 mA 10 Per 1 application pin. Per 1 application pin. 25 20 Conditions min Per 1 application pin. Specification typ max unit Note 1-1: Average output current is average of current in 100ms interval. No.A1853-15/32 LC88F40H0PA/H0PAU/F0PA/F0PAU/D0PA/D0PAU Allowable Operating Conditions at Ta = -40°C to +85°C, VSS1 = VSS2 = VSS3 = VSS4 = 0V Parameter Operating supply voltage Symbol VDD(1) VDD(2) VHD VIH(1) Applicable Pin /Remarks VDDCPU=VDDPLL VDDPORT1 VDDPORT2 VDDCPU=VDDPORT1 =VDDPORT2=VDDPLL Ports 0, 1, 2, 3, 4 P75 to P77 Ports A, B, D VIH(2) VIH(3) VIH(4) Ports 5, 6, C P70 to P74 RESB P22, P23, P75, P76 PA0, PA1, PA3, PA4 I2C side Low level input voltage VIL(2) VIL(3) VIL(4) VIL(1) Ports 0, 1, 2, 3, 4 P75 to P77 Ports A, B, D Ports 5, 6, C P70 to P74 RESB P22, P23, P75, P76 PA0, PA1, PA3, PA4 I2C side Instruction cycle time Supply voltage rise time Oscillation frequency range FmRC FmX’tal XT1, XT2 Internal RC oscillation 32.768kHz crystal oscillation. Tpup VDDCPU tCYC VDDCPU=VDD(1) 83.3 1 0.5 1.0 32.768 100 2.0 μs ms MHz kHz VDDCPU=VDD(1) VDDPORT=VDD(2) VSS 0.3×VDD(2) VDDCPU=VDD(1) VSS VSS VDDPORT=VDD(2) VSS 0.1×VDD(2) +0.4 0.1×VDD(1) +0.4 0.25×VDD(1) VDDCPU=VDD(1) VDDPORT=VDD(2) 0.7×VDD(2) VDD(2) VDDCPU=VDD(1) RAM and register contents in HOLD mode. VDDPORT=VDD(2) Conditions min 3.0 VDD(1) 1.2 0.3×VDD(2) +0.7 0.3×VDD(1) +0.7 0.75×VDD(1) Specification typ max 3.6 5.5 unit Memory sustaining supply voltage High level input voltage VDD(2) VDD(1) VDD(1) V No.A1853-16/32 LC88F40H0PA/H0PAU/F0PA/F0PAU/D0PA/D0PAU Electrical Characteristics at Ta = -40°C to +85°C, VSS1 = VSS2 = VSS3 = VSS4 = 0V Parameter High level input current Symbol IIH(1) Applicable Pin /Remarks Ports 0, 1, 2, 3, 4 P75 to P77 Ports A, B, D Conditions VDD[V] Output disable Pull-up resistor OFF VIN=VDD(2) (including the off-leak current of the output Tr.) IIH(2) Ports 5, 6, C P70 to P74 RESB Output disable Pull-up resistor OFF VIN=VDD(1) (including the off-leak current of the output Tr.) IIH(3) Low level input current IIL(1) XT1 Ports 0, 1, 2, 3, 4 P75 to P77 Ports A, B, D VIN=VDD(1) Output disable Pull-up resistor OFF VIN=VSS (including the off-leak current of the output Tr.) IIL(2) Ports 5, 6, C P70 to P74 RESB Output disable Pull-up resistor OFF VIN=VSS (including the off-leak current of the output Tr.) IIL(3) High level output voltage VOH(2) VOH(1) XT1 Ports 0, 1, 2, 3 P40 to P45 P75 to P77 Ports A, D PB2 to PB6 VOH(3) VOH(4) VOH(5) VOH(6) Low level output voltage VOL(2) VOL(1) Ports 0, 1, 3, 4 P20, P21 P24 to P27, P77 PA2, PA5 to PA7 Ports B, D VOL(3) VOL(4) VOL(5) Pull-up resistor Rpu(1) Rpu(2) Rpu(3) Hysteresis voltage VHYS Ports 5, 6, C P70 to P74 P22, P23 P75, P76 PA0, PA1 PA3, PA4 Ports 0, 1, 2, 3, 4 P75 to P77 Ports A, B, D Ports 5, 6, C P70 to P74 RESB Ports 1, 2, 3, 4, 5 Ports 7, A, B, C, D Ports 1 to 5, 7, A to D PnFSAn=1 0.1VDD V VOH=0.9VDD IOL=3.0mA IOL=11mA IOL=1.6mA VDDCPU= 3.0 to 3.6 VDDPORT= 4.5 to 5.5 VDDPORT= VDD(1) to 5.5 VDDPORT= 4.5 to 5.5 VDDPORT= VDD(1) to 5.5 VDDCPU= 3.0 to 3.6 0.4 1.5 0.4 15 15 15 35 35 35 80 150 150 kΩ IOL=1.6mA VDDPORT= VDD(1) to 5.5 0.4 P46, P47 PB0, PB1 IOH=-1.6mA, VDD(2) IOL=10mA Ports 5, 6, C P70 to P74 IOH=-0.4mA, VDD(1) IOH=-10mA, VDD(2) IOH=-1.0mA, VDD(1) IOH=-0.4mA, VDD(2) VIN=VSS IOH=-1.0mA, VDD(2) VDDCPU= 3.0 to 3.6 VDDPORT= 4.5 to 5.5 VDDPORT= VDD(1) to 5.5 VDDCPU= 3.0 to 3.6 VDDCPU= 3.0 to 3.6 VDDPORT= 4.5 to 5.5 VDDPORT= VDD(1) to 5.5 VDDPORT= 4.5 to 5.5 VDD(2) -1.0 VDD(2) -0.4 VDD(1) -1.0 VDD(1) -0.4 VDD(2) -1.5 VDD(2) -0.4 1.5 V -0.18 VDDCPU= 3.0 to 3.6 -1 VDDPORT= VDD(1) to 5.5 -1 VDDCPU= 3.0 to 3.6 0.18 μA VDDCPU= 3.0 to 3.6 1 VDDPORT= VDD(1) to 5.5 1 min Specification typ max unit Continued on next page. No.A1853-17/32 LC88F40H0PA/H0PAU/F0PA/F0PAU/D0PA/D0PAU Continued from preceding page. Parameter Pin capacitance Symbol CP Applicable Pin /Remarks All pins Conditions VDD[V] • For pins other than that under test: VIN=VSS • f=1MHz • Ta=25°C Low voltage circuit detection voltage VDET(2) VDDCPU VDET(1) VDDCPU On low voltage detection circuit Excluding the HOLD mode On low voltage detection circuit HOLD mode 2.7 1.27 2.85 1.42 3.0 1.57 V V 10 pF min Specification typ max unit Serial I/O Characteristics at Ta = -40°C to +85°C, VSS1 = VSS2 = VSS3 = VSS4 = 0V 1. SIO0, SIO1 Serial I/O Characteristics (Wakeup Function Disabled) (Note 4-1-1) Parameter Period Low level pulse width High level Input clock pulse width tSCKHA(1) tSCKHBSY (1a) tSCKHBSY (1b) Serial clock Period Low level pulse width High level Output clock pulse width tSCKHA(2) • Automatic communication mode • CMOS output selected • See Fig. 1. tSCKHBSY (2a) tSCKHBSY (2b) Data setup time Serial input tsDI(1) SIO0(P11), SIO1(P44) Data hold time thDI(1) • Automatic communication mode • CMOS output selected • See Fig. 1. • Modes other than automatic communication mode • See Fig. 1. • Specified with respect to rising edge of SIOCLK • See fig. 1. VDDPORT= VDD(1) to 5.5 0.03 Output Input clock delay time tdD0(1) SO0(P10), SO1(P43), SIO0(P11), SIO1(P44) VDDPORT= VDD(1) to 5.5 1tCYC +0.05 • (Note 4-1-2) 1tCYC +0.05 μs 0.03 4 4 23 tCYC VDDPORT= VDD(1) to 5.5 6 tSCKH(2) tSCK(2) tSCKL(2) SCK0(P12) SCK1(P45) • Automatic communication mode • See Fig. 1. • Automatic communication mode • See Fig. 1. • Modes other than automatic communication mode • See Fig. 1. • CMOS output selected • See Fig. 1. 4 1/2 tSCK 1/2 4 tSCKH(1) VDDPORT= VDD(1) to 5.5 Symbol tSCK(1) tSCKL(1) Applicable Pin /Remarks SCK0(P12) SCK1(P45) Conditions VDD[V] • See Fig. 1. min 4 2 2 6 23 Specification typ max unit tCYC Serial output Note 4-1-1: These specifications are theoretical values. Add margin depending on its use. Note 4-1-2: Specified with respect to falling edge of SIOCLK. Specified as the time to the beginning of output state change in open drain output mode. See Fig. 1. Output clock tdD0(2) • (Note 4-1-2) No.A1853-18/32 LC88F40H0PA/H0PAU/F0PA/F0PAU/D0PA/D0PAU 2. SIO0, SIO1 Serial Input/Output Characteristics (Wakeup Function Enabled) (Note 4-2-1) Parameter Period Serial clock Input clock Low level pulse width High level pulse width tSCKHBSY(3) Data setup time Serial input tsDI(2) SIO0(P11), SIO1(P44) Data hold time thDI(2) • Specified with respect to rising edge of SIOCLK • See fig. 1. VDDPORT= VDD(1) to 5.5 0.03 Output Serial output delay time Input clock tdD0(3) SO0(P10), SO1(P43), SIO0(P11), SIO1(P44) VDDPORT= VDD(1) to 5.5 1tCYC +0.05 • (Note 4-2-2) μs 0.03 tSCKH(3) Symbol tSCK(3) tSCKL(3) Applicable Pin /Remarks SCK0(P12) SCK1(P45) VDDPORT= VDD(1) to 5.5 Conditions VDD[V] • See Fig. 1. min 2 1 1 2 Specification typ max unit tCYC Note 4-2-1: These specifications are theoretical values. Add margin depending on its use. Note 4-2-2: Specified with respect to falling edge of SIOCLK. Specified as the time to the beginning of output state change in open drain output mode. See Fig. 1. 3. SMIIC0 to SMIIC3 Simple SIO Mode Input/Output Characteristics Parameter Period Input clock Low level pulse width High level pulse width Period Output clock Low level pulse width High level pulse width Data setup time Serial input tsDI(3) SM0DA(P23) SM1DA(PA1) SM2DA(PA4) Data hold time thDI(3) SM3DA(P76) • Specified with respect to rising edge of SIOCLK • See fig. 1. VDDPORT= VDD(1) to 5.5 0.03 Output delay time Serial output tdD0(4) SM0DO(P24) SM0D1(PA2) SM0D2(PA5) SM0D3(P77) SM0DA(P23) SM1DA(PA1) SM2DA(PA4) SM3DA(P76) • Specified with respect to falling edge of SIOCLK • Specified as interval up to time when output state starts changing. • See Fig. 1. VDDPORT= VDD(1) to 5.5 1tCYC +0.05 0.03 tSCKH(5) tSCK(5) tSCKL(5) SM0CK(P22) SM1CK(PA0) SM2CK(PA3) SM3CK(P75) • CMOS output selected • See Fig. 1. VDDPORT= VDD(1) to 5.5 tSCKH(4) Symbol tSCK(4) tSCKL(4) Applicable Pin /Remarks SM0CK(P22) SM1CK(PA0) SM2CK(PA3) SM3CK(P75) VDDPORT= VDD(1) to 5.5 Conditions VDD[V] • See Fig. 1. min 4 2 tCYC 2 8 1/2 tSCK 1/2 Specification typ max unit Serial clock μs Note 4-5-1: These specifications are theoretical values. Add margin depending on its use. No.A1853-19/32 LC88F40H0PA/H0PAU/F0PA/F0PAU/D0PA/D0PAU tSCKHBSY tSCKHBSY RUN: SIOCLK: DATAIN: DI0 DI1 DI6 DI7 DI8 DIx DATAOUT: DO0 DO1 DO6 DO7 Data transfer period (SIO0 and SIO1 only) DO8 DOx SIOCLK: tSCKL tsDI DATAIN: tSCK tSCKH thDI DATAOUT: Data transfer period (SIO0 and SIO1 only) SIOCLK: tSCKL tsDI thDI tSCKHA DATAIN: tdDO DATAOUT: * Remarks: DIx and DOx denote the last bits communicated; x = 0 to 32768 Figure 1 Serial I/O Waveforms No.A1853-20/32 LC88F40H0PA/H0PAU/F0PA/F0PAU/D0PA/D0PAU 4. SMIIC0 to SMIIC3 I2C Mode Input/Output Characteristics Parameter Period Input clock Low level pulse width High level pulse width Period Output clock Low level pulse width High level pulse width SM0C and SM0DA pins input spike suppression time tsp SM0CK(P22) SM1CK(PA0) SM2CK(PA3) SM3CK(P75) SM0DA(P23) SM1DA(PA1) SM2DA(PA4) SM3DA(P76) Bus release Input time between start and stop tBUF SM0CK(P22) SM1CK(PA0) SM2CK(PA3) SM3CK(P75) tBUFx Output SM0DA(P23) SM1DA(PA1) SM2DA(PA4) SM3DA(P76) • Standard-mode • Specified as interval up to time when output state starts changing. • Fast-mode • Specified as interval up to time when output state starts changing. Start/restart condition hold Input time tHD; STA SM0CK(P22) SM1CK(PA0) SM2CK(PA3) SM3CK(P75) SM0DA(P23) SM1DA(PA1) tHD; STAx Output SM2DA(PA4) SM3DA(P76) • When SMIIC register control bit, I2CSHDS=0 • See fig. 2. • When SMIIC register control bit, I2CSHDS=1 • See fig. 2. • Standard-mode • Specified as interval up to time when output state starts changing. • Fast-mode • Specified as interval up to time when output state starts changing. condition setup time tSU; STAx Output Input Restart tSU; STA SM0CK(P22) SM1CK(PA0) SM2CK(PA3) SM3CK(P75) SM0DA(P23) SM1DA(PA1) SM2DA(PA4) SM3DA(P76) • Standard-mode • Specified as interval up to time when output state starts changing. • Fast-mode • Specified as interval up to time when output state starts changing. setup time Input Stop condition tSU; STO SM0CK(P22) SM1CK(PA0) SM2CK(PA3) tSU; STOx Output SM3CK(P75) SM0DA(P23) SM1DA(PA1) SM2DA(PA4) SM3DA(P76) • Standard-mode • Specified as interval up to time when output state starts changing. • Fast-mode • Specified as interval up to time when output state starts changing. 1.1 VDDPORT= VDD(1) to 5.5 • See fig. 2. 1.0 Tfilt 1.6 VDDPORT= VDD(1) to 5.5 • See fig. 2. 1.0 Tfilt 1.0 VDDPORT= VDD(1) to 5.5 4.1 μs 2.5 Tfilt 2.0 1.6 VDDPORT= VDD(1) to 5.5 5.5 μs • See fig. 2. 2.5 1 Tfilt • See fig. 2. tSCLHx tSCLx tSCLLx SM0CK(P22) SM1CK(PA0) SM2CK(PA3) SM3CK(P75) • Specified as interval up to time when output state starts changing. VDDPORT= VDD(1) to 5.5 tSCLH Symbol tSCL tSCLL Applicable Pin /Remarks SM0CK(P22) SM1CK(PA0) SM2CK(PA3) SM3CK(P75) VDDPORT= VDD(1) to 5.5 Conditions VDD[V] • See Fig. 2. min 5 2.5 Tfilt 2 10 1/2 tSCL 1/2 Specification typ max unit Serial clock 5.5 μs 4.9 μs Note 4-6-1: These specifications are theoretical values. Add margin depending on its use. Continued on next page. No.A1853-21/32 LC88F40H0PA/H0PAU/F0PA/F0PAU/D0PA/D0PAU Continued from preceding page. Parameter Data hold time Input Symbol tHD; DAT Applicable Pin /Remarks SM0CK(P22) SM1CK(PA0) SM2CK(PA3) SM3CK(P75) tHD; DATx Output SM0DA(P23) SM1DA(PA1) SM2DA(PA4) SM3DA(P76) Data setup time Input tSU; DAT SM0CK(P22) SM1CK(PA0) SM2CK(PA3) SM3CK(P75) tSU; DATx Output SM0DA(P23) SM1DA(PA1) SM2DA(PA4) SM3DA(P76) Input Fall time tF SM0CK(P22) SM1CK(PA0) SM2CK(PA3) tF SM3CK(P75) SM0DA(P23) Output SM1DA(PA1) SM2DA(PA4) SM3DA(P76) • When SMIIC register control bits, PSLW=1, P5V=1 • When SMIIC register control bits, PSLW=1, P5V=0 • When SMIIC register control bits, PSLW=0 • Cb ≤ 400pF • See fig. 2. VDDPORT= VDD(1) to 5.5 VDDPORT=5 VDDPORT=3 VDDPORT= VDD(1) to 5.5 20+0.1Cb 20+0.1Cb 300 • Specified as interval up to time when output state starts changing. VDDPORT= VDD(1) to 5.5 1tSCL -1.5Tfilt Tfilt • See fig. 2. 1 • Specified as interval up to time when output state starts changing. VDDPORT= VDD(1) to 5.5 1 1.5 Tfilt • See fig. 2. 0 Conditions VDD[V] min Specification typ max unit 250 ns 250 100 Note 4-6-1: These specifications are theoretical values. Add margin depending on its use. Note 4-6-2: The value of Tfilt is determined by the values of the register SMICnBRG (n=0, 1, 2, 3), bits 7 and 6 (BRP1, BRP0) and the system clock frequency. BRP1 0 0 1 1 BRP0 0 1 0 1 Tfilt tCYC × 1 tCYC × 2 tCYC × 3 tCYC × 4 Set bits (BPR1, BPR0) so that the value of Tfilt falls between the following range: 250ns ≥ Tfilt > 140ns Note 4-6-3: Cb represents the total loads (in pF) connected to the bus pins. Cb ≤ 400pF Note 4-6-4: The standard-mode refers to a mode that is entered by configuring SMICnBRG (n=0, 1, 2, 3) as follows: 250ns ≥ Tfilt > 140ns BRDQ (bit5) = 1 SCL frequency setting ≤ 100kHz The fast-mode refers to a mode that is entered by configuring SMICnBRG (n=0, 1, 2, 3) as follows: 250ns ≥ Tfilt > 140ns BRDQ (bit5) = 0 SCL frequency setting ≤ 400kHz No.A1853-22/32 LC88F40H0PA/H0PAU/F0PA/F0PAU/D0PA/D0PAU P SDA S Sr P tBUF tHD;STA tR tF tHD;STA tsp SCK tLOW tHD;DAT tHIGH tSU;DAT tSU;STA tSU;STO S: Start condition P: Stop condition Sr: Restart condition Figure 2 I2C Timing 5. UART2 to UART5 Operating Conditions at Ta = -40°C to +85°C, VSS1 = VSS2 = VSS3 = VSS4 = 0V Parameter Transfer rate Symbol UBR Applicable Pin /Remarks U2RX(P16), U3RX(P34), U4RX(PD0), U5RX(PA6), U2TX(P17), U3TX(P35), U4TX(PD1), U5TX(PA7) VDDPORT= VDD(1) to 5.5 8 4096 tBGCYC Conditions VDD[V] min Specification typ max unit Note 4-7: tBGCYC denotes one cycle of the baudrate clock source. Pulse Input Conditions at Ta = -40°C to +85°C, VSS1 = VSS2 = VSS3 = VSS4 = 0V Parameter High/low level minimum pulse width Symbol tPIH(1) tPIL(1) Applicable Pin /Remarks INT0(P30), INT1(P31), INT2(P32), INT3(P33), INT4(P20), INT5(P21), INT6(P40), INT7(PB5) tPIL(2) RESB Can be reset via the external reset pin. (Note 5-1) tPIL(3) VDDCPU Can be reset by the low voltage detection circuit. (Note 5-1) (Note 5-2) 50 μs VDDCPU= 3.0 to 3.6 50 μs Conditions VDD[V] • Interrupt source flag can be set. • Event inputs for timers 2 and 3 are enabled. VDDPORT= VDD(1) to 5.5 2 tCYC min Specification typ max unit Note 5-1: This parameter specifies the time required to ensure that the reset sequence is carried out without fail. The reset may be applied even if this time specification is not satisfied. Note 5-2: (VDDCPU voltage) ≤ (Low voltage circuit detection voltage) tPIL tPIH Figure 3 Pulse Input Timing Signal Waveform No.A1853-23/32 LC88F40H0PA/H0PAU/F0PA/F0PAU/D0PA/D0PAU AD Converter Characteristics at Ta = -40°C to +85°C, VSS1 = VSS2 = VSS3 = VSS4 = 0V 1. 12-bit AD Conversion Mode Parameter Resolution Absolute accuracy Conversion time Analog input voltage range Analog port input current IAINH IAINL VAIN=VDDCPU VAIN=VSS Symbol NAD ETAD TCAD12 VAIN Applicable Pin /Remarks AN0(P60) to AN7(P67), AN8(P70) to AN12(P74) (Note 6-1) Conversion time calculated Conditions VDDCPU[V] 3.0 to 3.6 3.0 to 3.6 3.0 to 3.6 3.0 to 3.6 3.0 to 3.6 3.0 to 3.6 -1 102 VSS VDDCPU 1 min Specification typ 12 ±16 max unit bit LSB μs V μA Conversion time calculation formula: TCAD12= ((52/(AD division ratio))+2) × tCYC 2. 8-bit AD Conversion Mode Parameter Resolution Absolute accuracy Conversion time Analog input voltage range Analog port input current IAINH IAINL VAIN=VDDCPU VAIN=VSS Symbol NAD ETAD TCAD8 VAIN Applicable Pin /Remarks AN0(P60) to AN7(P67), AN8(P70) to AN12(P74) (Note 6-1) Conversion time calculated Conditions VDDCPU[V] 3.0 to 3.6 3.0 to 3.6 3.0 to 3.6 3.0 to 3.6 3.0 to 3.6 3.0 to 3.6 -1 32 VSS VDDCPU 1 min Specification typ 8 ±1.5 max unit bit LSB μs V μA Conversion time calculation formula: TCAD8= ((32/(AD division ratio))+2) × tCYC Note 6-1: The quantization error (±1/2LSB) is excluded from the absolute accuracy. Note 6-2: The conversion time refers to the interval from the time a conversion starting instruction is issued till the time the complete digital value against the analog input value is loaded in the result register. The conversion time is twice the normal value when one of the following conditions occurs: • The first AD conversion is executed in the 12-bit AD conversion mode after a system reset. • The first AD conversion is executed after the AD conversion mode is switched from 8-bit to 12-bit AD conversion mode. No.A1853-24/32 LC88F40H0PA/H0PAU/F0PA/F0PAU/D0PA/D0PAU Consumption Current Characteristics at Ta = -40°C to +85°C, VSS1 = VSS2 = VSS3 = VSS4 = 0V Parameter Normal mode consumption current (Note 7-1) IDDOP(2) Symbol IDDOP(1) Applicable Pin /Remarks VDDCPU =VDDPORT1 =VDDPORT2 =VDDPLL Conditions VDD[V] • FmX’tal=32.768kHz crystal oscillation mode • System clock set to VCO (12MHz) • Internal RC oscillation stopped • 1/1 frequency division mode • FmX’tal=32.768kHz crystal oscillation mode • System clock set to VCO (8MHz) • Internal RC oscillation stopped • 1/1 frequency division mode IDDOP(3) • FmX’tal=32.768kHz crystal oscillation mode • System clock set to VCO (4MHz) • Internal RC oscillation stopped • 1/1 frequency division mode IDDOP(4) • FmX’tal=0kHz (oscillation stopped) • System clock set to internal RC oscillation • 1/1 frequency division mode IDDOP(5) • FmX’tal=32.768kHz crystal oscillation mode • System clock set to 32.768kHz • Internal RC oscillation stopped • 1/1 frequency division mode HALT mode consumption current (Note 7-1) IDDHALT(2) IDDHALT(1) VDDCPU =VDDPORT1 =VDDPORT2 =VDDPLL HALT mode • FmX’tal=32.768kHz crystal oscillation mode • System clock set to VCO (12MHz) • Internal RC oscillation stopped • 1/1 frequency division mode HALT mode • FmX’tal=32.768kHz crystal oscillation mode • System clock set to VCO (8MHz) • Internal RC oscillation stopped • 1/1 frequency division mode IDDHALT(3) HALT mode • FmX’tal=32.768kHz crystal oscillation mode • System clock set to VCO (4MHz) • Internal RC oscillation stopped • 1/1 frequency division mode IDDHALT(4) HALT mode • FmX’tal=0kHz (oscillation stopped) • System clock set to internal RC oscillation • 1/1 frequency division mode IDDHALT(5) HALT mode • FmX’tal=32.768kHz crystal oscillation mode • System clock set to 32.768kHz • Internal RC oscillation stopped • 1/1 frequency division mode HOLD mode consumption current HOLDX mode consumption current IDDHOLD(2) VDDCPU HOLDX mode • FmX’tal=32.768kHz crystal oscillation mode 3.0 to 3.6 15 50 IDDHOLD(1) VDDCPU HOLD mode 3.0 to 3.6 1 30 μA 3.0 to 3.6 15 100 3.0 to 3.6 0.2 1 3.0 to 3.6 1.5 3 mA 3.0 to 3.6 2.5 4 3.0 to 3.6 3.5 5 3.0 to 3.6 35 150 μA 3.0 to 3.6 3.5 5 3.0 to 3.6 6 9 3.0 to 3.6 8 12 mA 3.0 to 3.6 10 15 min Specification typ max unit Note 7-1: The consumption current value includes none of the currents that flow into the output transistor and internal pull-up resistors. No.A1853-25/32 LC88F40H0PA/H0PAU/F0PA/F0PAU/D0PA/D0PAU F-ROM Programming Characteristics at Ta = +10°C to +55°C, VSS1 = VSS2 = VSS3 = VSS4 = 0V Parameter Onboard programming current Onboard programming time tFW(1) tFW(2) • 512-byte erase operation • 2-byte programming operation 3.0 to 3.6 3.0 to 3.6 20 40 30 60 ms μs Symbol IDDFW(1) Applicable Pin /Remarks VDDCPU Conditions VDDCPU[V] • Microcontroller erase consumption current is excluded. 3.0 to 3.6 10 20 mA min Specification typ max unit No.A1853-26/32 LC88F40H0PA/H0PAU/F0PA/F0PAU/D0PA/D0PAU Power Pin Treatment Condition 1 (VDDCPU, VSS1) Connect capacitors that meet the following conditions between the VDD1 and VSS1 pins: • Connect among the VDDCPU and VSS1 pins and the capacitors C1 and C2 with the shortest possible lead wires, of the same length (L1=L1’, L2=L2’) wherever possible. • Connect a large-capacity capacitor C1 and a small-capacity capacitor C2 in parallel. • The capacitance of C2 should be approximately 0.1μF or larger. • Please mount a suitable capacitor about C1. • The VDDCPU and VSS1 traces must be thicker than the other traces. L2 L1 VDDCPU C1 C2 VSS1 L1’ L2’ Figure 4 Power Pin Treatment Condition 2 (VDDPORT1 to 2, VSS2 to 3) Connect capacitors that meet the following conditions between the VDDPORT1 to VSS2 and VDDPORT2 to VSS3 pins: • Connect among the VDDPORT1 to 2 and VSS2 to 3 pins and the capacitor C3 with the shortest possible lead wires, of the same length (L3=L3’) wherever possible. • The capacitance of C3 should be approximately 0.1μF or larger. • The VDDPORT1 to 2 and VSS2 to 3 traces must be thicker than the other traces. L3 VDDPORT1/ VDDPORT2 C3 L3’ VSS2/ VSS3 Figure 5 No.A1853-27/32 LC88F40H0PA/H0PAU/F0PA/F0PAU/D0PA/D0PAU Power Pin Treatment Condition 3 (VDDPLL, VSS4) Connect capacitors that meet the following conditions between the VDDPLL and VSS4 pins: • Connect among the VDDPLL and VSS4 pins and the capacitors C4 and C5 with the shortest possible lead wires, of the same length (L4=L4’, L5=L5’) wherever possible. • Connect a large-capacity capacitor C4 and a small-capacity capacitor C5 in parallel. • The capacitance of C4 should be approximately 10μF. • The capacitance of C5 should be approximately 0.1μF. • The VDDPLL and VSS4 traces must be thicker than the other traces. L5 L4 VDDPLL C4 C5 VSS4 L4’ L5’ Figure 6 Power Pin Treatment Condition 4 (VREG, VSS1) Connect capacitors that meet the following conditions between the VREG and VSS1 pins: • Connect among the VREG and VSS1 pins and the capacitors C6 with the shortest possible lead wires, of the same length (L6=L6’) wherever possible. • The capacitance of C6 should be approximately 1μF. • The VREG and VSS1 traces must be thicker than the other traces. L6 VREG C6 VSS1 L6’ Figure 7 No.A1853-28/32 LC88F40H0PA/H0PAU/F0PA/F0PAU/D0PA/D0PAU LPF Pin Treatment Condition (LPFO) Insert a resistor and capacitors that meet the following conditions between the LPFO and VSS4 pins. R1 = 3.3kΩ C7 = 0.068μF C8 = 0.0039μF • Routing traces between the LPFO and VSS4 pins and the resistor and capacitors, and between R1 and C7 must be as short as possible. * After the PLL circuit is activated, 50ms or more is required for stabilizing oscillation. LPFO C8 R1 C7 VSS4 Figure 8 TEST Pin Treatment Condition (TEST) Insert a resistor that meets the following condition between the TEST and VSS1 pins. RTEST = 100kΩ TEST RTEST VSS1 Figure 9 No.A1853-29/32 LC88F40H0PA/H0PAU/F0PA/F0PAU/D0PA/D0PAU Example of Crystal Oscillator Circuit Characteristics Given below are the characteristics of a sample crystal oscillator circuit that were measured using a SANYO-designated oscillation characteristics evaluation board and external components with circuit constant values with which the oscillator vendor confirmed normal and stable oscillation. Table 1 Example of Crystal Oscillator Circuit Characteristics with a Crystal Resonator Circuit Constant Nominal Frequency Vendor Name Oscillator Name C1 [pF] 32.768kHz RIVER ELETEC TFX-03 (CL=12.5pF) 15 C2 [pF] 15 Rd [Ω] 680k Operating Voltage Range [V] VDDCPU= 3.0 to 3.6 Oscillator Stabilization Time tmsX'tal(typ) [s] Remarks The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized after the instruction for starting the XT oscillator circuit is executed plus the time interval that is required for the oscillation to get stabilized after the HOLD mode is released (see Figure 11). Note: The traces to and from the components that are involved in oscillation should be kept as short as possible as the oscillation characteristics are affected by their trace pattern. XT1 XT2 Rd C1 X’tal C2 Figure 10 XT Oscillator Circuit No.A1853-30/32 LC88F40H0PA/H0PAU/F0PA/F0PAU/D0PA/D0PAU Power VDDPORT *1 VDDCPU Power VDDCPU Reset time tPIL(2) Operating VDD lower limit 0V RESB Internal RC oscillation tms X'tal XT1, XT2 Operating mode Unpredictable Reset Initialization instruction execution User instruction execution Figure 11 Reset Time and Oscillation Stabilization Time *1: The voltage when the power is turned on and off must stand in the following relationship: VDDPORT ≥ VDDCPU. It should be noted that, while the VDDPORT power is supplied, the I/O pin remains in an undefined state until the VDDCPU voltage reaches the allowable operation range. HOLD release No HOLD release signal HOLD release signal valid Interrupt operation Internal RC oscillation tms X'tal XT1, XT2 State HOLD HALT Instruction execution Figure 12 HOLD Release and Oscillation Stabilization Time No.A1853-31/32 LC88F40H0PA/H0PAU/F0PA/F0PAU/D0PA/D0PAU Reset Pin Treatment Condition (RESB) VDDCPU RRES RESB CRES (Note) When the power is turned on, the RESB pin must be set to the low level. (A reset period of 50μs or longer is required after the power has stabilized.) Recommended value RRES: 100kΩ CRES: 0.033μF Figure 13 Reset Circuit SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein. SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO Semiconductor Co.,Ltd. products described or contained herein are controlled under any of applicable local export control laws and regulations, such products may require the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written consent of SANYO Semiconductor Co.,Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO Semiconductor Co.,Ltd. product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. Upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third party. SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's intellctual property rights which has resulted from the use of the technical information and products mentioned above. This catalog provides information as of December, 2010. Specifications and information herein are subject to change without notice. PS No.A1853-32/32