LC88F5LA4ACS

Ordering number : ENA1860 LC88F5LA4ACS Overview CMOS IC FROM 96K byte, RAM 6K byte on-chip 16-bit 1-chip Microcontroller The SANYO LC88F5LA4ACS is a 16-bit microcomputer that, centered around an Xstromy16 CPU, integrates on a single chip a number of hardware features such as 96K-byte flash ROM (onboard programmable), 6K-byte RAM, six 16-bit timers, a base timer serving as a time-of-day clock, a real time clock, two synchronous SIO interfaces with automatic transmission capability, a single master I2C/synchronous SIO interface, a slave I2C/synchronous SIO interface, two asynchronous SIO (UART) interfaces, a 4-channel 12-bit resolution AD converter, a watchdog timer, a system clock frequency divider, a 38-source (24 modules) 13-vector interrupt feature, and on-chip debugger feature. Features Xstromy16 CPU • 4G-byte address space • General-purpose registers: 16 bits × 16registers Flash ROM • Capable of onboard programming with a wide range of voltage levels (2.6 to 3.6V). • Block-erasable in 128 or 1K byte units. • Data written in 2-byte units. • 98304 × 8 bits RAM • 6144 × 8 bits * This product is licensed from Silicon Storage Technology, Inc. (USA), and manufactured and sold by SANYO Semiconductor Co., Ltd. Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment (home appliances, AV equipment, communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee thereof. If you should intend to use our products for applications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our customer shall be solely responsible for the use. Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer' s products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer' s products or equipment. Ver.1.00 30211HKIM 20100223-S00001 No.A1860-1/33 LC88F5LA4ACS Minimum instruction cycle time (tCYC) • 100ns (10MHz) VDD = 2.6 to 3.6V • 250ns (4MHz) VDD = 2.2 to 3.6V Ports ● Normal withstand voltage I/O ports Ports whose I/O direction can be designated in 1 bit units ● Oscillation/normal withstand voltage I/O ports ● Oscillation pins ● Reset pins ● TEST pins ● Power pins : 33 (P0n P1n, P20 to P25, P3n, P60 to P62) : 2 (PC0, PC1) : 2 (CF1, CF2) : 1 (RESB) : 1 (TEST) : 7 (VSS1 to 2, VSSA, VDD1 to 3, VDDA) Timers • Timer 0: 16-bit timer that supports PWM/toggle outputs 1) 5-bit prescaler 2) 8-bit PWM × 2, 8-bit timer + 8-bit PWM mode selectable 3) Clock source selectable from system clock, OSC0, OSC1, and internal RC oscillator • Timer 1: 16-bit timer with capture registers 1) 5-bit prescaler 2) May be divided into 2 channels of 8-bit timer 3) Clock source selectable from system clock, OSC0, OSC1, and internal RC oscillator • Timer 2: 16-bit timer with capture registers 1) 4-bit prescaler 2) May be divided into 2 channels of 8-bit timer 3) Clock source selectable from system clock, OSC0, OSC1, and external events • Timer 3: 16-bit timer that supports PWM/toggle outputs 1) 8-bit prescaler 2) 8-bit timer × 2ch or 8-bit timer + 8-bit PWM mode selectable 3) Clock source selectable from system clock, OSC0, OSC1, and external events • Timer 4: 16-bit timer that supports toggle outputs 1) Clock source selectable from system clock and prescaler 0 • Timer 5: 16-bit timer that supports toggle outputs 1) Clock source selectable from system clock and prescaler 0 * Prescaler 0 and 1 are consisted of 4 bits and can choose their clock source from OSC0 or OSC1. • Base timer 1) Clock may be selected from OSC0 (32.768kHz crystal oscillator) and frequency-divided output of system clock. 2) Interrupts can be generated in 7 timing schemes. Real time clock 1) Calender with Jan. 1, 2000 to Dec.31, 2799 including automatic leap year calculation function. 2) Consisted of Independent second- minute-hour-day-month-year-century counters. 3) Programmable count-clock calibration function. No.A1860-2/33 LC88F5LA4ACS Serial interfaces • SIO0: 8-bit synchronous SIO 1) LSB first/MSB first mode selectable 2) Supports data communication with a data length of 8 bits or less (1 to 8 bits specifiable) 3) Built-in 8-bit baudrate generator (4 tCYC to 512 tCYC transfer clocks) 4) Continuous/automatic data transmission (9- to 32768-bit units specifiable) 5) Interval function (intervals specifiable in 0 to 64 tSCK units) 6) Wakeup function • SIO1: 8-bit synchronous SIO 1) LSB first/MSB first mode selectable 2) Supports data communication with a data length of 8 bits or less (1 to 8 bits specifiable) 3) Built-in 8-bit baudrate generator (4 tCYC to 512 tCYC transfer clocks) 4) Continuous/automatic data transmission (9- to 32768-bit units specifiable) 5) Interval function (intervals specifiable in 0 to 64 tSCK units) 6) Wakeup function • SMIIC0: Single master I2C/8-bit synchronous SIO Mode 0: Single-master mode communication Mode 1: Synchronous 8-bit serial I/O (MSB first) • SLIIC0: Slave I2C/8-bit synchronous SIO Mode 0: I2C slave mode communication Mode 1: Synchronous 8-bit serial I/O (MSB first) Note: usable only with the external clock source • UART0 1) Data length : 8 bits (LSB first) 2) Start bits : 1 bit 3) Stop bits : 1 bit 4) Parity bits : None/even parity/odd parity 5) Transfer rate : 4/8 cycle 6) Baudrate source clock : P07 input signal used as a 1 cycle signal (T0PWMH can be used as a clock source) or Timer 4 cycle. 7) Full duplex communication Note: The “cycle” refers to one period of the baudrate clock source. • UART2 1) Data length : 8 bits (LSB first) 2) Start bits : 1 bit 3) Stop bits : 1/2 bit 4) Parity bits : None/even parity/odd parity 5) Transfer rate : 8 to 4096 cycle 6) Baudrate source clock : System clock/OSC0/OSC1/P25 input signal 7) Wakeup function 8) Full duplex communication Note: The “cycle” refers to one period of the baudrate clock source. No.A1860-3/33 LC88F5LA4ACS AD converter 1) 12/8 bits resolution selectable 2) Analog input: 14 channels 3) Comparator mode Watchdog timer 1) Driven by the base timer + internal watchdog timer dedicated counter 2) Interrupt or reset mode selectable Interrupts (peripheral function) • 38 sources (24 modules), 13 vector addresses 1) Provides three levels (low (L), high (H), and highest (X)) of multiplex interrupt control. Any interrupt requests of the level equal to or lower than the current interrupt are not accepted. 2) When interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest level takes precedence over the other interrupts. For interrupts of the same level, the interrupt into the smallest vector address takes precedence. No. 1 2 3 4 5 6 7 8 9 10 11 12 13 Vector Address 08000H 08004H 08008H 0800CH 08014H 08018H 0801CH 08020H 08024H 08030H 08034H 08038H 0803CH Watchdog timer (1) Base timer (2) Timer 0 (2) INT0 (1) INT1 (1) INT2 (1)/timer 1 (2)/UART2 (4) INT3 (1)/timer 2 (4)/SMIIC0 (1)/SLIIC1 (1) INT4 (1)/timer 3 (2) INT5 (1)/timer 4 (1)/SIO1 (2) ADC (1)/timer 5 (1) INT6 (1) INT7 (1)/SIO0 (2)/SIO0(2) Port 0 (3)/RTC (1) Module • 3 priority levels selectable. • Of interrupts of the same level, the one with the smallest vector address takes precedence. • A number enclosed in parentheses denotes the number of sources. Subroutine Stack: 6K-byte RAM area • Subroutine calls that automatically save PSW, interrupt vector calls: 6 bytes • Subroutine calls that do not automatically save PSW: 4 bytes Multiplication/division instructions • 16 bits × 16 bits (18 tCYC execution time) • 16 bits ÷ 16 bits (18 to 19 tCYC execution time) • 32 bits ÷ 16 bits (18 to 19 tCYC execution time) Oscillator circuits • RC oscillator circuit (internal): For system clock • CF oscillator circuit (built-in Rf circuit): For system clock (OSC1) • VMRC oscillator circuit: For system clock (OSC1) • Crystal oscillator circuit (built-in Rf circuit): For low-speed system clock (OSC0) • SLRC oscillator circuit (internal): For system clock (In the case of exception processing) System clock divider function • Can run on low current. • 1/1 to 1/128 of the system clock frequency can be set. No.A1860-4/33 LC88F5LA4ACS Standby Function • HALT mode: Halts instruction execution while allowing the peripheral circuits to continue operation. 1) Oscillation is not halted automatically. 2) Released by a system reset or occurrence of an interrupt. • HOLD mode: Suspends instruction execution and the operation of the peripheral circuits. 1) OSC1, RC and OSC0 oscillators automatically stop. 2) There are the six ways of releasing the HOLD mode. (1) Setting the reset pin to the low level (2) Setting at least one of the INT0, INT1, INT2, INT3, INT4, INT5, INT6, and INT7 pins to the specified level (3) Having an interrupt source established at port 0 (4) Having an interrupt established at SIO0 or SIO1 (5) Having an interrupt established at UART2 • HOLDX mode: Suspends instruction execution and the operation of the peripheral circuits except those which run on OSC0. 1) OSC1 and RC oscillations automatically stop. 2) OSC0 maintains the state that is established when the HOLDX mode is entered. 3) There are seven ways of releasing the HOLDX mode. (1) Setting the reset pin to the low level (2) Setting at least one of the INT0, INT1, INT2, INT3, INT4, INT5, INT6, and INT7 pins to the specified level (3) Having an interrupt source established at port 0 (4) Having an interrupt source established at the base timer circuit (5) Having an interrupt established at SIO0 or SIO1 (6) Having an interrupt established at UART2 . On-chip debugger function • Supports software debugging with the IC mounted on the target board. • Supports source line debugging and tracing functions, and breakpoint setting and real time display. • Single-wire communication Power supply voltage • VDD1, 2 : 2.2 to 3.6V. • VDD3 : (I/O) 1.6 to 3.6V. * Voltage of VDD3 must be lower than VDD1. Package Form • WLP46 (3.03 × 3.03): Lead-free and halogen-free type Development Tools • On-chip debugger: EOCUIF1 + LC88F5LA4A No.A1860-5/33 LC88F5LA4ACS Package Dimensions unit : mm (typ) 3404 TOP VIEW 3.03 SIDE VIEW 0.315 BOTTOM VIEW 0.4 0.315 1234567 3.03 0.4 GFEDCBA 0.68 MAX SIDE VIEW 0.26 0.2 SANYO : WLP46(3.03X3.03) Pin Assignment Top view Bottom view 7 6 5 LC88F5LA4ACS 4 3 2 1 G F E D C B A SANYO: WLP46 (3.03×3.03) (Lead-free and halogen-free type) No.A1860-6/33 LC88F5LA4ACS No. G1 E2 F1 E1 D2 D1 C1 C2 B1 A1 B2 A2 B3 A3 C3 A4 TEST RESB VSSA VSS1 PC0/XT1 PC1/XT2 VDD1 VDDA CF1 CF2 P00/P0INT/AN0 P01/P0INT/AN1 P60/AN2 P61/AN3 P02/P0INT P03/P0INT Name No. B4 D3 A5 B5 A6 C5 A7 B6 B7 C6 C7 D6 D7 D5 E7 E6 P04/P04INT P05/P05INT P06/T0PWML P07/T0PWMH/U0BRG P37/T4O P36/SCK1 P35/SI1/SB1 P34/SO1 P33/SM0DA P32/SM0CK P31/INT1/SM0DO VDD2 VSS2 P30/INT0 P10/SO0 P11/SI0/SB0 Name No. F7 F6 G7 E5 G6 F5 G5 F4 G4 E3 G3 F3 G2 F2 P12/SCK0 P13/U0TX P14/T3OL/U0RX/INT2 P15/T3OH/INT3 P16/U2RX P17/U2TX P62 VDD3 P20/INT4 P21/INT5 P22/SL0CK P23/SL0DA P24/SL0DO/INT6 P25/INT7/T5O Name No.A1860-7/33 LC88F5LA4ACS System Block Diagram VMRC CF RC X’tal Base timer Low speed RC Watchdog timer FLASH ROM Timer 0 RAM Timer 1 Clock generator Xstromy16 CPU On-chip debugger Timer 2 Port 0 Timer 3 Port 1 Timer 4 Port 2 Timer 5 Port 3 UART0 Port 6 UART2 Port C SIO0 INT0 to INT7 SIO1 AD SMIIC0 RTC SLIIC0 No.A1860-8/33 LC88F5LA4ACS Pin Description Pin Name VSS1, VSS2 VSSA VDD1, VDD2 VDD3 VDDA Port 0 P00 to P07 I/O - Power supply Description I/O - Power supply for AD + Power supply + Power supply for port2’s I/O + Power supply for AD • 8-bit I/O port • I/O specifiable in 1-bit units • Pull-up resistors can be turned on and off in 1 bit units • HOLD release input (P00 to P03, P04, P05) • Port 0 interrupt input (P00 to P03, P04, P05) • Pin functions AN0 (P00) to AN1 (P01): AD converter input port P06: Timer 0L output P07: Timer 0L output/UART0 clock input Port 1 P10 to P17 I/O • 8-bit I/O port • I/O specifiable in 1-bit units • Pull-up resistors can be turned on and off in 1 bit units • Pin functions P10: SIO0 data output P11: SIO0 data input/pulse input/output P12: SIO0 clock input/output P13: UART0 transmit P14: Timer 3L output/UART0 receive/ INT2 input/HOLD release/timer 2 event input/timer 2L capture input P15: Timer 3H output/ INT3 input/HOLD release/timer 2 event input/timer 2H capture input P16: UART2 receive P17: UART2 transmit Interrupt acknowledge type INT2, INT3: H level, L level, H edge, L edge, both edges Port 2 P20 to P25 I/O • 6-bit I/O port • I/O specifiable in 1-bit units • Pull-up resistors can be turned on and off in 1 bit units • Pin functions P20: INT4 input/HOLD release input/timer 3 event input/timer 2L capture input/timer 2H capture input P21: INT5 input/HOLD release input/timer 3 event input/timer 2L capture input/timer 2H capture input P22: SLIIC0 clock input/output P23: SLIIC0 bus input/output/data input P24: SLIIC0 data output (used in 3-wire SIO mode)/ INT6 input/HOLD release input P25: Timer 5 output/ INT7 input/HOLD release input Interrupt acknowledge type INT4, INT5, INT6, INT7: H level, L level, H edge, L edge, both edges Port 3 P30 to P37 I/O • 8-bit I/O port • I/O specifiable in 1-bit units • Pull-up resistors can be turned on and off in 1 bit units • Pin functions P30: INT0 input/HOLD release/timer 2L capture input P31: INT1 input/HOLD release/timer 2H capture input/SMIIC0 data output (used in 3-wire SIO mode) P32: SMIIC0 clock input/output P33: SMIIC0 bus input/output/data input P34: SIO1 data output P35: SIO1 data input/bus input/output P36: SIO1 clock input/output P37: Timer 4 output Interrupt acknowledge type INT0, INT1: H level, L level, H edge, L edge, both edges Continued on next page. No.A1860-9/33 LC88F5LA4ACS Continued from preceding page. Pin Name Port 6 P60 to P62 I/O I/O • 3-bit I/O port • I/O specifiable in 1-bit units • Pull-up resistors can be turned on and off in 1 bit units • Pin functions AN2 (P60) to AN3 (P61): AD converter input port Port C PC0 to PC1 I/O • 2-bit I/O port • I/O specifiable in 1-bit units • Pin functions PC0: 32.768kHz crystal oscillator input (XT1) PC1: 32.768kHz crystal oscillator output (XT2) TEST I/O • TEST pin • Used to communicate with on-chip debugger. • Connects an external 100kΩ pull-down resistor. RESB CF1 CF2 I I O Reset pin Ceramic resonator input pin Ceramic resonator output pin Description Port Output Types The table below lists the types of port outputs and the presence/absence of a pull-up resistor. Data can be read into any input port even if it is in the output mode. Port Name P00 to P07 P60 to P62 P10 to P17 P20 to P25 P30 to P37 PC0 PC1 N-channel open drain (32.768kHz crystal oscillator input) Nch-open drain (32.768kHz crystal oscillator output) None None Able to program special functions’ output type from CMOS output or Nch-opendrain Option Selected in Units of 1 bit CMOS Output Type Pull-up Resistor Programmable * Make the following connection to minimize the noise input to the VDD1 pin and prolong the backup time. * Power supply must be VDD1 ≤ VDD3. * Be sure to electrically short the VSS1, VSS2 and VSSA pins. Example 1: When data is being backed up in the HOLD mode, the H level signals to the output ports are fed by the backup capacitors. LSI Power supply For Backup VDD1 VDDA VDD2 Power supply VDD3 VSS1 VSS2 VSSA No.A1860-10/33 LC88F5LA4ACS Example 2: When data is being backed up in the HOLD mode, the H level output at any ports is not sustained and is unpredictable. LSI VDD1 For backup Power supply VDDA VDD2 Power supply VDD3 VSS1 VSS2 VSSA Absolute Maximum Ratings at Ta = 25°C, VSS1 = VSS2 = VSSA = 0V Parameter Maximum supply voltage VDD3 max Input voltage Input/output voltage VIO(2) Peak output current IOPH (2) Average High level output current output current (Note 1-1) Total output current ΣIOAH (2) ΣIOAH (3) ΣIOAH (4) ΣIOAH (5) ΣIOAH (1) IOMH (2) IOMH (1) IOPH (1) VI(1) VIO(1) VDD3 CF1, RESB Ports 0, 1, 3 Port 6 PC0, PC1 Ports 2 P04 to P07, P62 Ports 1, 2, 3 P00 to P03 P60 to P61 P04 to P07, P62 Ports 1, 2, 3 P00 to P03 P60 to P61 P60 to P61 P00 to P03 P04 to P07 P31 to p37 Port 1 P30, P62 P04 to P07, P62 Ports 1, 3 Port 2 Total of currents at applicable pins Total of currents at applicable pins Total of currents at applicable pins Total of currents at applicable pins Total of currents at applicable pins CMOS output selected Per applicable pin Per applicable pin VDD3≤VDD CMOS output selected Per applicable pin Per applicable pin -0.3 -7.5 -4.5 -5 -2.5 -10 -15 -15 -30 -15 mA -0.3 VDD3≤VDD Symbol VDD max Applicable Pin /Remarks VDD1, VDD2, VDDA Conditions VDD[V] VDD1=VDD2=VDDA min -0.3 -0.3 -0.3 Specification typ max +4.0 +4.0 VDD +0.3 VDD +0.3 VDD3 +0.3 unit V Note 1-1: Average output current refers to the average of output currents measured for a period of 100ms. Continued on next page. No.A1860-11/33 LC88F5LA4ACS Continued from preceding page. Parameter Peak output current IOPL(2) Symbol IOPL(1) Applicable Pin /Remarks P04 to P07, P62 Ports 1, 2, 3 P00 to P03 P60 to P61 PC0 to PC1 Average output current (Note 1-1) Low level output current IOML(2) IOML(1) P04 to P07, P62 Port 1, 2, 3 P00 to P03 P60 to P61 PC0 to PC1 Total output current ΣIOAL(2) ΣIOAL(3) P60 to P61 P00 to P03 P00 to P03 P60 to P61 PC0 to PC1 ΣIOAL(4) ΣIOAL(5) ΣIOAL(6) Allowable power dissipation Operating ambient temperature Storage ambient temperature Tstg Topr Pd max P04 to P07 P31 to P37 Ports 1, 2 P30, P62 P04 to P07, P62 Ports 1, 2, 3 WLP46 (3.03×3.03) Total of currents at applicable pins Total of currents at applicable pins Total of currents at applicable pins Ta=-40 to +85°C With thermal resistance board (Note 1-2) -40 -55 +85 °C +125 T.B.D mW 30 60 80 ΣIOAL(1) PC0 to PC1 Total of currents at applicable pins Total of currents at applicable pins Total of currents at applicable pins 15 10 10 mA Per applicable pin 5 Per applicable pin 10 Per applicable pin 7.5 Conditions VDD[V] Per applicable pin min Specification typ max 12.5 unit Note 1-1: Average output current refers to the average of output currents measured for a period of 100ms. Note 1-2: Thermal resistance board is used. No.A1860-12/33 LC88F5LA4ACS Allowable Operating Conditions at Ta = -40°C to +85°C, VSS1 = VSS2 = VSSA = 0V Parameter Operating supply voltage (Note 2-1) Memory sustaining supply voltage High level input voltage VIH(1) VIH(2) VIH(3) VIH(4) Low level input voltage VIL(1) VIL(2) VIL(3) VIL(4) Instruction cycle time (Note 2-2) External system clock frequency FEXCF(1) CF1 • CF2 pin open • System clock frequency division ratio = 1/1 • External system clock DUTY50±5% • CF2 pin open • System clock frequency division ratio = 1/2 2.2 to 3.6 2.6 to 3.6 2.2 to 3.6 0.1 0.2 0.2 4 20 8 MHz 2.6 to 3.6 0.1 10 2.2 to 3.6 0.245 66 tCYC Ports 0, 1, 3, 6 CF1, RESB PC0, PC1 P32, P33 I C side Port 2 Ports 0, 1, 3, 6 CF1, RESB PC0, PC1 P32, P33 I2C side Port 2 VDD3= 1.6V to 3.6V VDD3= 1.6V to 3.6V 2 Symbol VDD(1) Applicable Pin/Remarks VDD1=VDD2=VDDA Conditions VDD[V] 0.098μs≤tCYC≤66μs 0.245μs≤tCYC≤66μs min 2.6 2.2 Specification typ max 3.6 3.6 unit VHD VDD1=VDD2=VDDA RAM and register contents sustained in HOLD mode 2.2 to 3.6 2.2 to 3.6 2.2 to 3.6 2.2 to 3.6 2.2 to 3.6 2.2 to 3.6 2.2 to 3.6 2.2 to 3.6 2.6 to 3.6 1.8 0.7VDD 0.75VDD 0.7VDD 0.7VDD3 VSS VSS VSS VSS 0.098 3.6 VDD VDD VDD VDD3 0.25VDD 0.25VDD 0.3VDD 0.3VDD3 66 μs V Note 2-1: VDD≥2.6V must be maintained when making onboard programming into flash ROM. Note 2-2: Relationship between tCYC and oscillation frequency is 1/FmCF when frequency division ratio is 1/1 and 2/FmCF when the ratio is 1/2. Continued on next page. No.A1860-13/33 LC88F5LA4ACS Continued from preceding page Parameter Oscillation frequency range (Note 2-3) FmMRC(1) FmCF(2) CF1, CF2 Symbol FmCF(1) Applicable Pin /Remarks CF1, CF2 Conditions VDD[V] 10MHz ceramic oscillator mode See Fig. 1. 4MHz ceramic oscillator mode See Fig. 1. Multivaliable RC oscillation When SEL4M=0 center range setting (Note 2-4) FmMRC(2) Multivaliable RC oscillation When SEL4M=1 center range setting (Note 2-4) FmRC FmSLRC FsX'tal XT1, XT2 Internal RC oscillation Internal low-speed RC oscillation 32.768kHz crystal oscillator mode See Fig. 2. 2.2 to 3.6 2.2 to 3.6 2.2 to 3.6 0.5 18 1.0 30 32.768 2.0 45 kHz 2.2 to 3.6 2 4 6 2.6 to 3.6 7.5 10 12.5 MHz 2.2 to 3.6 2.2 to 3.6 min Specification typ 10 4 max unit Note 2-3: See Tables 1 and 2 for oscillator constant values. Note 2-4: To change to a multivaliable RC oscillation as a system clock, wait more than 20μs oscllation stabilizing time after multivaliable RC oscillation is disabled to enabled. No.A1860-14/33 LC88F5LA4ACS Electrical Characteristics at Ta = -40 to +85°C, VSS1 = VSS2 = VSSA = 0V Parameter High level input current Symbol IIH(1) Applicable/ Remarks Ports 0, 1, 3, 6 PC0, PC1 RESB Conditions VDD[V] Output disabled Pull-up resistor off VIN=VDD (including output Tr. off leakage current) IIH(2) IIH(3) CF1 Port 2 VIN=VDD Output disabled Pull-up resistor off VIN=VDD3 VDD3= 1.6V to 3.6V (including output Tr. off leakage current) Low level input current IIL(1) Ports 0, 1, 3, 6 PC0, PC1 RESB Output disabled Pull-up resistor off VIN=VSS (including output Tr. off leakage current) IIL(2) IIL(3) CF1 Port 2 VIN=VSS Output disabled Pull-up resistor off VIN=VSS3 VDD3= 1.6V to 3.6V (including output Tr. off leakage current) High level output voltage VOH(1) VOH(2) VOH(3) VOH(4) VOH(5) Low level output voltage VOL(2) VOL(3) VOL(4) VOL(5) VOL(6) VOL(7) Pull-up resistor Rpu(1) Rpu(2) Rpu(3) Ports 0, 1, 3, 6 Port 2 P22, P23 VOL(1) Ports 0, 1, 6 P30 to P31, P34 to P37 P32, P33 P20 to P21, P24 to P25 IOL=1.3mA IOL=3.0mA IOL=3.0mA VDD3=1.6V to 3.6V IOL=1.3mA VDD3=1.6V to 3.6V IOL=3.0mA VDD3=1.6V to 3.6V IOL=3.0mA VDD3=1.6V to 3.6V VOH=0.9VDD VOH=0.9VDD VDD3=2.2V to 3.6V VOH=0.9VDD VDD3=1.6V to 2.2V Hysteresis voltage VHYS(1) VHYS(2) RESB Port 2 VDD3= 1.6V to 3.6V PnFSA=1 or other function is in input state VHYS(3) Pin capacitance CP Ports 0, 1, 3 All pins PnFSA=1 or other function is in input state Pins other than that under test VIN=VSS, f=1MHz, Ta=25°C 2.2 to 3.6 10 pF 2.2 to 3.6 0.1VDD 2.2 to 3.6 2.2 to 3.6 2.6 to 3.6 2.2 to 3.6 2.2 to 3.6 2.6 to 3.6 2.2 to 3.6 2.2 to 3.6 2.2 to 3.6 2.2 to 3.6 2.2 to 3.6 18 18 30 55 55 80 0.1VDD 0.1VDD3 0.4 0.4 0.4 0.4 0.4 0.32 150 150 200 kΩ Port 2 Ports 0, 1, 3, 6 IOH=-0.6mA IOH=-0.4mA IOH=-0.6mA VDD3= 2.6V to 3.6V IOH=-0.4mA VDD3= 2.6V to 3.6V IOH=-0.2mA VDD3= 1.6V to 3.6V IOL=3.0mA 2.6 to 3.6 2.2 to 3.6 2.6 to 3.6 3.0 to 5.5 2.2 to 5.5 2.6 to 3.6 VDD-0.4 VDD-0.4 VDD3-0.4 VDD3-0.4 VDD3-0.4 0.4 V 2.2 to 3.6 -1 2.2 to 3.6 -15 2.2 to 3.6 -1 μA 2.2 to 3.6 1 2.2 to 3.6 15 2.2 to 3.6 1 min Specification typ max unit V No.A1860-15/33 LC88F5LA4ACS Serial I/O Characteristics at Ta = -40 to +85°C, VSS1 = VSS2 = VSSA = 0V Serial I/O Characteristics (Wakeup Function Disabled) (Note 4-1-1) Parameter Period Low level pulse width High level pulse width Input clock tSCKH(1) tSCKHA(1) • Automatic communication mode • See Fig. 6. tSCKHBSY(1a) • Automatic communication mode • See Fig. 6. tSCKHBSY(1b) • Mode other than automatic communication mode • See Fig. 6. Serial clock Period Low level pulse width High level pulse width Output clock tSCKHA(2) • Automatic communication mode • CMOS output selected • See Fig. 6. tSCKHBSY(2a) • Automatic communication mode • CMOS output selected • See Fig. 6. tSCKHBSY(2b) • Mode other than automatic communication mode • See Fig. 6. Serial input Data setup time tsDI(1) SI0 (P11), SB0 (P11) Data hold time Output Input clock delay time thDI(1) tdD0(1) SO0 (P10), SB0 (P11) • Specified with respect to rising edge of SIOCLK • See Fig. 6. • (Note 4-1-2) 1tCYC +0.05 2.2 to 3.6 1tCYC +0.05 μs 2.2 to 3.6 0.03 0.03 4 4 23 tCYC 2.2 to 3.6 6 tSCKH(2) tSCK(2) tSCKL(2) SCK0 (P12) • CMOS output selected • See Fig. 6. 4 1/2 tSCK 1/2 4 23 2.2 to 3.6 tCYC 6 Symbol tSCK(1) tSCKL(1) Applicable Pin/Remarks SCK0 (P12) Conditions VDD[V] • See Fig. 6. min 4 2 2 Specification typ max unit Serial output Note 4-1-1: These specifications are theoretical values. Add margin depending on its use. Note 4-1-2: Specified with respect to the falling edge of SIOCLK. Specified as the interval up to the time an output change begins in the open drain output mode. See Fig. 6. Output clock tdDO(2) • (Note 4-1-2) No.A1860-16/33 LC88F5LA4ACS SIO0 Serial Input/Output Characteristics (Wakeup Function Enabled) (Note 4-2-1) Parameter Period Serial clock Input clock Low level pulse width High level pulse width Data setup time Serial input tSCKH(3) tSCKHBSY(3) tsDI(2) SI0 (P11), SB0 (P11) Data hold time thDI(2) • Specified with respect to rising edge of SIOCLK • See Fig. 6. 2.2 to 3.6 0.03 Output Input clock delay time tdD0(3) SO0 (P10), SB0 (P11) 2.2 to 3.6 • (Note 4-2-2) 1tCYC +0.05 μs 0.03 Symbol tSCK(3) tSCKL(3) 2.2 to 3.6 Applicable Pin/Remarks SCK0 (P12) Conditions VDD[V] • See Fig. 6. min 2 1 1 2 Specification typ max unit tCYC Note 4-2-1: These specifications are theoretical values. Add margin depending on its use. Note 4-2-2: Specified with respect to the falling edge of SIOCLK. Specified as the interval up to the time an output change begins in the open drain output mode. See Fig.6. Serial output No.A1860-17/33 LC88F5LA4ACS SIO1 Serial Input/Output Characteristics (Wakeup Function Disabled) (Note 4-3-1) Parameter Period Low level pulse width High level pulse width Input clock tSCKH(4) tSCKHA(4) • Automatic communication mode • See Fig. 6. tSCKHBSY(4a) • Automatic communication mode • See Fig. 6. tSCKHBSY(4b) • Mode other than automatic communication mode • See Fig. 6. Serial clock Period Low level pulse width High level pulse width Output clock tSCKHA(5) • Automatic communication mode • CMOS output selected • See Fig. 6. tSCKHBSY(5a) • Automatic communication mode • CMOS output selected • See Fig. 6. tSCKHBSY(5b) • Mode other than automatic communication mode • See Fig. 6. Data setup time Serial input tsDI(3) SI1 (P35), SB1 (P25) Data hold time thDI(3) • Specified with respect to rising edge of SIOCLK • See Fig. 6. 2.2 to 3.6 0.03 Output Input clock delay time tdD0(4) SO1 (P34), SB1 (P35) • (Note 4-3-2) 1tCYC +0.05 2.2 to 3.6 1tCYC +0.05 μs 0.03 4 4 23 tCYC 2.2 to 3.6 6 tSCKH(5) tSCK(5) tSCKL(5) SCK1 (P36) • CMOS output selected • See Fig. 6. 4 1/2 tSCK 1/2 4 23 2.2 to 3.6 tCYC 6 Symbol tSCK(4) tSCKL(4) Applicable Pin/Remarks SCK1 (P36) Conditions VDD[V] • See Fig. 6. min 4 2 2 Specification typ max unit Serial output tdDO(5) Output clock • (Note 4-3-2) Note 4-3-1: These specifications are theoretical values. Add margin depending on its use. Note 4-3-2: Specified with respect to the falling edge of SIOCLK. Specified as the interval up to the time an output change begins in the open drain output mode. See Fig. 6. No.A1860-18/33 LC88F5LA4ACS SIO1 Serial Input/Output Characteristics (Wakeup Function Enabled) (Note 4-4-1) Parameter Period Serial clock Input clock Low level pulse width High level pulse width Data setup time Serial input tSCKH(6) tSCKHBSY(6) tsDI(4) SI1 (P35), SB1 (P35) Data hold time thDI(4) • Specified with respect to rising edge of SIOCLK • See Fig. 6. 2.2 to 3.6 0.03 μs Serial output Output Input clock delay time tdD0(6) SO1 (P34), SB1 (P35) 2.2 to 3.6 • (Note 4-4-2) 1tCYC +0.05 0.03 Symbol tSCK(6) tSCKL(6) 2.2 to 3.6 Applicable Pin/Remarks SCK1 (P36) Conditions VDD[V] • See Fig. 6. min 2 1 1 2 Specification typ max unit tCYC Note 4-4-1: These specifications are theoretical values. Add margin depending on its use. Note 4-4-2: Specified with respect to the falling edge of SIOCLK. Specified as the interval up to the time an output change begins in the open drain output mode. See Fig. 6. SMIIC0 Simple SIO Mode Input/Output Characteristics Parameter Period Input clock Low level pulse width High level pulse width Period Output clock Low level pulse width High level pulse width Data setup time Serial input tsDI(5) SM0DA (P33) • Specified with respect to rising edge of SIOCLK • See Fig. 6. Data hold time thDI(5) 2.2 to 3.6 0.03 Output delay Serial output time tdD0(7) SM0DO (P34), SM0DA (P33) • Specified with respect to falling edge of SIOCLK • Specified as interval up to time when output state starts changing. • See Fig. 6. 2.2 to 3.6 1tCYC +0.05 μs 0.03 tSCKH(8) tSCK(8) tSCKL(8) SM0CK (P32) • CMOS output selected • See Fig. 6. 2.2 to 3.6 tSCKH(7) Symbol tSCK(7) tSCKL(7) Applicable Pin/Remarks SM0CK (P32) See Fig. 6. Conditions VDD[V] min 4 2.2 to 3.6 2 tCYC 2 4 1/2 tSCK 1/2 Specification typ max unit Note 4-5-1: These specifications are theoretical values. Add margin depending on its use. Serial clock No.A1860-19/33 LC88F5LA4ACS SMIIC0 I2C Mode Input/Output Characteristics Parameter Period Input clock Low level pulse width High level pulse width Period Output clock Low level pulse width High level pulse width SM0CK and SM0DA pins input spike suppression time Bus release start and stop Input time between tBUF SM0CK (P32) SM0DA (P33) 2.5 Tfilt • See Fig. 8. tsp SM0CK (P32) SM0DA (P33) • See Fig. 8. 2.2 to 3.6 1 Tfilt tSCLHx tSCLx tSCLLx SM0CK (P32) • Specified as interval up to time when output state starts changing. 2.2 to 3.6 tSCLH Symbol tSCL tSCLL Applicable Pin/Remarks SM0CK (P32) • See Fig. 8. Conditions VDD[V] min 5 2.2 to 3.6 2.5 Tfilt 2 10 1/2 tSCL 1/2 Specification typ max unit Clock tBUFx Output SM0CK (P32) SM0DA (P33) • Standard clock mode • Specified as interval up to time when output state starts changing. • High-speed clock mode • Specified as interval up to time when output state starts changing. 2.2 to 3.6 5.5 μs 1.6 Start/restart condition hold time Input tHD;STA SM0CK (P32) SM0DA (P33) • When SMIIC register control bit, SHDS=0 • See Fig. 8. • When SMIIC register control bit, SHDS=1 • See Fig. 8. 2.5 2.2 to 3.6 4.1 μs 1.0 2.0 Tfilt tHD;STAx Output SM0CK (P32) SM0DA (P33) • Standard clock mode • Specified as interval up to time when output state starts changing. • High-speed clock mode • Specified as interval up to time when output state starts changing. Restart time Input condition setup tSU;STA SM0CK (P32) SM0DA (P33) • See Fig. 8. 1.0 Tfilt tSU;STAx Output SM0CK (P32) SM0DA (P33) • Standard clock mode • Specified as interval up to time when output state starts changing. • High-speed clock mode • Specified as interval up to time when output state starts changing. 2.2 to 3.6 5.5 μs 1.6 Continued on next page. No.A1860-20/33 LC88F5LA4ACS Continued from preceding page Parameter Stop condition Input setup time Symbol tSU;STO Applicable Pin/Remarks SM0CK (P32) SM0DA (P33) • See Fig. 8. 1.0 Tfilt Conditions VDD[V] min Specification typ max unit tSU;STOx Output SM0CK (P32) SM0DA (P33) • Standard clock mode • Specified as interval up to time when output state starts changing. • High-speed clock mode • Specified as interval up to time when output state starts changing. 2.2 to 3.6 4.9 μs 1.6 Data hold time Input tHD;DAT SM0CK (P32) SM0DA (P33) • See Fig. 8. 0 2.2 to 3.6 1 1.5 Tfilt tHD;DATx Output SM0CK (P32) SM0DA (P33) • Specified as interval up to time when output state starts changing. Data setup time Input tSU;DAT SM0CK (P32) SM0DA (P33) • See Fig. 8. 1 2.2 to 3.6 1tSCL -1.5Tfilt Tfilt tSU;DATx Output SM0CK (P32) SM0DA (P33) • Specified as interval up to time when output state starts changing. SM0CK and SM0DA pins fall time Input tF SM0CK (P32) SM0DA (P33) • See Fig. 8. 2.2 to 3.6 300 tF Output SM0CK (P32) SM0DA (P33) • When SMIIC register control bits, PSLW=1, PHV=1 • SM0CK, SM0DA port output FAST mode • Cb≤100pF 2.8 20 +0.1Cb 250 ns 2.6 to 3.6 100 Note 4-6-1: These specifications are theoretical values. Add margin depending on its use. Note 4-6-2: The value of Tfilt is determined by the values of the register SMIC0BRG, bits 7 and 6 (BRP1, BRP0) and the system clock frequency. BRP1 0 0 1 1 BRP0 0 1 0 1 Tfilt tCYC×1 tCYC×2 tCYC×3 tCYC×4 Set bits (BPR1, BPR0) so that the value of Tfilt falls between the following range: 250ns ≥ Tfilt >140ns Note 4-6-3: Cb represents the total loads (in pF) connected to the bus pins. Cb ≤ 100pF Note 4-6-4: The standard clock mode refers to a mode that is entered by configuring SMIC0BRG as follows: 250ns ≥ Tfilt >140ns BRDQ (bit5) = 1 SCL frequency setting ≤ 100kHz The high-speed clock mode refers to a mode that is entered by configuring SMIC0BRG as follows: 250ns ≥ Tfilt >140ns BRDQ (bit5) = 0 SCL frequency setting ≤ 400kHz No.A1860-21/33 LC88F5LA4ACS SLIIC0 Simple SIO Mode Input/Output Characteristics Parameter Period Serial clock Input clock Low level pulse width High level pulse width Data setup time Serial input tsDI(5) SL0DA (P23) • Specified with respect to rising edge of SIOCLK • See Fig. 8. Data hold time thDI(5) 2.2 to 3.6 0.03 μs Serial output Output delay time tdD0(7) SL0DO (P24), SL0DA (P23) • Specified with respect to falling edge of SIOCLK • Specified as interval up to time when output state starts changing. • See Fig. 8. 2.2 to 3.6 1tCYC +0.05 0.03 tSCKH(7) Symbol tSCK(7) tSCKL(7) Applicable Pin/Remarks SL0CK (P22) See Fig. 8. Conditions VDD[V] min 4 2.2 to 3.6 2 2 tCYC Specification typ max unit Note 4-7-1: These specifications are theoretical values. Add margin depending on its use. Note 4-7-2: When not specified, VDD3=1.6V to 3.6V (VDD3≤VDD) No.A1860-22/33 LC88F5LA4ACS SLIIC1 I2C Mode Input/Output Characteristics Parameter Period Input clock Clock Low level pulse width High level pulse width SL0CK and SL0DA pins input spike suppression time Bus release start and stop Input time between tBUF SL0CK (P22) SL0DA (P23) 2.2 to 3.6 2.5 Tfilt • See Fig. 8. tsp SL0CK (P22) SL0DA (P23) • See Fig. 8. 2.2 to 3.6 1 Tfilt tSCLH Symbol tSCL tSCLL Applicable Pin/Remarks SL0CK (P22) • See Fig. 8. Conditions VDD[V] min 5 2.2 to 3.6 2.5 2 Tfilt Specification typ max unit Start/restart condition hold time Input tHD;STA SL0CK (P22) SL0DA (P23) • When SLIIC register control bit, SHDS=0 • See Fig. 8. • When SLIIC register control bit SHDS=1 • See Fig. 8. 2.2 to 3.6 2.5 2.0 Tfilt Restart time Input condition setup tSU;STA SL0CK (P22) SL0DA (P23) • See Fig. 8. 2.2 to 3.6 1.0 Tfilt Stop condition Input setup time tSU;STO SL0CK (P22) SL0DA (P23) • See Fig. 8. 2.2 to 3.6 1.0 Tfilt Data hold time Input tHD;DAT SL0CK (P22) SL0DA (P23) • See Fig. 8. 0 tHD;DATx Output SL0CK (P22) SL0DA (P23) • Specified as interval up to time when output state starts changing. 2.2 to 3.6 Tfilt 1 1.5 Data setup time Input tSU;DAT SL0CK (P22) SL0DA (P23) • See Fig. 8. 1 tSU;DATx Output SL0CK (P22) SL0DA (P23) • Specified as interval up to time when output state starts changing. 2.2 to 3.6 1tSCL -1.5Tfilt Tfilt Continued on next page. No.A1860-23/33 LC88F5LA4ACS Continued from preceding page Parameter SM0CK and Input SM0DA pins fall time tF Symbol Applicable Pin/Remarks SM0CK (P32) SM0DA (P33) • See Fig. 8. 2.2 to 3.6 300 Conditions VDD[V] min Specification typ max unit tF SM0CK (P32) SM0DA (P33) • When SLIIC0 register control bits PSLW=1, PHV=1 When VDD3=2.8V • When SLIIC0 register control bits PSLW=1, PHV=1 When VDD=1.8 • SL0CK, SL0DA port output FAST mode • Cb≤100pF 2.6 to 3.6 2.2 to 3.6 2.8 to 3.6 20 +0.1Cb 250 ns 250 Output 20 +0.1Cb 100 Note 4-8-1: The value of Tfilt is determined by the values of the register SLIC0PCNT, bits 5 and 4 (BRP1, BRP0) and the system clock frequency. BRP1 0 0 1 1 BRP0 0 1 0 1 Tfilt tCYC×1 tCYC×2 tCYC×3 tCYC×4 Set bits (BPR1, BPR0) so that the value of Tfilt falls between the following range: 250ns ≥ Tfilt > 140ns Note 4-8-2: Cb represents the total loads (in pF) connected to the bus pins. Cb ≤ 100pF Note 4-8-3: When not specified, VDD3=1.6V to 3.6V (VDD3≤VDD) No.A1860-24/33 LC88F5LA4ACS UART0 Operating Conditions at Ta = -40 to +85°C, VSS1 = VSS2 = VSSA = 0V Parameter Transfer rate Symbol UBR0 Applicable Pin/Remarks U0RX (P13), U0TX (P14), U0BRG (P07) 2.2 to 3.6 4 8 tBGCYC Conditions VDD[V] min Specification typ max unit Note 4-9: tBGCYC denotes one cycle of the baudrate clock source. UART2 Operating Conditions at Ta = -40 to +85°C, VSS1 = VSS2 = VSSA = 0V Parameter Transfer rate Symbol UBR2 Applicable Pin/Remarks U2RX (P16), U2TX (P17) Conditions VDD[V] 2.2 to 3.6 min 8 Specification typ max 4096 unit tBGCYC Note 4-10: tBGCYC denotes one cycle of the baudrate clock source. Pulse Input Conditions at Ta = -40 to +85°C, VSS1 = VSS2 = VSSA = 0V Parameter High/low level pulse width Symbol tPIH(1) tPIL(1) Applicable Pin/Remarks INT0 (P30), INT1 (P31), INT2 (P14), INT3 (P15), INT4 (P20), INT5 (P21), INT6 (P24), INT7 (P25) tPIL(2) RESB Resetting is enabled. 2.2 to 3.6 10 μs Conditions VDD[V] • Interrupt source flag can be set. • Event inputs for timers 2 and 3 are enabled. 2.2 to 3.6 2 tCYC min Specification typ max unit Note 4-11: When not specified, VDD3=1.6V to 3.6V (VDD3≤VDD) No.A1860-25/33 LC88F5LA4ACS AD Converter Characteristics at Ta = -40 to +85°C, VSS1 = VSS2 = VSSA = 0V 12-bit AD Conversion Mode Parameter Resolution Absolute accuracy Conversion time Symbol NAD ETAD TCAD12 Applicable Pin /Remarks AN0 (P00), AN1 (P01), AN2 (P60), AN3 (P61) (Note 6-1) Conversion time calculated Conditions VDD[V] 2.6 to 3.6 2.6 to 3.6 3.0 to 3.6 2.6 to 3.6 Analog input voltage range Analog port input current IAINH IAINL VAIN=VDD VAIN=VSS VAIN 2.6 to 3.6 2.6 to 3.6 2.6 to 3.6 -1 32 67 VSSA min Specification typ 12 ±16 209 209 VDDA 1 max unit bit LSB μs V μA Conversion time calculation formula: TCAD12= ((52/(AD division ratio))+2) × tCYC 8-bit AD Conversion Mode Parameter Resolution Absolute accuracy Conversion time Symbol NAD ETAD TCAD8 Applicable Pin /Remarks AN0 (P00), AN1 (P01), AN2 (P60), AN3 (P61) (Note 6-1) Conversion time calculated Conditions VDD[V] 2.6 to 3.6 2.6 to 3.6 3.0 to 3.6 2.6 to 3.6 Analog input voltage range Analog port input current IAINH IAINL VAIN=VDD VAIN=VSS VAIN 2.6 to 3.6 2.6 to 3.6 2.6 to 3.6 -1 20 42 VSSA min Specification typ 8 ±1.5 129 129 VDDA 1 max unit bit LSB μs V μA Conversion time calculation formula: TCAD8= ((32/(AD division ratio))+2) × tCYC Note 6-1: The quantization error (±1/2LSB) is excluded from the absolute accuracy. Note 6-2: The conversion time refers to the interval from the time a conversion starting instruction is issued till the time the complete digital value against the analog input value is loaded in the result register. The conversion time is twice the normal value when one of the following conditions occurs: • The first AD conversion is executed in the 12-bit AD conversion mode after a system reset. • The first AD conversion is executed after the AD conversion mode is switched from 8-bit to 12-bit AD conversion mode. No.A1860-26/33 LC88F5LA4ACS Consumption Current Characteristics at Ta=-40 to +85°C, VSS1=VSS2=VSSA=0V typ: 3.0V Parameter Normal mode consumption current (Note 7-1) Symbol IDDOP(1) Applicable Pin/Remarks VDD1 =VDD2 =VDDA ≥VDD3 Conditions VDD[V] • FmCF=10MHz ceramic oscillation mode • FmMRC=0MHz (oscillation stoped) • FmX'tal=32.768kHz crystal oscillation mode • System clock set to 10MHz • Internal RC oscillation stopped • 1/1 frequency division mode IDDOP(2) • FmCF=0Hz (oscillation stopped) • FmMRC=10MHz oscillator mode • FmX'tal=32.768kHz crystal oscillation mode • System clock set to 10MHz • Internal RC oscillation stopped • 1/1 frequency division mode IDDOP(3) • FmCF=0Hz (oscillation stopped) • FmMRC=4MHz oscillator mode • FmX'tal=32.768kHz crystal oscillation mode • System clock set to 4MHz • Internal RC oscillation stopped • 1/1 frequency division mode IDDOP(4) • FmCF=0Hz (oscillation stopped) • FmMRC=0Hz (oscillation stopped) • FmX'tal=32.768kHz crystal oscillator mode • System clock set to internal RC oscillation • 1/1 frequency division mode IDDOP(5) • FmCF=0Hz (oscillation stopped) • FmMRC=0Hz (oscillation stopped) • FmX'tal=32.768kHz crystal oscillator mode • System clock set to 32.768kHz • Internal RC oscillation stopped • 1/1 frequency division mode 2.2 to 3.6 24.4 65 μA 2.2 to 3.6 0.62 1.8 2.2 to 3.6 2.28 3.2 mA 2.6 to 3.6 3.72 6.6 2.6 to 3.6 3.89 7.2 min Specification typ max unit Note 7-1: The consumption current value includes none of the currents that flow into the output transistor and internal pull-up resistors. Continued on next page. No.A1860-27/33 LC88F5LA4ACS Continued from preceding page. Parameter HALT mode consumption current (Note 7-1) Symbol IDDHALT(1) Applicable Pin/Remarks VDD1 =VDD2 =VDDA ≥VDD3 • HALT mode • FmCF=10MHz ceramic oscillation mode • FmMRC=0MHz (oscillation stoped) • FmX'tal=32.768kHz crystal oscillation mode • System clock set to 10MHz • Internal RC oscillation stopped • 1/1 frequency division mode IDDHALT(2) • HALT mode • FmCF=0Hz (oscillation stopped) • FmMRC=10MHz oscillator mode • FmX'tal=32.768kHz crystal oscillation mode • System clock set to 10MHz • Internal RC oscillation stopped • 1/1 frequency division mode IDDHALT(3) • HALT mode • FmCF=0Hz (oscillation stopped) • FmMRC=4MHz oscillator mode • FmX'tal=32.768kHz crystal oscillation mode • System clock set to 4MHz • Internal RC oscillation stopped • 1/1 frequency division mode IDDHALT(4) • HALT mode • FmCF=0Hz (oscillation stopped) • FmMRC=0Hz (oscillation stopped) • FmX'tal=32.768kHz crystal oscillator mode • System clock set to internal RC oscillation • 1/1 frequency division mode IDDHALT(5) • HALT mode • FmCF=0Hz (oscillation stopped) • FmMRC=0Hz (oscillation stopped) • FmX'tal=32.768kHz crystal oscillator mode • System clock set to 32.768kHz • Internal RC oscillation stopped • 1/1 frequency division mode HOLD mode consumption current HOLDX mode consumption current IDDHOLD(2) HOLDX mode • CF1=VDD or open (external clock mode) • FmX'tal=32.768kHz crystal oscillator mode 2.2 to 3.6 5.2 35 IDDHOLD(1) VDD1 HOLD mode • CF1=VDD or open (external clock mode) 2.2 to 3.6 0.02 20 μA 2.2 to 3.6 8.21 40 2.2 to 3.6 0.12 0.5 2.2 to 3.6 0.44 0.8 mA 2.6 to 3.6 1.05 1.8 2.6 to 3.6 1.18 2.0 Conditions VDD[V] min Specification typ max unit Note 7-1: The consumption current value includes none of the currents that flow into the output transistor and internal pull-up resistors. F-ROM Programming Characteristics at Ta = +10°C to +55°C, VSS1=VSS2=VSSA=0V Parameter Onboard programming current Onboard programming time tFW(2) tFW(1) • 128-/1K-byte erase operation • 2-byte programming operation 2.6 to 3.6 2.6 to 3.6 30 60 ms μs Symbol IDDFW(1) Applicable Pin/Remarks VDD1 Conditions VDD[V] • Microcontroller erase current current is excluded. 2.6 to 3.6 7 mA min Specification typ max unit No.A1860-28/33 LC88F5LA4ACS Power Pin Treatment Conditions 1 (VDD1, VSS1) Connect capacitors that meet the following conditions between the VDD1 and VSS1 pins: • Connect among the VDD1 and VSS1 pins and the capacitors C1 and C2 with the shortest possible lead wires, of the same length (L1=L1', L2=L2') wherever possible. • Connect a large-capacity capacitor C1 and a small-capacity capacitor C2 in parallel. The capacitance of C2 should be approximately 0.1μF or larger. • The VDD1 and VSS1 traces must be thicker than the other traces. L2 L1 VSS1 C1 C2 VDD1 L1’ L2’ Power Pin Treatment Conditions 2 (VDD(2, 3), VSS(2)) Connect capacitors that meet the following condition between the VDD(2) and VSS(2), VDD(3) and VSS(2) pins: • Connect among the VDD(2, 3) and VSS(2) pins and the capacitor C3 with the shortest possible lead wires, of the same length (L3=L3') wherever possible. • The capacitance of C3 should be approximately 0.1μF or larger. • The VDD(2, 3) and VSS(2) traces must be thicker than the other traces. L3 VSS(2) C3 VDD(2, 3) L3’ Power Pin Treatment Conditions 3 (VDDA, VSSA) Connect capacitors that meet the following condition between the VDDA and VSSA pins: • Connect among the VDDA and VSSA pins and the capacitor C4 with the shortest possible lead wires, of the same length (L4=L4') wherever possible. • The capacitance of C4 should be approximately 0.1μF or larger. • The VDDA and VSSA traces must be thicker than the other traces. L4 VSSA C4 VDDA L4’ No.A1860-29/33 LC88F5LA4ACS Characteristics of a Sample OSC1 System Clock Oscillation Circuit Given below are the characteristics of a sample main system clock oscillation circuit that are measured using a SANYO-designated oscillation characteristics evaluation board and external components with circuit constant values with which the oscillator vendor confirmed normal and stable oscillation. Table 1 Characteristics of a Sample Main System Clock Oscillator Circuit with a Ceramic Resonator Nominal Frequency Vendor Name Circuit Constant Resonator C3 [pF] 10MHz 8MHz 4MHz MURATA CSTCE10M0G52-R0 CSTCE8M00G52-R0 CSTCR4M00G53-R0 (10) (10) (15) C4 [pF] (10) (10) (15) Rf [Ω] OPEN OPEN OPEN Rd2 [Ω] 0 0 680 Operating Voltage Range [V] 2.2 to 3.6 2.2 to 3.6 2.2 to 3.6 Oscillation Stabilization Time typ [ms] 0.02 0.02 0.02 max [ms] 0.2 0.2 0.2 C1, C2 integrated type C1, C2 integrated type C1, C2 integrated type Remarks The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized after VDD goes above the lower limit level of the operating voltage range (see Figure 4) Characteristics of a Sample System Clock Oscillator Circuit Given below are the characteristics of a sample subsystem clock oscillation circuit that are measured using a SANYOdesignated oscillation characteristics evaluation board and external components with circuit constant values with which the oscillator vendor confirmed normal and stable oscillation. Table 2 Characteristics of a Sample Subsystem Clock Oscillator Circuit with a Crystal Resonator Nominal Frequency Vendor Name EPSON TOYOCOM Circuit Constant Oscillator Name C3 [pF] 32.768kHz MC-306 18 C4 [pF] 18 Rf2 [Ω] OPEN Rd2 [Ω] 0 Operating Voltage Range [V] 2.2 to 3.6 Oscillation Stabilization Time typ [s] 0.9 max [s] 2 Applicable CL value=12.5pF Remarks The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized after the instruction for starting the subclock oscillator circuit is executed plus the time interval that is required for the oscillation to get stabilized after the HOLD mode is released (see Figure 4). Note: The traces to and from the components that are involved in oscillation should be kept as short as possible as the oscillation characteristics are affected by their trace pattern. CF1 CF2 XT1 XT2 Rf1 Rd1 Rf2 Rd2 C1 CF C2 C3 X’tal C4 Figure 1 CF Oscillator Circuit Figure 2 XT Oscillator Circuit 0.5VDD Figure 3 AC Timing Measurement Point No.A1860-30/33 LC88F5LA4ACS VDD Operating VDD lower limit 0V Reset time RESB Power Internal RC oscillation tmsCF CF1, CF2 tmsX'tal XT1, XT2 Operating mode Unpredictable Reset Initialization instruction execution User instruction execution Reset Time and Oscillation Stabilization Time HOLD release No HOLD release signal HOLD release signal valid Interrupt operation Internal RC oscillation tmsCF CF1, CF2 tmsX'tal XT1, XT2 State HOLD HALT Instruction execution HOLD Release and Oscillation Stabilization Time Figure 4 Oscillation Stabilization Time Timing Charts No.A1860-31/33 LC88F5LA4ACS VDD RRES RES CRES Note: Reset signal must be present when power supply rises. Determine the value of CRES and RRES so that the reset signal is present for 10μs after the supply voltage gets stabilized. Figure 5 Reset Circuit tSCKHBSY tSCKHBSY RUN: SIOCLK: DATAIN: DI0 DI1 DI6 DI7 DI8 DIx DATAOUT: DO0 DO1 DO6 DO7 Data RAM transfer period DO8 DOx (SIO0 and SIO1 only) tSCK SIOCLK: tSCKL tsDI DATAIN: tdDO DATAOUT: Data RAM transfer period tSCKH thDI (SIO0 and SIO1 only) SIOCLK: tSCKL tsDI thDI tSCKHA DATAIN: tdDO DATAOUT: * Remarks: DIx and DOx denote the last bits communicated; x = 0 to 32768 Figure 6 Serial I/O Waveforms tPIL tPIH Figure 7 Pulse Input Timing Signal Waveform No.A1860-32/33 LC88F5LA4ACS P SDA tBUF tHD;STA tR tF tHD;STA tsp S Sr P SCK tLOW tHD;DAT tHIGH tSU;DAT tSU;STA tSU;STO S: Start condition P: Stop condition Sr: Restart condition Figure 8 I2C Timing SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein. SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO Semiconductor Co.,Ltd. products described or contained herein are controlled under any of applicable local export control laws and regulations, such products may require the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written consent of SANYO Semiconductor Co.,Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO Semiconductor Co.,Ltd. product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. Upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third party. SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's intellectual property rights which has resulted from the use of the technical information and products mentioned above. This catalog provides information as of March, 2010. Specifications and information herein are subject to change without notice. PS No.A1860-33/33