LC88F85D0A

Ordering number : ENA1954 LC88F85D0A Overview CMOS IC FROM 256K byte, RAM 8K byte on-chip 16-bit 1-chip Microcontroller The LC88F85D0A is a 16-bit microcomputer that, centered around an Xstormy16 CPU core, integrates on a single chip a number of hardware features such as 256K bytes of flash ROM (onboard programmable), 8K bytes of RAM, five 16-bit timers, a time base timer, a synchronous SIO interface with automatic transfer function, a single-master I2C/synchronous SIO interface, two asynchronous SIO (UART) interfaces, a remote control receiver, LCD dedicated RAM, an LCD dotmatrix driver, a 12-bit-resolution 8-channel AD converter, a watchdog timer, a system clock frequency divider, and a 35source 10-vector interrupt feature. Features Xstromy16 CPU • 4G-byte address space • General-purpose registers: 16 bits × 16 Flash ROM • Onboard programmable with a wide range of supply voltages: 3.0 to 5.5V • Block erasable in 512-byte/1K-byte units • Data writing in 2-byte units • 262144 × 8 bits RAM • Data: 8192 × 8 bits • LCD display: 128 × 16 bits * This product is licensed from Silicon Storage Technology, Inc. (USA), and manufactured and sold by SANYO Semiconductor Co., Ltd. Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment (home appliances, AV equipment, communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee thereof. If you should intend to use our products for applications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our customer shall be solely responsible for the use. Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer' s products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer' s products or equipment. Ver.1.00 51111HKIM 20110412-S00003 No.A1954-1/31 LC88F85D0A Minimum instruction cycle time (tCYC) • 100ns (10MHz) VDD = 4.5 to 5.5V • 125ns (8MHz) VDD = 3.0 to 5.5V • 500ns (2MHz) VDD = 2.0 to 5.5V Ports • Normal withstand voltage I/O ports Ports whose I/O direction specifiable in 1-bit units: 20 (P0n, P1n, P20 to P23) • LCD (Pins COM16/SEG0 to COM31/SEG15 are multiplexed with COM and SEG.) LCD driver bias power supply pins 4 (VLCD1 to VLCD4) Step-up capacitor pins 2 (CUP00, CUP01) 16 common mode Segment output 64 (SEG0 to SEG63) Common output 16 (COM0 to COM15) 32 common mode Segment output 48 (SEG16 to SEG63) Common output 32 (COM0 to COM31) • Oscillation dedicated ports 4 (XT1, XT2, CF1, CF2) • Reset pin 1 (RESB) • TEST pin 1 (TEST) • LCD port power pins 2 (LCDVSS0, LCDVSS1) • Power pins 2 (VDD, VSS) LCD • LCD power supply • Number of dots • Contrast • LCD frame frequency : Capacitor step-up type : 1024 (64 segments × 16 commons) / 1536 (48 segments × 32 commons) : Selectable from 16 levels : Selectable from 4 frequencies Timers • Timer 0: 16-bit timer that supports PWM/toggle outputs With 5-bit prescaler 8-bit PWM × 2 / 8-bit timer + 8-bit PWM split mode selectable Clock source selectable from system clock, OSC0, OSC1, and internal RC oscillator • Timer 1: 16-bit timer with a capture register With 5-bit prescaler Can be divided into 8-bit timer × 2 channels Clock source selectable from system clock, OSC0, OSC1, and internal RC oscillator • Timer 3: 16-bit timer that supports PWM/toggle outputs With 8-bit prescaler 8-bit timer × 2 channels / 8-bit timer + 8-bit PWM split mode selectable Clock source selectable from system clock, OSC0, OSC1, and external events • Timer 4: 16-bit timer that supports toggle output Clock source selectable from system clock and prescaler 0 • Timer 5: 16-bit timer that supports toggle output Clock source selectable from system clock and prescaler 0 * The prescaler 0 consists of 4 bits and its clock source is selectable from the system clock, OSC0, and OSC1. • Base timer The clock can be selected from OSC0 (32.768kHz crystal oscillator) and the frequency-divided output of the system clock. Interrupts can be generated in 7 time schemes. Realtime clock (RTC) Calendar function from January 1, 2000 to December 31, 2799 (with automatic leap year compensation) Independent counter configuration for century, year, month, day, hour, minute, and second Programmable count clock correction function No.A1954-2/31 LC88F85D0A Serial interfaces • SIO0: 8-bit synchronous SIO LSB first/MSB first selectable Supports communication of less than 8 bits (1 to 8 bits specifiable). Built-in 8-bit baudrate generator (transfer clock cycles of 4 tCYC to 512 tCYC) Automatic continuous data transfer (9 to 32768 bits specifiable in 1-bit units) Interval function (interval time specifiable in 0 to 64 tSCK units) Wakeup function • SMIIC0: Single-master I2C/8-bit synchronous SIO Mode 0: Single-master master mode communication Mode 1: 8-bit synchronous serial I/O (MSB first) • UART0 Data length: 8 bits (LSB first) Start bits: 1 bit Stop bits: 1 bit Parity bits: None/even parity/odd parity Transfer rate: 4/8 tCYC Baudrate clock source: The P07 input signal is used as a 1 cycle signal (T0PWMH can be used as the clock source) or a timer 4 period. Full duplex communication • UART2 Data length: 8 bits (LSB first) Start bits: 1 bit Stop bits: 1/2 bit Parity bit: None/even parity/odd parity Transfer rate: 8 to 4096 tCYC Baudrate clock source: System clock/OSC0/OSC1/P21 input signal Wakeup function Full duplex communication AD converter 8/12-bit resolution selectable Analog inputs: 12 channels Comparator mode Automatic reference voltage generation Watchdog timer Runs on the base timer + internal watchdog timer dedicated counter. Interrupt or reset signals selectable Infrared remote control receiver Noise rejection function (Noise filter time constant: Approx. 120μs when the 32.768kHz crystal oscillator is selected as the reference clock source) Supports PPM (Pulse Position Modulation), Manchester and other encoding systems. HOLDX mode release function Interrupts (peripheral function) Either "Normal" or "LC888300 Compatible" mode is selectable by user option. * Note: The "LC888300 Compatible" mode is an option that is available to provide compatibility between this model and the LC888300. It is to be unavailable in future developed models. Provides three levels of multiplex interrupt control. Any interrupt request of the level equal to or lower than the current interrupt is not accepted. When interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest level takes precedence over the other interrupts. For interrupts of the same level, the interrupt into the smallest vector address takes precedence. No.A1954-3/31 LC88F85D0A • Normal mode: 35 sources (15 modules), 10 vectors No. 1 2 3 4 5 6 7 8 9 10 Vector 08000H 08004H 08008H 08018H 0801CH 08020H 08024H 08030H 08038H 0803CH Watchdog timer (1) Base timer (2) Timer 0 (2) Timer 1 (2)/UART2 (4) SMIIC0 (1) Timer 3 (2)/infrared remote control receiver (4) Timer 4 (1) ADC (1)/timer 5 (1) SIO0 (2) Port 0 (3)/RTC2 (1)/SEGINT (8) Interrupt Module • LC888300 Compatible mode: 35 sources (15 modules), 13 vectors No. 1 2 3 4 5 6 7 8 9 10 11 12 13 Vector 08000H 08004H 08008H 08018H 0801CH 08020H 08024H 08028H 0802CH 08030H 08034H 08038H 0803CH Watchdog timer (1) Base timer (2) Timer 0 (2) SIO0 (2) Timer 1 (2) UART2 (4) Timer 3 (2) Timer 4 (1) Timer 5 (1) ADC (1) SMIIC0 (1) Infrared remote control receiver (4) Port 0 (3)/RTC2 (1)/SEGINT (8) Interrupt Module • Priority levels X > H > L • When interrupts of the same level occur at the same time, an interrupt with a smaller vector address is given priority. • The number in parentheses indicates the number of sources in a module. Subroutine stack: 8K-byte RAM area • Subroutine calls that automatically save the PSW, interrupt vector call: 6 bytes • Subroutine calls that do not automatically save the PSW: 4 bytes Multiplication/division instructions • 16 bits × 16 bits (18 tCYC execution time) • 16 bits ÷ 16 bits (18 to 19 tCYC execution time) • 32 bits ÷ 16 bits (18 to 19 tCYC execution time) ■Oscillator circuits • RC oscillator circuit (internal): • CF oscillator circuit: • RC oscillator circuit (external RCR1): • Crystal oscillator circuit (Rf built-in): • RC oscillator circuit (external RCR0): • SLRC oscillator circuit (internal): For system clock For system clock (OSC1) For system clock (OSC1) For low-speed system clock (OSC0) (option available) For low-speed system clock (OSC0) For system clock (used during exception processing) ■System clock frequency divider function • Can run on low consumption current. • Supports frequency-dividing of 1/1 to 1/128 of the system clock Standby function • HALT mode: Halts instruction execution while allowing the peripheral circuits to continue operation. 1) Oscillation is not halted automatically. 2) HALT mode is released by a system reset or an interrupt . Continued on next page. No.A1954-4/31 LC88F85D0A Continued from preceding page. • HOLD mode: Suspends instruction execution and the operation of the peripheral circuits. 1) OSC1, RC, and OSC0 oscillations automatically stop. 2) There are five ways of releasing the HOLD mode: Setting the reset pin to the low level Having an interrupt source established at port 0 Having an interrupt source established at SIO0 Having an interrupt source established at UART2 Having an interrupt source established at SEGINT • HOLDX mode: Suspends instruction execution and the operation of all the circuits except the peripheral circuits running on OSC0. 1) OSC1 and RC oscillators automatically stop operation. 2) OSC0 retains the state established when the HOLDX mode is entered. 3) There are seven ways of releasing the HOLDX mode: Setting the reset pin to the low level Having an interrupt source established at port 0 Having an interrupt source established at SIO0 Having an interrupt source established at UART2 Having an interrupt source established at SEGINT Having an interrupt source established in the base timer or RTC2 circuit Having an interrupt source established in the infrared remote control receiver circuit On-chip debugger function • Supports software debugging with the microcontroller mounted on the target board. • Supports source line debugging, tracing, breakpoint manipulation, and realtime display. • Single-wire communication Operating temperature • -20 to +75°C Package form • TQFP120 (14×14) (lead-free type) Development tools • On-chip debugger: EOCUIF1 + LC88F85D0A Package Dimensions unit : mm (typ) 3257A 16.0 14.0 120 1 (1.2) 1.2MAX (1.0) 0.4 0.15 14.0 16.0 0.125 0.1 SANYO : TQFP120(14X14) 0.5 No.A1954-5/31 LC88F85D0A Pad Assignment • Chip size (X × Y) • PAD opening siz • PAD pitch • Chip thickness : 4.10mm × 3.40mm : 59μm : 80μm : 280μm ± 20μm 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 □ □ □ □ □ □ □ □ □ □ 62 61 60 59 58 57 56 55 54 53 Y X (0, 0) □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 □ □ □ □ □ □ □ □ 6 7 8 • Note: Package pin numbers differ from chip pad numbers. The numbers shown in the above figure are pad numbers. 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 1 2 3 4 5 □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ No.A1954-6/31 LC88F85D0A Table of PAD Coordinates Pad No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 P00 P01 P02 P03 P04 P05 P06 P07 P10 P11 P12 P13 P14 P15 P16 P17 P20 P21 P22 P23 SEG63 SEG62 SEG61 SEG60 SEG59 SEG58 SEG57 SEG56 SEG55 SEG54 SEG53 VSS CF1 CF2 VDD Pin Name VLCD4 VLCD3 VLCD2 VLCD1 TST XT2 XT1 RESB Coordinate X μm -1647.9 -1567.9 -1483.2 -1403.2 -1184.0 -890.0 -781.5 -670.0 -494.5 -374.5 -263.5 -165.0 -85.0 10.0 110.0 210.0 300.0 380.0 460.0 540.0 620.0 700.0 780.0 860.0 940.0 1020.0 1100.0 1180.0 1260.0 1340.0 1420.0 1500.0 1919.9 1919.9 1919.9 1919.9 1958.5 1958.5 1958.5 1958.5 1958.5 1958.5 1958.5 1958.5 1958.5 1958.5 1958.5 Y μm -1569.9 -1569.9 -1569.9 -1569.9 -1569.9 -1569.9 -1569.9 -1569.9 -1569.9 -1569.9 -1569.9 -1569.9 -1569.9 -1569.9 -1569.9 -1569.9 -1569.9 -1569.9 -1569.9 -1569.9 -1569.9 -1569.9 -1569.9 -1569.9 -1569.9 -1569.9 -1569.9 -1569.9 -1569.9 -1569.9 -1569.9 -1569.9 -1415.0 -1325.0 -1192.0 -1057.0 -871.8 -781.8 -691.8 -601.8 -511.8 -421.8 -331.8 -241.8 -61.8 28.2 118.2 Pad No. 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 Pin Name SEG52 SEG51 SEG50 SEG49 SEG48 SEG47 SEG46 SEG45 SEG44 SEG43 SEG42 SEG41 SEG40 SEG39 SEG38 LCDVSS1 SEG37 SEG36 SEG35 SEG34 SEG33 SEG32 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 COM31/SEG15 COM30/SEG14 COM29/SEG13 COM28/SEG12 Coordinate X μm 1958.5 1958.5 1958.5 1958.5 1958.5 1919.9 1919.9 1919.9 1919.9 1919.9 1919.9 1919.9 1919.9 1919.9 1919.9 1420.0 1300.0 1190.0 1080.0 990.0 910.0 830.0 750.0 670.0 590.0 510.0 430.0 350.0 270.0 190.0 110.0 30.0 -50.0 -130.0 -210.0 -290.0 -370.0 -450.0 -620.0 -780.0 -940.0 -1100.0 Y μm 208.2 298.2 388.2 478.2 568.2 710.0 790.0 870.0 950.0 1030.0 1110.0 1190.0 1280.0 1370.0 1460.0 1569.9 1569.9 1569.9 1569.9 1569.9 1569.9 1569.9 1569.9 1569.9 1569.9 1569.9 1569.9 1569.9 1569.9 1569.9 1569.9 1569.9 1569.9 1569.9 1569.9 1569.9 1569.9 1569.9 1569.9 1569.9 1569.9 1569.9 - Continued on next page. No.A1954-7/31 LC88F85D0A Continued from preceding page. Pad No. 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 Pin Name COM27/SEG11 COM26/SEG10 COM25/SEG9 COM24/SEG8 COM23/SEG7 COM22/SEG6 COM21/SEG5 COM20/SEG4 COM19/SEG3 COM18/SEG2 COM17/SEG1 Coordinate X μm -1260.0 -1420.0 -1580.0 -1919.9 -1919.9 -1919.9 -1919.9 -1919.9 -1919.9 -1919.9 -1919.9 Y μm 1569.9 1569.9 1569.9 1340.0 1180.0 1020.0 860.0 700.0 540.0 380.0 220.0 Pad No. 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 Pin Name COM16/SEG0 COM15 COM14 COM13 COM12 COM11 COM10 COM9 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 COM0 LCSVSS0 CUP00 CUP01 Coordinate X μm -1919.9 -1919.9 -1919.9 -1919.9 -1919.9 -1919.9 -1919.9 -1919.9 -1919.9 -1919.9 -1919.9 -1919.9 -1919.9 -1919.9 -1919.9 -1919.9 -1919.9 -1919.9 -1919.9 -1919.9 Y μm 60.0 -20.0 -100.0 -180.0 -260.0 -340.0 -420.0 -500.0 -580.0 -660.0 -740.0 -820.0 -900.0 -980.0 -1060.0 -1140.0 -1220.0 -1320.0 -1443.3 -1523.3 Note: • The coordinate values shown in the above table represent the coordinates of the pin pads measured with the center coordinates of the IC set to (0, 0). • There are three pads for each of the VDD and VSS pins. They should be triple bonded. No.A1954-8/31 LC88F85D0A Pin Assignment COM25/SEG9 COM26/SEG10 COM27/SEG11 COM28/SEG12 COM29/SEG13 COM30/SEG14 COM31/SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 LCDVSS1 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 COM24/SEG8 COM23/SEG7 COM22/SEG6 COM21/SEG5 COM20/SEG4 COM19/SEG3 COM18/SEG2 COM17/SEG1 COM16/SEG0 COM15 COM14 COM13 COM12 COM11 COM10 COM9 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 COM0 LCSVSS0 CUP00 CUP01 LC88F85D0A XT2 XT1 RESB VDD CF1 CF2 VSS P00/P0LI/AN8 P01/P0LI/AN9 P02/P0LI/AN10 P03/P0LI/AN11 P04/P0HLI/AN12 P05/P0HLI/AN13 P06/T0PWML/AN14 P07/T0PWMH/AN15 P10/SI0O P11/SI0IO P12/SI0CK P13/T3PWML P14/T3PWMH/U0RX P15/U0TX P16/U2RX P17/U2TX VLCD4 VLCD3 VLCD2 VLCD1 TEST 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48/SGND15/SGIN15 SEG49/SGND14/SGIN14 SEG50/SGND13/SGIN13 SEG51/SGND12/SGIN12 SEG52/SGND11/SGIN11 SEG53/SGND10/SGIN10 SEG54/SGND9/SGIN9 SEG55/SGND8/SGIN8 SEG56/SGND7/SGIN7/SGINT7 SEG57/SGND6/SGIN6/SGINT6 SEG58/SGND5/SGIN5/SGINT5 SEG59/SGND4/SGIN4/SGINT4 SEG60/SGND3/SGIN3/SGINT3 SEG61/SGND2/SGIN2/SGINT2 SEG62/SGND1/SGIN1/SGINT1/T3IH SEG63/SGND0/SGIN0/SGINT0/T3IL P23/AN3/SM0DA P22/AN2/SM0CK P21/AN1/T5O P20/AN0/T4O/RMIN Top view SANYO: TQFP120 (14×14) “Lead-free Type” No.A1954-9/31 LC88F85D0A System Block Diagram CF RC RC X’tal RC Base timer Low speed RC Watchdog timer FLASH ROM Timer 0 RAM Timer 1 Clock generator Xstormy16 CPU On-chip debugger Timer 3 Port 0 Timer 4 Port 1 Timer 5 Port 2 UART0 AD UART2 RTC2 SIO0 SMIIC0 LCD control Infrared remote control receiver LCD display RAM No.A1954-10/31 LC88F85D0A Pin Description Pin Name VSS VDD VLCD1 to 4 LCDVSS0, LCDVSS1 CUP00, CUP01 PORT 0 P00 to P07 I/O I/O - Power supply pin + Power supply pin LCD bias power source (connected to capacitors) LCD port power source (-) Switching pins for generating the LCD drive voltage. A capacitor must be connected across both pins. • 8-bit I/O port • I/O specifiable in 1 bit units • Pull-up registers can be turned on and off in 1-bit units. • HOLD releaset inputs (P00 to P03, P04, P05) • Port 0 interrupt inputs (P00 to P03, P04, P05) • Pin functions P00 (AN8) to P07 (AN15): AD converter inputs P06: Timer 0L output P07: Timer 0H output/UART0 clock input PORT 1 P10 to P17 I/O • 8-bit I/O port • I/O specifiable in 1-bit units • Pull-up registers can be turned on and off in 1-bit units. • Pin functions P10: SIO0 data output P11: SIO0 data input/bus input/output P12: SIO0 clock input/output P13: Timer 3L output P14: Timer 3H output/UART0 receive P15: UART0 transmit P16: UART2 receive P17: UART2 transmit PORT 2 P20 to P23 I/O • 4-bit I/O port • I/O specifiable in 1-bit units • Pull-up registers can be turned on and off in 1-bit units. • Pin functions P20 (AN0) to P23 (AN3): AD converter inputs P20: Timer 4 output/remote controller receive P21: Timer 5 output P22: SMIIC0 clock input/output P23: SMIIC0 bus input/output/data input COM0 to COM15 COM16/SEG0 to COM31/SEG15 SEG16 to SEG47 SEG48 to SEG63 O I/O O O • LCD common output • LCD common output/segment output Common output/segment output switched by a register • LCD segment output • LCD segment output • SEG63-SEG48: General-purpose N-channel open drain output/general-purpose input SEG63-SEG48: LCD output in 4-bit units/general-purpose N-channel open drain output/general-purpose input selectable • SEG63-SEG56: Interrupt function (4-bit units) Chatter removal sampling frequency select (4-bit units) Level/edge sense mode select (4-bit units) Hi/low level or rising/falling edge sense mode select (1-bit units) • SEG63-SEG62: Timer 3 external input TEST I/O • TEST pin • On-chip debugger communication pin • An external 100kΩ pull-down resistor must be connected. RESB CF1 CF2 XT1 XT2 I I O I O Reset pin Ceramic oscillator input/RC oscillator resistor to be connected Ceramic oscillator output 32.768kHz crystal oscillator input/RC oscillator resistor to be connected 32.768kHz crystal oscillator output Description No.A1954-11/31 LC88F85D0A Port Output Types The table below lists the types of port outputs and the presence/absence of a pull-up resistor. Data can be read into any input port even if it is in the output mode. Port Name P00 to P07 P10 to P17 P20 to P23 SEG48 to SEG63 4 bits Options Selected in Units of 1 bit 1 bit CMOS Multiplexed pin outputs are programmable either as CMOS or N-channel open drain output. N-channel open drain (LCD segment output) None Output Type Pull-up Resistor Programmable Programmable Table of User Options Option Name X'tal OSC (*1) Normal Low Power Interrupt Vector (*2) Normal LC888300 Compatible Option Normal XT mode Low power XT mode Interrupt vector switching Description *1 The circuit constant values of the external components and oscillation stabilization time differ between the normal XT mode and low power XT mode. *2 The "LC888300 Compatible" mode is an option that is available to provide compatibility between this model and the LC888300. It is to be unavailable in future models. No.A1954-12/31 LC88F85D0A Application circuit LCD panel 64×16/48×32 COM0 COM15 SEG16 COM16/SEG0 COM31/SEG15 SEG63 I/O P00 P01 P02 P03 P04 P05 P06 P07 CUP01 CUP00 C1 C2 C3 C4 C5 VLCD4 VLCD3 VLCD2 VLCD1 LC88F85D0A I/O UART device P10 (SIO0-OUT) P11 (SIO0-IN) P12 (SIO0-CLK) P13 P14 P15 P16 (UART2-RX) P17 (UART2-TX) VDD 2.3V to 5.5V + CDEN CRES RESB Pulse output I/O P20 P21 P22 P23 VSS LCDVSS0 LCDVSS1 XT2 CF2 RTST CF1 XT1 On-chip debugger TST CF CDC CCR1 RCR1 CGC *3 X'tal CDX *1: Crystal oscillation *2: Internal RC oscillation *3: Ceramic oscillation CGX *1 CCR0 RCR0 *5 *4 X'tal CGX CDX RCR0 CCR0 (*1) CF CGC CDC RCR1 CCR1 C1 to C5 CDEN CRES RTST Crystal resonator Trimmer capacitor Capacitor for X’tal oscillator Resistor for low-speed oscillator Capacitor for low-speed oscillation stabilization *4: RC oscillation type *4: RC oscillation type (*1) 0.1μF capacitor is recommended when using XT1/XT2 as the system clock source. Ceramic resonator Capacitor for CF oscillator Capacitor for CF oscillator Resistor for high-speed oscillation Capacitor for high-speed oscillation stabilization Capacitor Electrolytic capacitor Capacitance for RESB Resistor used when using the on-chip debugger *5: RC oscillation type *5: RC oscillation type No.A1954-13/31 LC88F85D0A Absolute Maximum Ratings at Ta = 25°C, VSS = LCDVSS0 = LCDVSS1 = 0V Parameter Maximum supply voltage LCD supply voltage Maximum LCD supply voltage Input voltage Input/output voltage Peak output current High level output current IOPH(2) Mean output current (Note 1-1) Total output current IOMH(2) ΣIOAH(1) ΣIOAH(2) ΣIOAH(3) Peak output current Low level output current Mean output current (Note 1-1) Total output current ΣIOAL(2) ΣIOAL(3) Allowable power dissipation Operating ambient temperature Storage ambient temperature Tstg Topr -20 -65 Pd max Port 1 Ports 0, 1, 2 Total of all applicable pins Total of all applicable pins Ta=-20 to +75°C ΣIOAL(1) Ports 0, 2 Total of all applicable pins IOPL(1) IOPL(2) IOML(1) IOML(2) Port 1 Ports 0, 2 Port 1 Ports 0, 1, 2 Ports 0, 2 Port 1 Ports 0, 2 Port 1 IOMH(1) Port 1 Ports 0, 2 IOPH(1) VI(1) VIO(1) LCD max SEG0 to SEG63 COM0 to COM31 CF1, XT1, RESB Ports 0, 1, 2 SEG63 to SEG48 Ports 0, 2 CMOS output select Per 1 applicable pin Per 1 applicable pin CMOS output select Per 1 applicable pin CMOS output select Per 1 applicable pin Total of all applicable pins Total of all applicable pins Total of all applicable pins Per 1 applicable pin Per 1 applicable pin Per 1 applicable pin Per 1 applicable pin VDD, VLCD4 VLCD max VLCD2 to VLCD4 VDD Symbol VDD max Pin/Remarks VDD VDD Conditions Specification VDD[V] min -0.3 -0.3 -0.3 -0.3 -0.3 -5 -14 -3 -9 -22.5 -25 -47.5 13 17 7.5 10.5 35 60 80 250 +75 °C +125 mW mA typ max +6.5 +6.5 +6.5 VDD+0.3 VDD+0.3 V unit Note 1-1: The mean output current is a mean value measured over 100ms. No.A1954-14/31 LC88F85D0A Allowable Operating Conditions at Ta = -20°C to +75°C, VSS = LCDVSS0 = LCDVSS1 = 0V Parameter Operating supply voltage (Note2-1) LCD drive voltage Memory sustaining supply voltage High level input voltage VIH(2) Low level input voltage VIL(2) Instruction cycle time (Note 2-2) External system clock frequency FEXCF(1) CF1 • CF2 pin open • System clock frequency division ratio=1/1 • External system clock duty=50±5% Oscillation frequency range (Note 2-3) FmCF(3) FmRC FmSLRC FsX'tal FmRC1(1) FmRC1(2) FsRC0 XT1, XT2 CF1 CF1 XT1 CF1,CF2 FmCF(2) CF1,CF2 FmCF(1) CF1,CF2 10MHz ceramic oscillation See Fig. 1. 8MHz ceramic oscillation See Fig. 1. 4MHz ceramic oscillation See Fig. 1. Internal RC oscillation Internal SLRC oscillation 32.768kHz crystal oscillation See Fig. 2. High-speed RC oscillation (Note 2-4) High-speed RC oscillation (Note 2-4) Low-speed RC oscillation (Note 2-4) tCYC CF1, RESB 4.5 to 5.5 3.0 to 5.5 2.0 to 5.5 4.5 to 5.5 3.0 to 5.5 2.0 to 5.5 4.5 to 5.5 3.0 to 5.5 2.4 to 5.5 2.0 to 5.5 2.0 to 5.5 2.2 to 5.5 2.4 to 5.5 2.0 to 5.5 2.2 to 5.5 400 400 30 0.5 18 VIL(1) CF1, RESB Ports 0, 1, 2 Output disabled VIH(1) Ports 0, 1, 2 Output disabled 0.30VDD +0.70 0.75VDD VSS VSS 0.098 0.123 0.490 0.1 0.1 0.1 10 8 4 1.0 30 32.768 4200 2000 80 2.0 45 VDD VDD 0.10VDD +0.40 0.25VDD 66 66 66 10 8 2 MHz μs VHD VDD RAM and register contents sustained in HOLD mode. 2.0 5.5 V VLCD(1) VLCD2 to VLCD4 Symbol VDD(1) Pin/Remarks VDD Conditions 0.098μs≤tCYC≤66μs 0.123μs≤tCYC≤66μs 0.490μs≤tCYC≤66μs Ratings VDD[V] min 4.5 3.0 2.0 typ max 5.5 5.5 5.5 5.5 unit MHz kHz Note2-1: VDD must be held greater than or equal to 3.0V when onboard writing to flash ROM. Note2-2: Relationship between tCYC and oscillation frequency is 1/FmCF at a frequency division ratio of 1/1 and 2/FmCF at a division ratio of 1/2. Note2-3: See Tables 1 and 2 for the oscillation constants. Note2-4: Ta=0°C to 60°C No.A1954-15/31 LC88F85D0A Electrical Characteristics at Ta = -20°C to +75°C, VSS = LCDVSS0 = LCDVSS1 = 0V Parameter High level input current Symbol IIH(1) Pin/Remarks Ports 0, 1, 2 RESB Conditions Output disabled Pull-up resistor off VIN=VDD (including output Tr off leakage current) Low level input current IIL(1) Ports 0, 1, 2 Output disabled Pull-up resistor off VIN=VSS (including output Tr off leakage current) High-level output voltage VOH(1) VOH(2) VOH(3) VOH(4) VOH(5) Low level output voltage VOL(1) VOL(2) VOL(3) VOL(4) VOL(5) Pull-up resistance Rpu(1) Rpu(2) Hysteresis voltage Pin capacitance VHYS CP Ports 0, 1, 2 RESB All pins For pins other than that under test VIN=VSS f=1MHz Ta=25°C 2.0 to 5.5 10 pF COM0 to COM31 SEG0 to SEG63 Ports 0, 1, 2 COM0 to COM31 SEG0 to SEG63 Ports 0, 1, 2 Ports 0, 1, 2 IOH=-1.0mA IOH=-0.4mA IOH=-0.1mA IOH=-25μA IOH=-10μA IOL(1)=10mA IOL(1)=1.6mA IOL(1)=0.7mA IOLH=25μA IOL=10μA VOH=0.9VDD 4.5 to 5.5 3.0 to 5.5 2.0 to 5.5 2.0 to 5.5 2.0 to 5.5 4.5 to 5.5 3.0 to 5.5 2.0 to 5.5 2.0 to 5.5 2.0 to 5.5 4.5 to 5.5 2.0 to 4.5 2.0 to 5.5 15 18 35 55 0.1VDD VDD-1 VDD-0.4 VDD-0.4 VLCD4 -0.05 VLCD4 -0.05 1.5 0.4 0.4 VSS +0.05 VSS +0.05 80 180 kΩ V 2.7 to 5.5 -1 μA 2.0 to 5.5 1 μA Specification VDD[V] min typ max unit V No.A1954-16/31 LC88F85D0A LCD Drive Voltage at Ta = -20°C to +75°C, VSS = LCDVSS0 = LCDVSS1 = 0V Special notes: 0.1μF capacitors are connected to VLCD1, VLCD2, VLCD3, and VLCD4. (with no panel load) Parameter LCD drive voltage Symbol VLCD1 Pin/Remarks VDD VLCD1 Conditions Contrast “00” Contrast “01” Contrast “02” Contrast “03” Contrast “04” Contrast “05” Contrast “06” Contrast “07” Contrast “08” Contrast “09” Contrast “10” Contrast “11” Contrast “12” Contrast “13” Contrast “14” Contrast “15” VLCD2 VLCD3 VLCD4 2.0 to 5.5 Typ ×0.88 Specification VDD[V] min typ 1.030 1.045 1.060 1.075 1.090 1.105 1.120 1.135 1.150 1.165 1.180 1.195 1.210 1.225 1.240 1.255 2×VLCD1 3×VLCD1 4×VLCD1 Typ ×1.10 V max unit No.A1954-17/31 LC88F85D0A Serial I/O Characteristics at Ta = -20°C to +75°C, VSS = LCDVSS0 = LCDVSS1 = 0V SIO0 Serial I/O Characteristics (When wakeup function is not in used) (Note 4-1-1) Parameter Frequency Low level pulse width High level pulse width Input clock tSCKHA(1) • Automatic communication mode • See Fig. 6. tSCKHBSY(1a) • Automatic communication mode • See Fig. 6. tSCKHBSY(1b) Serial clock • Mode other than automatic communication mode • See Fig. 6. Frequency Low level pulse width High level pulse width Output clock tSCKHA(2) • Automatic communication mode • CMOS output type selected • See Fig. 6. tSCKHBSY(2a) • Automatic communication mode • CMOS output type selected • See Fig. 6. tSCKHBSY(2b) • Mode other than automatic communication mode • See Fig. 6. Data setup time Serial input tsDI(1) SI0(P11), SB0(P11) Data hold time thDI(1) • Specified with respect to rising edge of SIOCLK. • See Fig. 6. 2.0 to 5.5 0.03 Output Input clock delay time tdD0(1) SO0(P10), SB0(P11) • (Note4-1-2) 1tCYC +0.05 2.0 to 5.5 1tCYC +0.05 μs 0.03 4 4 23 tCYC 2.0 to 5.5 6 tSCKH(2) tSCK(2) tSCKL(2) SCK0(P12) • CMOS output type selected • See Fig. 6. 4 1/2 tSCK 1/2 4 23 2.0 to 5.5 6 tCYC tSCKH(1) Symbol tSCK(1) tSCKL(1) Pin/Remarks SCK0(P12) Conditions • See Fig. 6. Specification VDD[V] min 4 2 2 typ max unit Serial output Note 4-1-1: These specifications are theoretical values. Margins must be allowed according to the actual operating conditions. Note 4-1-2: Specified with respect to the falling edge of SIOCLK. Specified as the time up to the time the output state is changed in the open drain output mode. See Fig. 6. Output clock tdDO(2) • (Note4-1-2) No.A1954-18/31 LC88F85D0A SIO1 Serial I/O Characteristics (When wakeup function is not in used) (Note 4-2-1) Parameter Period Serial clock Low level pulse width High level pulse width tSCKHBSY(3) Data setup time Serial input tsDI(2) SI0(P11), SB0(P11) Data hold time thDI(2) • Specified with respect to rising edge of SIOCLK. • See Fig. 6. 2.0 to 5.5 0.03 μs Serial output Output Input clock delay time tdD0(3) SO0(P10), SB0(P11) 2.0 to 5.5 • (Note4-2-2) 1tCYC +0.05 0.03 tSCKH(3) Symbol tSCK(3) tSCKL(3) 2.0 to 5.5 1 2 Pin/Remarks SCK0(P12) Conditions • See Fig. 6. Specification VDD[V] min 2 1 tCYC typ max unit Note 4-2-1: These specifications are theoretical values. Margins must be allowed according to the actual operating conditions. Note 4-2-2: Specified with respect to the falling edge of SIOCLK. Specified as the time up to the time the output state is changed in the open drain output mode. See Fig. 6. SMIIC0 Simple SIO Mode I/O Characteristics Parameter Period Input clock Low level pulse width High level pulse width Period Output clock Low level pulse width High level pulse width Data setup time Serial input tsDI(5) SM0DA (P23) Data hold time thDI(5) • Specified with respect to rising edge of SIOCLK • See Fig. 6. 2.0 to 5.5 0.03 Output delay time Serial output tdD0(7) SM0DA (P23) • Specified with respect to falling edge of SIOCLK • Specified as the time up to the beginning of output change . • See Fig. 6. 2.0 to 5.5 1tCYC +0.05 μs 0.03 tSCKH(8) tSCK(8) tSCKL(8) SM0CK (P22) • CMOS output type selected • See Fig. 6. 2.0 to 5.5 tSCKH(7) Symbol tSCK(7) tSCKL(7) Pin/Remarks SM0CK (P22) 2.0 to 5.5 Conditions VDD[V] • See Fig. 6. min 4 2 tCYC 2 4 1/2 tSCK 1/2 Specification typ max unit Note 4-3-1: These specifications are theoretical values. Margins must be allowed according to the actual operating conditions. Serial clock Input clock No.A1954-19/31 LC88F85D0A SMIIC0 I2C Mode I/O Characteristics Parameter Period Input clock Low level pulse width High level pulse width Period Output clock Low level pulse width High level pulse width SM0CK, SM0DA pin input spike suppression time Start-to-stop release time Input period bus tBUF SM0CK(P22) SM0DA(P23) 2.5 Tfilt • See Fig. 8. tsp SM0CK(P22) SM0DA(P23) • See Fig. 8. 2.0 to 5.5 1 Tfilt tSCLHx tSCLx tSCLLx SM0CK (P22) • Specified as the time up to the beginning of output change. 2.0 to 5.5 tSCLH Symbol tSCL tSCLL Pin/Remarks SM0CK (P22) 2.0 to 5.5 Conditions VDD[V] • See Fig. 8. min 5 2.5 Tfilt 2 10 1/2 tSCL 1/2 Specification typ max unit Clock tBUFx SM0CK(P22) SM0DA(P23) • Standard clock mode • Specified as the time up to the beginning of output change. • High-speed clock mode • Specified as the time up to the beginning of output change. 1.6 2.0 to 5.5 5.5 μs Output Start/restart condition hold Input time tHD;STA SM0CK(P22) SM0DA(P23) • When SMIIC register control bit I2CSHDS=0 • See Fig. 8. • When SMIIC register control bit I CSHDS=1 • See Fig. 8. 2 2.0 Tfilt 2.5 tHD;STAx SM0CK(P22) SM0DA(P23) • Standard clock mode • Specified as the time up to the beginning of output change. • High-speed clock mode • Specified as the time up to the beginning of output change. 2.0 to 5.5 4.1 μs 1.0 Output Restart condition Input setup time tSU;STA SM0CK(P22) SM0DA(P23) • See Fig. 8. 1.0 Tfilt tSU;STAx SM0CK(P22) SM0DA(P23) • Standard clock mode • Specified as the time up to the beginning of output change. • High-speed clock mode • Specified as the time up to the beginning of output change. 1.6 2.0 to 5.5 5.5 μs Output Continued on next page. No.A1954-20/31 LC88F85D0A Continued from preceding page. Parameter Stop condition setup time Symbol tSU;STO Pin/Remarks SM0CK(P22) SM0DA(P23) tSU;STOx SM0CK(P22) SM0DA(P23) Output • Standard clock mode • Specified as the time up to the beginning of output change. • High-speed clock mode • Specified as the time up to the beginning of output change. Input Data hold time tHD;DAT SM0CK(P22) SM0DA(P23) tHD;DATx SM0CK(P22) SM0DA(P23) tSU;DAT SM0CK(P22) SM0DA(P23) tSU;DATx SM0CK(P22) SM0DA(P23) tF SM0CK(P22) SM0DA(P23) tF SM0CK(P22) SM0DA(P23) Output • When SMIIC register control bits PSLW=1, P5V=1 • When SMIIC register control bits PSLW=1, P5V=0 • When SM0CK and SM0DA port outputs are placed in fast mode • Cb≤400pF 3.0 to 5.5 100 • Specified as the time up to the beginning of output change. • See Fig. 8. 2.0 to 5.5 2.0 to 5.5 1tSCL1.5Tfilt • Specified as the time up to the beginning of output change. • See Fig. 8. 1 Tfilt 2.0 to 5.5 1 1.5 • See Fig. 8. 0 Tfilt 1.1 2.0 to 5.5 4.9 μs Conditions VDD[V] Input • See Fig. 8. 1.0 Tfilt min Specification typ max Unit Input SM0CK, SM0DA pin fall time Output Input Data setup time Output 300 5 3 20+0.1Cb 20+0.1Cb 250 250 ns Note 4-4-1: These specifications are theoretical values. Margins must be allowed according to the actual operating conditions. Note 4-4-2: Tfilt denotes the value that is determined by the values of register SMIC0BRG, bits 7 and 6 (BRP1, BRP0) and the system clock frequency. BRP1 0 0 1 1 BRP0 0 1 0 1 Tfilt tCYC×1 tCYC×2 tCYC×3 tCYC×4 Set up (BPR1, BPR0) so that Tfilt falls within the following range: 250ns ≥ Tfilt > 140ns Note 4-4-3: Cb denotes the total capacitance (in pF) of the loads connected to each bus. Cb ≤ 400pF Note 4-4-4: The standard clock mode refers to a mode that is entered by configuring SMIC0BRG within the following ranges: 250ns ≥ Tfilt > 140ns BRDQ (bit 5) = 1 SCL frequency setting ≤ 100kHz The high-speed clock mode refers to a mode that is entered by configuring SMIC0BRG as follows: 250ns ≥ Tfilt > 140ns BRDQ (bit 5) = 0 SCL frequency setting ≤ 400kHz No.A1954-21/31 LC88F85D0A UART0 Operating Conditions at Ta = -20 to +75°C, VSS = LCDVSS0 = LCDVSS1 = 0V Parameter Transfer rate Symbol UBR0 Pin/Remarks Conditions Specification VDD[V] 2.0 to 5.5 min 4 typ max 8 unit tBGCYC U0RX(P14), U0TX(P15), U0BRG(P07) Note 4-5: tBGCYC denotes 1 period of the baudrate clock source. UART2 Operating Conditions at Ta = -20 to +75°C, VSS = LCDVSS0 = LCDVSS1 = 0V Parameter Transfer rate Symbol UBR2 Pin/Remarks U2RX(P16), U2TX(P17) Conditions Specification VDD[V] 2.0 to 5.5 min 8 typ max 4096 unit tBGCYC Note 4-6: tBGCYC denotes 1 period of the baudrate clock source. Pulse Input Conditions at Ta = -20 to +75°C, VSS = LCDVSS0 = LCDVSS1 = 0V Parameter Symbol tPIL(2) Pin/Remarks RESB Conditions Resettable. Specification VDD[V] 2.0 to 5.5 min 10 typ max unit μs AD Converter Characteristics at Ta = -20 to +75°C, VSS = LCDVSS0 = LCDVSS1 = 0V 12-bits AD Conversion Mode Parameter Resolution Absolute accuracy Conversion time Symbol NAD ETAD TCAD12 Pin/Remarks AN0(P20), AN1(P21), AN2(P22), AN3(P23), AN8(P00) to Analog input voltage range Analog port input current IAINH IAINL VAIN=VDD VAIN=VSS VAIN AN15(P07) (Note 6-1) Conversion time is calculated. Conditions Specification VDD[V] 2.9 to 5.5 2.9 to 5.5 4.5 to 5.5 2.9 to 5.5 2.9 to 5.5 2.9 to 5.5 2.9 to 5.5 -1 27 67 VSS min typ 12 ±16 209 209 VDD 1 max unit bit LSB μs V μA • Conversion time calculation method: TCAD12= ((52/(AD division ratio))+2) × tCYC 8-bits AD Conversion Mode Parameter Resolution Absolute accuracy Conversion time Symbol NAD ETAD TCAD8 Pin/Remarks AN0(P20), AN1(P21), AN2(P22), AN3(P23), AN8(P00) to Analog input voltage range Analog port input current IAINH IAINL VAIN=VDD VAIN=VSS VAIN AN15(P07) (Note 6-1) Conversion time is calculated. Conditions Specification VDD[V] 2.9 to 5.5 2.9 to 5.5 4.5 to 5.5 2.9 to 5.5 2.9 to 5.5 2.9 to 5.5 2.9 to 5.5 -1 17 42 VSS min typ 8 ±1.5 129 129 VDD 1 max unit bit LSB μs V μA • Conversion time calculation method: TCAD8= ((32/(AD division ratio))+2) × tCYC Note 6-1: The quantization error (±1/2LSB) is excluded from the absolute accuracy. Note 6-2: The conversion time refers to the interval from the time a conversion starting instruction is issued till the time the complete digital value against the analog input value is loaded in the result register. The conversion time is twice the normal value when one of the following conditions occurs: • The first AD conversion is executed in the 12-bit AD conversion mode after a system reset. • The first AD conversion is executed after the AD conversion mode is switched from 8-bit to 12-bit AD conversion mode. No.A1954-22/31 LC88F85D0A Consumption Current Characteristics at Ta = -20 to +75°C, VSS = LCDVSS0 = LCDVSS1 = 0V Parameter Normal mode consumption current (Note 7-1) IDDOP(3) IDDOP(4) IDDOP(5) IDDOP(6) IDDOP(7) IDDOP(8) IDDOP(9) IDDOP(2) Symbol IDDOP(1) Pin/ Remarks VDD Conditions • FOSC0=32.768kHz • System clock set to FOSC0 side • Internal RC oscillation stopped • FOSC1=0Hz (oscillation stopped) • Frequency division ratio set to 1/1 • Normal XT mode [No panel load] • FOSC0=32.768kHz • System clock set to FOSC0 side • Internal RC oscillation stopped • FOSC1=0Hz (oscillation stopped) • Frequency division ratio set to 1/1 • Low power XT mode [No panel load] • FmCF=10MHz ceramic oscillator • FOSC0=0Hz (oscillation stopped) • System clock set to 10MHz side • Internal RC oscillation stopped • Frequency division ratio set to 1/1 IDDOP(10) • FmCF=8MHz ceramic oscillator oscillator • FOSC0=0Hz (oscillation stopped) IDDOP(11) • System clock set to 8MHz side • Internal RC oscillation stopped • Frequency division ratio set to 1/1 IDDOP(12) • FmCF=4MHz ceramic oscillator • FOSC0=0Hz (oscillation stopped) IDDOP(13) • System clock set to 4MHz • Internal RC oscillation stopped • Frequency division ratio set to 1/2 IDDOP(14) • System clock set to internal RC side • Internal RC oscillation oscillated IDDOP(15) • FOSC0=0Hz (oscillation stopped) • FOSC1=0Hz (oscillation stopped) • Frequency division ratio set to 1/1 IDDOP(16) • FOSC1=1MHz RCR1=470kΩ • System clock set to FOSC1 side • Internal RC oscillation stopped IDDOP(17) • FOSC0=0Hz (oscillation stopped) • Frequency division ratio set to 1/1 *Ta=0 to 60°C IDDOP(18) • FOSC0=64kHz RCR0=910kΩ • System clock set to FOSC0 side • Internal RC oscillation stopped IDDOP(19) • FOSC1=0Hz (oscillation stopped) • Frequency division ratio set to 1/1 *Ta=0 to 60°C 2.0 to 3.6 62 120 2.0 to 5.5 100 187 μA 2.0 to 3.6 1.0 2.5 2.0 to 3.6 1.2 3.6 2.2 to 4.5 2.2 4.7 3.0 to 4.5 5.8 11 4.5 to 5.5 7.6 14.7 4.5 to 5.5 8.4 15.2 LCD display OFF LCD display OFF LCD display ON LCD display ON Specification VDD[V] 2.0 to 5.5 2.0 to 3.6 2.0 to 5.5 2.0 to 3.6 2.0 to 5.5 2.0 to 3.6 2.0 to 5.5 2.0 to 3.6 min typ 87 44 75 35 53 35 48 31 max 170 110 155 95 μA 100 65 92 55 unit 4.5 to 5.5 3.6 5.5 mA 2.0 to 5.5 2.2 5.6 2.0 to 5.5 1.5 2.6 Note 7-1: The consumption current value includes none of the currents that flow into the output Tr and internal pull-up resistors. Continued on next page. No.A1954-23/31 LC88F85D0A Continued from preceding page. Parameter HALT mode consumption current (Note 7-2) IDDHALT(3) IDDHALT(4) IDDHALT(5) IDDHALT(6) IDDHALT(7) IDDHALT(8) IDDHALT(9) IDDHALT(2) Symbol IDDHALT(1) Pin/ Remarks VDD HALT mode • FOSC0=32.768kHz • System clock set to FOSC0 side • Internal RC oscillation stopped • FOSC1=0Hz (oscillation stopped) • Frequency division ratio set to 1/1 • Normal XT mode [No panel load] HALT mode • FOSC0=32.768kHz • System clock set to FOSC0 side • Internal RC oscillation stopped • FOSC1=0Hz (oscillation stopped) • Frequency division ratio set to 1/1 • Low power XT mode [No panel load] HALT mode • FmCF=10MHz ceramic oscillator • FOSC0=0Hz (oscillation stopped) • System clock set to 10MHz side • Internal RC oscillation stopped • Frequency division ratio set to 1/1 IDDHALT(10) HALT mode • FmCF=8MHz ceramic oscillator • Internal RC oscillation stopped IDDHALT(11) • FOSC0=0Hz (oscillation stopped) • System clock set to 8MHz side • Internal RC oscillation stopped • Frequency division ratio set to 1/1 IDDHALT(12) HALT mode • FmCF=4MHz ceramic oscillator • FOSC0=0Hz (oscillation stopped) IDDHALT(13) • System clock set to 4MHz side • Internal RC oscillation stopped • Frequency division ratio set to 1/2 IDDHALT(14) HALT mode • System clock set to internal RC side • Internal RC oscillation oscillated IDDHALT(15) • FOSC0=0Hz (oscillation stopped) • FOSC1=0Hz (oscillation stopped) • Frequency division ratio set to 1/1 IDDHALT(16) HALT mode • FOSC1=1MHz RCR1=470kΩ • System clock set to FOSC1 side IDDHALT(17) • Internal RC oscillation stopped • FOSC0=0Hz (oscillation stopped) • Frequency division ratio set to 1/1 *Ta=0 to 60°C IDDHALT(18) HALT mode • FOSC0=64kHz RCR0=910kΩ • System clock set to FOSC0 side IDDHALT(19) • Internal RC oscillation stopped • FOSC1=0Hz (oscillation stopped) • Frequency division ratio set to 1/1 *Ta=0 to 60°C 2.0 to 3.6 10 40 2.0 to 5.5 20 60 μA 2.0 to 3.6 0.1 0.3 2.0 to 5.5 0.2 0.5 2.0 to 3.6 0.3 0.6 2.0 to 5.5 0.7 1.3 2.2 to 4.5 0.3 0.85 4.5 to 5.5 0.7 1.2 mA 3.0 to 4.5 1.2 2.1 4.5 to 5.5 1.7 2.9 4.5 to 5.5 2.0 3.4 LCD display OFF LCD display ON LCD display OFF Conditions LCD display ON Specification VDD[V] 2.0 to 5.5 2.0 to 3.6 2.0 to 5.5 2.0 to 3.6 2.0 to 5.5 2.0 to 3.6 2.0 to 5.5 2.0 to 3.6 min typ 45 16 36 7.8 15.5 12 6.5 4 max 110 50 90 51 μA 53 30 40 30 unit Note 7-2: The consumption current value includes none of the currents that flow into the output Tr and internal pull-up resistors. Continued on next page. No.A1954-24/31 LC88F85D0A Continued from preceding page. Parameter HOLD mode consumption current HOLDX mode consumption current IDDHOLD(4) IDDHOLD(5) IDDHOLD(6) Symbol IDDHOLD(1) IDDHOLD(2) IDDHOLD(3) Pin/ Remarks VDD HOLD mode • CF1=VDD or open (external clock mode) HOLDX mode • CF1=VDD or open (external clock mode) • FOSC0=32.768kHz • Normal XT mode HOLDX mode • CF1=VDD or open (external clock mode) • FOSC0=32.768kHz • Low power XT mode Conditions Specification VDD[V] 2.0 to 5.5 2.0 to 3.6 2.0 to 5.5 2.0 to 3.6 2.0 to 5.5 2.0 to 3.6 min typ 0.08 0.02 30 5 0.6 0.4 max 35 25 65 55 35 25 μA unit Note 7-3: The consumption current value includes none of the currents that flow into the output Tr and internal pull-up resistors. F-ROM Writing Characteristics at Ta = +10°C to +55°C, VSS = LCDVSS0 = LCDVSS1 = 0V Parameter Onboard writing current Writing time tFW(1) tFW(2) Symbol IDDFW(1) Pin/ Remarks VDD Conditions • Excluding power dissipation in the microcontroller block • 512-/1K-byte erase operation • 2-byte writing operation Specification VDD[V] 3.0 to 5.5 3.0 to 5.5 3.0 to 5.5 min typ max 15 30 60 unit mA ms μs Characteristics of a Sample OSC1 System Clock Oscillation Circuit Sample main system clock oscillation circuit characteristics Given below are the characteristics of a sample main system clock oscillation circuit that are measured using a SANYO-designated oscillation characteristics evaluation board and external components with circuit constant values with which the oscillator vendor confirmed normal and stable oscillation. Table 1 Characteristics of the Main System Clock Oscillation Circuit that Uses a Ceramic Oscillator Nominal Frequency Circuit Constant Vendor Name Oscillator Name C3 [pF] 10MHz 8MHz MURATA Manufacturing Co., Ltd. 4MHz CSTCR4M00G53095-R0 (15) (15) OPEN 1.5K 2.0 to 5.5 0.02 0.5 CSTCR4M00G53-R0 (15) (15) OPEN 1.5K 2.2 to 5.5 0.02 0.5 CSTCE10M0G52-R0 CSTCE8M00G52-R0 (10) (10) C4 [pF] (10) (10) Rf [Ω] OPEN OPEN Rd2 [Ω] 150 470 Operating Voltage Range [V] 2.4 to 5.5 2.4 to 5.5 Oscillation Stabilization Time Typ [ms] 0.02 0.02 max [ms] 0.5 0.5 C1 and C2 integrated type C1 and C2 integrated type C1 and C2 integrated type C1 and C2 integrated type Remarks The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized after VDD exceeds its lower limit operating voltage (see Figure 4). No.A1954-25/31 LC88F85D0A Characteristics of a Sample Subsystem Clock Oscillation Circuit Given below are the characteristics of a sample subsystem clock oscillation circuit that are measured using a SANYOdesignated oscillation characteristics evaluation board and external components with circuit constant values with which the oscillator vendor confirmed normal and stable oscillation. Table 2 Characteristics of a Sample Subsystem Clock Oscillator Circuit that uses a Crystal Oscillator Circuit Constant Nominal Frequency Normal XT mode Low power XT mode 32.768kHz 32.768kHz Vendor Name TBD TBD Oscillator Name TBD TBD C3 [pF] TBD TBD C4 [pF] TBD TBD Rf2 [Ω] TBD TBD Rd2 [Ω] TBD TBD Remarks The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized after an instruction for starting the subclock oscillator circuit is issued or the time interval that is required for the oscillation to get stabilized after the HOLD mode is released (see Figure 4). Note: The components that are involved in oscillation should be placed as close to the IC and to one another as possible because they are vulnerable to the influences of the circuit pattern. Rf1 CF1 CF2 XT1 Rf2 XT2 Rd1 Rd2 C1 CF C2 C3 X’tal C4 Figure 1 CF Oscillator Circuit Figure 2 XT Oscillator Circuit 0.5VDD Figure 3 AC Timing Measurement Point No.A1954-26/31 LC88F85D0A Power supply Reset time RESB VDD Operating VDD lower limit 0V Internal RC oscillation tmsCF CF1, CF2 tmsX’tal XT1, XT2 VMRC Operating mode Unpredictable Reset Initialization instruction executed User instruction executed Reset Time and Oscillation Stabilization Time No.A1954-27/31 LC88F85D0A HOLD release No HOLD release signal HOLD release signal valid Interrupt operation Internal RC oscillator tmsCF CF1, CF2 tmsX’tal XT1, XT2 VMRC State HOLD HALT Instruction executed HOLD Reset and Oscillation Stabilization Time Figure 4 Oscillation Stabilization Time VDD RRES RESB CRES Note: Make sure that reset is in effect when power is turned on. Determine the values of CRES and RRES so that the reset is in effect for a period of 10μs after the power gets stabilized. Figure 5 Reset Circuit No.A1954-28/31 LC88F85D0A tSCKHBSY tSCKHBSY RUN: SIOCLK: DATAIN: DI0 DI1 DI6 DI7 DI8 DIx DATAOUT: DO0 DO1 DO6 DO7 Data transfer period DO8 DOx (SIO0, 1 only) tSCK SIOCLK: tSCKL tsDI DATAIN: tdDO DATAOUT: Data transfer period tSCKH thDI (SIO0, 1 only) SIOCLK: tSCKL tsDI thDI tSCKHA DATAIN: tdDO DATAOUT: *: Remarks: DIx and DOx are the final communication bits. X = 0 to 32768 Figure 6 Serial I/O Waveforms Examples tPIL tPIH Figure 7 Pulse Input Timing Signal Waveform No.A1954-29/31 LC88F85D0A P SDA tBUF tHD;STA tR tF tHD;STA tsp S Sr P SCK tLOW tHD;DAT tHIGH tSU;DAT tSU;STA tSU;STO S: Start condition P: Stop condition Sr: Restart condition Figure 8 I2C Timing Note: The oscillation frequency of any RC oscillator using OSC1 or OSC0 varies according to the printed circuit patterns and components mounted on the board. It also varies greatly according to the shape and form of the product (chip, plastic package, etc.) and board capacitance. Consequently, the characteristics charts given below should be used merely as reference values and the resistance value be determined after evaluating them with the actual product. 10 7 5 3 Frequency - Resistor Ta=25°C, typ 1000 7 5 3 Frequency - Resistor Ta=25°C, typ Frequency - MHz 2 Frequency - kHz 0 200 400 600 800 1000 1200 2 1.0 7 5 3 2 0.1 100 7 5 3 2 10 0 200 400 600 800 1000 1200 Resistor - kΩ ILC05653 Resistor - kΩ ILC05654 Figure 9 OSC1 Oscillation Frequency vs. Resistance Characteristics Figure 10 OSC0 Oscillation Frequency vs. Resistance Characteristics No.A1954-30/31 LC88F85D0A SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein. SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO Semiconductor Co.,Ltd. products described or contained herein are controlled under any of applicable local export control laws and regulations, such products may require the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written consent of SANYO Semiconductor Co.,Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO Semiconductor Co.,Ltd. product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. Upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third party. SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's intellectual property rights which has resulted from the use of the technical information and products mentioned above. This catalog provides information as of April, 2011. Specifications and information herein are subject to change without notice. PS No.A1954-31/31