LC89201

Ordering number : EN*4974 CMOS LSI LC89201 9600-bps Facsimile Modem Preliminary Overview The LC89201 is a CMOS single-chip, synchronous, halfduplex, 9600-bps fax modem designed for use with public telephone networks. Built in are such essential features for Group III facsimile systems as modulator, demodulator, transmission filters, and V.24 interface. The LSI supports the V.29, V.27ter, V.21ch2, T.30, and T.4 telecommunications standards promulgated by the ITU-T (formerly the CCITT) for transmission at 9600, 7200, 4800, 2400 and 300 bps. Advanced signal processing provides reliable data transmissions even under adverse circuit conditions. Built-in High-level Data Link Control (HDLC) support permits the construction of Error Correction Mode (ECM) facsimile machines. • • • • • • • Built-in eye pattern generator. Adaptive differential pulse-code modulation (ADPCM). Caller ID detection. Built-in diagnostics. Energy-saving CMOS design (typ. 250 mW). Single 5 V power supply. 80-pin flat package (QIP-80E). Package Dimensions unit: mm 3174-QFP80E [LC89201] Features • Support for the following ITU-T standards: V.29 (9600, 7200 and 4800 bps), V.27ter (4800 and 2400 bps), V.21ch2 (300 bps), T.30, and T.4. • Half-duplex operation. • Group III facsimile support. • Automatic switching between high- (V.29 and V.27ter) and low-speed (V.21ch2) incoming facsimiles. • Short training (for ITU-T V.27ter only). • HDLC framing and deframing (V.29, V.27ter, and V.21ch2). • Tone generation and detection. • Dual-tone multifrequency (DTMF) generation and detection. • Call progress tone detection. • Pseudo link back tone generation. • Built-in automatic adaptive equalizer. • Built-in fixed-amplitude amplifier. — Link amplitude equalizer — Cable amplitude equalizer • Built-in transmission filters (digital filters). • Programmable transmission level adjustment. • Dynamic range for reception of 0 to –47 dBm. • Programmable reception sensitivity adjustment. • DTE interface. — Serial interface (ITU-T V.24) — Parallel interface (4 words × 8 bits, with built-in FIFO) • Programmable interrupt generator. SANYO: QIP80E SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN 92995HA (OT) No. 4974-1/8 LC89201 System Block Diagram No. 4974-2/8 LC89201 Internal Block Diagram No. 4974-3/8 LC89201 Pin Assignment Pin Functions 1. Power Supply, Clock and Test Pins Pin No. 14 31 54 63 73 8 13 24 35 53 64 74 38 51 37 52 1 7 50 9 10 80 56 55 Symbol I/O Function DVDD P Digital power supply DGND P Digital ground AVDD AGND PVDD PGND VREF X2 X1 CLKOUT TESTMB CKSB P P P P P I O O I I Analog power supply Analog ground Frequency multiplier PLL power supply Frequency multiplier PLL ground Reference power supply. This must be half AVDD. System clock input (29.4912 MHz) Oscillator amplifier output Output clock, one-quarter the frequency of the internal master clock (9.216 MHz). Test pin. Connect to DVDD. Test pin. Connect to DVDD. No. 4974-4/8 LC89201 2. DTE Interface Pins Pin No. 29 28 27 26 25 23 22 21 20 19 18 17 16 30 32 33 34 15 Symbol D0 D1 D2 D3 D4 D5 D6 D7 A0 A1 A2 A3 A4 CSB READB WRITEB IREQB RESETB I/O Function B Data bus to host CPU I Address bus to host CPU I I I O I Chip select signal Interface memory read signal Interface memory write signal Interrupt request to host CPU System reset signal 3. Eye Pattern Interface Pins Pin No. 67 68 66 65 Symbol EYECLK EYESYNC EYEX EYEY I/O O O O Function Timing clock for generating eye pattern data. This may be used as the shift clock for an external shift register. Eye pattern synchronization signal Eye pattern data serial outputs (8 bits, MSB first) 4. V.24 (RS-232C) Interface Pins Pin No. 57 59 58 61 60 62 Symbol RTSB CTSB RLSDB TXD RXD DCLK I/O I O O I O O Function Request to send signal. The low level at this pin starts transmission; the high level suspends it. Clear to send signal. The low level at this pin signals the availability of data for transmission; the high level indicates that the data is invalid. Received line signal data signal. The low level at this pin gives the timing for transferring the data received to the terminal. Transmit data input Receive data output Transmission data clock output 5. Analog Signal Pins Pin No. 39 44 43 40 41 42 47 46 45 49 48 Symbol TXA RXA AUXIN OPA2P OPA2M OPA2O OPA1P OPA1M OPA1O PGCI PGCO I/O O I I I I O I I O I O Reception gain adjustment circuit input. (For details, seecircuit diagram.) Reception gain adjustment circuit output. Reception buffer input/output pins (For details, see circuit diagram.) Transmission buffer input/output pins. (For details, see circuit diagram.) Transmitter analog output Receiver analog input Auxiliary analog input Function No. 4974-5/8 LC89201 6. System signal pins Pin No. 11 78 77 6 3 4 5 2 36 Symbol MC HOLDB HOLDAB PRTSB PO VCOI VCOO RIN STOPB I/O I I O I O I O I I Program mode control signal. Connect to DVDD. System hold signal. Connect to DVDD. System hold confirmation signal. Frequency multiplier PLL reset input. (For details, see circuit diagram.) Phase comparator output. (For details, see circuit diagram.) Voltage-controlled oscillator input. (For details, seecircuit diagram.) Voltage-controlled oscillator output Voltage-controlled oscillator adjustment input. (For details, see circuit diagram.) Oscillator amplifier STOP input Function Note: All other pins are to be left unconnected. Specifications Absolute Maximum Ratings at DGND, AGND, PGND = 0 V Parameter Symbol DVDD max Maximum supply voltage AVDD max PVDD max I/O voltages Allowable power dissipation Operating temperature Storage temperature Soldering heat resistance VI VO Pd max Topr Tstg Hand soldering (3 seconds) Reflow (10 seconds) Ta = 25°C Ta = 25°C Ta = 25°C Ta = 25°C Ta ≤ 70°C Conditions Ratings –0.3 to +7.0 –0.3 to +7.0 –0.3 to +7.0 –0.3 to VDD + 0.3 400 –30 to +70 –55 to +125 350 235 Unit V V V V mW °C °C °C °C Allowable Operating Ranges at Ta = –30 to +70°C, DGND, AGND, PGND = 0 V Parameter Symbol DVDD Supply voltage AVDD PVDD Input voltage VIN Conditions min 4.5 4.5 4.5 0 typ 5.0 5.0 5.0 max 5.5 5.5 5.5 VDD Unit V V V V No. 4974-6/8 LC89201 Electrical Characteristics at Ta = –30 to +70°C, DGND, AGND, PGND = 0 V, DVDD, AVDD, PVDD = 4.5 to 5.5 V Parameter Input high level voltage Input low level voltage Symbol VIH VIL Conditions TTL levels: RESETB, PRSTB, STOPB, A0 to A4, D0 to D7, CSB, READB, WRITEB, RTSB, TXD, HOLDB, MC, TESTMB, CKSB VIN = DGND, AGND, PGND, DVDD, AVDD, PVDD: RESETB, PRSTB, STOPB, A0 to A4, D0 to D7, CSB, READB, WRITEB, RTSB, TXD, HOLDB, MC, TESTMB, CKSB IOH = –3 mA, TTL levels: WEB, MENB, CLKOUT, HOLDAB, PA0 to PA5, D0 to D7, IREQB, CTSB, RLSDB, RXD, DCLK, VCOO, EYEX, EYEY, EYECLK, EYESYNC IOL = 3 mA, TTL levels: WEB, MENB, CLKOUT, HOLDAB, PA0 to PA5, D0 to D7, IREQB, CTSB, RLSDB, RXD, DCLK, VCOO, EYEX, EYEY, EYECLK, EYESYNC For high-impedance output: D0 to D7 X2, X1 VREF VREF RIN, VCOI, OPA1M, OPA1P, RAX, OPA2M, OPA2P, PGCI TXA, PGCO, OPA1O, OPA2O TXA, PGCO, OPA1O, OPA2O VDD = 5.5 V VDD = 5.0 V 50 1 VDD*0.2 VDD*0.2 VDD*0.8 VDD*0.8 7 80 –10 +10 29.4912 VDD/2 min 2.2 0.8 typ max Unit V V Input leak current IL –1 +1 µA Output high level voltage VOH 2.4 V Output low level voltage VOL IOZ fOSC VREF RREF VIA VOA RO IDD 0.4 V Output leak current Oscillator frequency VREF input voltage VREF impedance Input voltage range Output voltage range Output impedance Current drain µA MHz V MΩ V V kΩ mA mA AC Characteristics 1. DTE interface timing Read cycle timing No. 4974-7/8 LC89201 Parameter Address stabilization time (relative to READB signal) Chip select stabilization time (relative to READB signal) Data propagation delay Data float propagation delay Address hold time (relative to READB signal) Address stabilization time (relative to WRITEB signal) Chip select stabilization time (relative to WRITEB signal) Data setup time Data hold time Address hold time (relative to WRITEB signal) Symbol TAR TCR TRD TDF TRA TAW TCW TDW TWD TWA 10 10 15 0 20 5 10 Conditions min 15 0 30 typ max Unit ns ns ns ns ns ns ns ns ns ns 2. Reset timing Parameter PRTSB pulse width PRTSB propagation delay relative to RESETB RESETB pulse width Symbol T1 T2 T3 Conditions min 500 5 500 typ max Unit µs ms ns s No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. s Anyone purchasing any products described or contained herein for an above-mentioned use shall: Œ Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use:  Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. s Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of September, 1995. Specifications and information herein are subject to change without notice. PS No. 4974-8/8 Caption P.2 1. 2. 29.4912-MHz crystal oscillator or crystal resonator 3. 4. Power supply 5. 6. Eye pattern generator 7. Oscilloscope Auxiliary analog input Telephone line Host CPU P.7/8 A4 to A0 D7 to D0 A4 to A0 D7 to D0 8. Power-on reset circuit P.3 1. 2. 3. 4. Eye pattern generator 5. 6. HDLC block Analog front end Interface memory Timing generator V.24 interface New P2/8 2. 29.4912-MHz crystal oscillator or crystal resonator 8. Power-on reset circuit D0 to D7 A0 to A4 P3/8 D7 to D0 A4 to A0