LC895199K

Ordering number : ENN6238 CMOS IC LC895199K 32× CD-ROM Decoder with ATAPI (IDE) Interface Overview The LC895199K is a CD-ROM decoder IC that provides subcode read functions and an ATAPI interface integrated on the same chip. Functions • • • • CD-ROM ECC function Subcode read function ATA-PI (IDE) I/F (register block, etc.) CAV audio function • Built-in batch transfer function (function for sending CD main channel, C2 flag, subcode, etc. at one time) • Built-in multi-block transfer function (function for automatically sending several blocks at one time) • Built-in CAV audio function • Built-in intelligent functions (auto buffering, auto decoding, CD-R support, etc.) • Built-in subcode P to W buffering function (NO-ECC) and CD-TEXT support • Package: SQFP-144 Features • Built-in ATAPI (IDE) I/F • 32× speed supported: Using EDO-DRAM (×16, 50 ns) 16.6 Mbytes/s (with IORDY) Operating frequency: 33.8688 MHz • 32× speed supported: Using EDO-DRAM (×16, 45 ns) 16.6 Mbytes/s (without IORDY) Operating frequency: 33.8688 MHz • 24× speed supported: Using EDO-DRAM (×16, 50 ns) 16.6 Mbytes/s (without IORDY) Operating frequency: 33.8688 MHz • 1 Mbits to 4 Mbits of buffer RAM connectable in case of DRAM • CD main channel, C2 flag, and subcode areas in buffer RAM can be freely set by user Package Dimensions unit: mm 3214-SQFP144 [LC895199K] 22.0 20.0 1.25 109 0.5 108 1.25 73 72 0.145 22.0 20.0 0.5 1.25 1.6max 144 37 1 0.20 36 0.1 1.4 1.25 0.5 0.5 SANYO: SQFP144 Any and all SANYO products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft’s control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO representative nearest you before using any SANYO products described or contained herein in such applications. SANYO assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO products described or contained herein. SANYO Electric Co.,Ltd. Semiconductor Company TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN 21000TH (OT)/30899TH (OT) No. 6238-1/12 LC895199K Changes from the LC895199 Items changed from the LC895199-MK2 • Revision 4. • The DVD-ROM and DVD-RAM interface functions have been removed. • The buffer circuits for the DRAM pins (RAS, CAS0, CAS1, OE, WE, and A0 to A8) have been changed from 8 mA sink to 4 mA sink. • The buffer circuits for the D/A converter output pins (DSDATA, DLRCK, DBCK) have been changed from 8 mA sink to 4 mA sink. • The amount of external DRAM supported has been changed from 16M to 4M. • The MCK3 output has been changed to a 1/1, 1/2, stop output. • Settings have been added for cases when the PLL circuit is not used. (W register R46 bit 7 (set to 1) and C register R1 (set to 40h)) Specifications Absolute Maximum Ratings at VSS = 0 V Parameter Maximum supply voltage Symbol VDD5 max VDD3 max VI15, VO5 VI13, VO3 Pd max Topr Tstg 10 s II, IO Ta = 25°C Ta = 25°C Ta = 25°C Ta = 25°C Ta ≤ 70°C Conditions Ratings –0.3 to +6.0 –0.3 to +4.6 –0.3 to VDD5 + 0.3 –0.3 to VDD3 + 0.3 550 –30 to +70 –55 to +125 235 ±20 Unit V V V V mW °C °C °C mA Input/output voltage Allowable power dissipation Operating temperature Storage temperature Soldering temperature (pin part only) Input/output power Note: * Per 1 input/output reference cell * Allowable Operating Range at Ta = –30 to +70°C, VSS = 0 V IO Cell 5.0 V Supply Voltage Parameter Supply voltage Input voltage range Symbol VDD VIN Conditions Ratings min 4.5 0 typ 5.0 max 5.5 VDD Unit V V Internal Cell 3.3 V Supply Voltage Parameter Supply voltage Input voltage range Symbol VDD VIN Conditions Ratings min 3.0 0 typ 3.3 max 3.6 VDD Unit V V No. 6238-2/12 LC895199K DC Characteristics at Ta = –30 to +70°C, VSS = 0 V, VDD = 4.5 to 5.5 V Parameter Input high-level voltage Input low-level voltage Input high-level voltage Input low-level voltage Input high-level voltage Input low-level voltage Output high-level voltage Output low-level voltage Output high-level voltage Output low-level voltage Output high-level voltage Output low-level voltage Output high-level voltage Output low-level voltage Output high-level voltage Output low-level voltage Output low-level voltage Output low-level voltage Input leakage current Output leakage current Pull-up resistance Pull-up resistance Symbol VIH VIL VIH VIL VIH VIL VOH VOL VOH VOL VOH VOL VOH VOL VOH VOL VOL VOL IIL IOZ RUP RUP ZDMACK *2 TTL levels with pull-down resistor TTL levels Schmitt IOH1 = –4 mA IOL1 = 4 mA IOH1 = –8 mA IOL1 = 8 mA IOH1 = –12 mA IOL1 = 12 mA IOH1 = –12 mA IOL1 = 12 mA IOH1 = –4 mA IOL1 = 24 mA IOL1 = 24 mA IOL1 = 8 mA VI = VSS, VDD During high-impedance output Conditions TTL levels Applicable pins *1 Ratings min 2.2 — 2.2 — 2.4 — VDD – 2.1 — VDD – 2.1 — VDD – 2.1 — VDD – 2.1 — VDD – 2.1 — — — –10 –10 40 20 80 40 typ — — — — — — — — — — — — — — — — — — max — 0.8 — 0.8 — 0.8 — 0.4 — 0.4 — 0.4 — 0.4 — 0.4 0.4 0.4 +10 +10 160 80 Unit V V V V V V V V V V V V V V V V V V µA µA kΩ kΩ (1) (10) (2), (3), (11) (4) (10), (12) (5) (5) (8), (11) (9) (6), (7) (1), (2), (3), (11) (6), (8), (9), (11) (10) (7) Notes:1. The applicable pin sets are as follows. 2. When ZDMACK is reset, internal pull-up resistor is OFF. When Config-Reg-R46 (PULON)-bit 0 (ZDMACK) = 1, pull-up resistor becomes ON. INPUT (1) ATPINSEL, CSCTRL, SUA0 to SUA6, BCK, C2PO, LRCK, SDATA, SBS0, SCOR, WFCK, TEST0 to TEST1 (2) ZRESET, ZCS, ZRD, ZWR, CSEL (3) DA0 to DA2, ZCS1FX, ZCS3FX, ZDIOR, ZDIOW, ZDMACK, ZHRST OUTPUT (4) RA0 to RA8, ZRAS0, ZCAS0 to ZCAS1, ZUWE, ZLWE, ZOE (5) MCK, MCK3 (6) ZRSTCPU (7) ZINT, ZINT1, ZSWAIT (8) DMARQ, HINTRQ (9) IORDY, ZIOCS16 INOUT (10) D0 to D7, IO0 to IO15, HDB0 to HDB7 (11) DD0 to DD15, ZDASP, ZPDIAG (12) EXCK Note: Pins XTAL and XTALCK are not included in the DC characteristics. No. 6238-3/12 LC895199K Recommended Oscillator Circuit LC895199K XTALCK PN52 R1 XTAL PN53 R2 C1 C2 A12521 R1 = 1 MΩ R2 = 47 Ω C1 = 0 C2 = 47 pF Ceramic oscillator frequency = 33.8688 MHz. The 33.8688 MHz frequency in the recommended circuit is the third harmonic. Since the exact values of these components will vary depending on characteristics of the printed circuit board used and other factors, consult the manufacturer of the oscillator element when designing the oscillator circuit. External Circuits for the On-Chip PLL Version (LC895199) LC895199K PLL PN69 3.3V R3 PN70 R4 C3 Analog VSS A12522 PN71 R5 R3 = 5.1 kΩ, R4 = 200 Ω, R5 = 10 kΩ, C3 = 0.1 µF The analog VDD and VSS must be made completely independent of the logic system power supply. In particular, they must not be affected by fluctuations in the logic system power supply. No. 6238-4/12 LC895199K Block Diagram LC895199K Data bus[0:7] *1 EXCK RAM Data bus[0:15] Address bus[0:17] Sub-code I/F 10byte FIFO for Sub Q Address generator CAV-Audio contorol CD-DSP Address generator *10 DAC *2 CD-DSP I/F & SYNC Detector De-scramble & Buffering Address generator ECC & EDC ZRESET ZRSTCPU HOST *3 *4 *5 ZINT0 ZINT1 *6 *7 ZSWAIT Each Block XTALCK XTAL MCK3 MCK *11 A12523 Reset Controller Address generator Each Block Bus control signal External Bus Arbiter & DRAM controller *8 *9 Buffer IDE I/F Based HISIDE Each Block Register R0-R127 decoder **1 DRAM Data output input I/F Address generator Micro controller Microcontroller RAM access Address generator Clock generator & PLL *1 *2 *3 *4 *5 *6 *7 *8 *9 *10 *11 **1 WFCK, SBSO, SCOR BCK, SDATA, LRCK, C2PO DD0 to DD15, ZDASP, ZPDIAG ZCS1FX, ZCS3FX, DA0 to DA2, ZDIOR, ZDIOW, ZDMACK, CSEL DMARQ, HINTRQ, ZIOCS16, IORDY, ZHRST ZRD, ZWR, SUA0 to SUA6, ZCS, CSCTRL D0 to D7 IO0 to IO15 RA0 to RA8, ZRAS0, ZCAS0, ZCAS1, ZOE, ZUWE, ZLWE DBCK, DLRCK, DSDATA IOP0 to IOP7 HISIDE(WD25C32) is made by WESTERN DIGITAL No. 6238-5/12 LC895199K Pin Functions LC895199K Pin Functions (When pin 103 (ATPINSEL) is low) Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 TEST0 XTALCK VSS0 IOP0 IOP1 IOP2 IOP3 IOP4 IOP5 IOP6 IOP7 Pin name VSS0 ZRAS0 ZCAS0 ZCAS1 VSS0 ZOE ZUWE ZLWE VSS0 RA0 RA1 RA2 RA3 RA4 RA5 RA6 RA7 VDD0 VSS0 RA8 IO0 IO1 IO2 IO3 IO4 IO5 VSS0 IO6 IO7 IO8 IO9 IO10 IO11 IO12 IO13 VSS0 VDD1 IO14 IO15 Type P O O O P O O O P O O O O O O O O P P O B B B B B B P B B B B B B B B P P B B NC P B B B B B B B B NC I I Test pin. This pin must be connected to VSS in normal operation. Crystal oscillator circuit input General-purpose input and output ports 3.3 V Data buffer DRAM data input and output These pins have built-in pull-up resistors. Data buffer DRAM data input and output These pins have built-in pull-up resistors. Data buffer DRAM data input and output These pins have built-in pull-up resistors. Data buffer DRAM address signal output 5.0 V Data buffer DRAM address signal outputs Buffer DRAM output enable Buffer DRAM upper write enable Buffer DRAM lower write enable Buffer DRAM RAS signal output Buffer DRAM CAS signal output 0 (Normally held at 0 (low).) Buffer DRAM CAS signal output 1 Type I O INPUT OUTPUT B P Pin functions BIDIRECTION POWER NC NOT CONNECT Continued on next page. No. 6238-6/12 LC895199K Continued from preceding page. Pin No. 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 Pin XTAL VDD0 VSS0 MCK TEST1 DSDATA DLRCK DBCK C2PO SDATA BCK LRCK EXCK WFCK SBSO SCOR PLL1 PLL2 PLL3 VSS0 VDD1 ZRESET MCK3 CSCTRL ZRD ZWR ZCS SUA0 SUA1 SUA2 SUA3 SUA4 SUA5 SUA6 D0 D1 D2 VDD0 VSS0 D3 D4 D5 D6 D7 ZINT0 ZINT1 ZSWAIT ZRSTCPU CSEL ZHRST ATPINSEL ZDASP ZCS3FX ZCS1FX DA2 P P I O I I I I I I I I I I I B B B P P B B B B B O O O O I I I B I I I Interrupt request signal output to the microcontroller Wait signal output to the microcontroller CPU reset signal ATAPI control signals ATAPI pin layout selection. (This pin must be connected to VSS0.) Microcontroller data signals These pins have built-in pull-up resistors. Microcontroller data signals These pins have built-in pull-up resistors. 5.0 V Microcontroller register selection signals (This is an analog VSS pin in the LC895199 built-in PLL version.) 3.3 V (This is an analog VDD pin in the LC895199 built-in PLL version.) IC reset XTALCLK 1/1, 1/5, 2/5, 1/512, and stop output Microcontroller CS pin active low/active high selection Microcontroller data read signal input Microcontroller data write signal input Register chip select input from the microcontroller PLL circuit connections I/O O P P O I O O O I I I I O I I I Subcode input and output CD DSP interface D/A converter outputs XTALCLK 1/1, 1/2, and stop output Test pin. This pin must be connected to VSS in normal operation. Crystal oscillator circuit output 5.0 V Function Continued on next page. No. 6238-7/12 LC895199K Continued from preceding page. Pin No. 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 Pin VSS1 VDD1 DA0 ZPDIAG DA1 ZIOCS16 HINTRQ ZDMACK VSS1 IORDY ZDIOR ZDIOW DMARQ VSS1 DD15 DD0 DD14 DD1 VDD0 VSS1 DD13 DD2 DD12 DD3 VSS1 DD11 DD4 DD10 VSS1 VDD0 DD5 DD9 DD6 VSS1 DD8 DD7 VDD1 I/O P P I B I O O I P O I I O P B B B B P P B B B B P B B B P P B B B P B B P ATAPI data bus 3.3 V ATAPI data bus 5.0 V ATAPI data bus ATAPI data bus 5.0 V ATAPI data bus ATAPI control signals ATAPI control signals 3.3 V Function Unused (“NC”) pins must be left open. Pins whose name begin with Z operate with inverted (negative) logic. VSS0 is the logic system ground and VSS1 is the IDE interface driver ground. Applications must supply 5.0 V for VDD0 and 3.3 V for VDD1. No. 6238-8/12 LC895199K Pin Functions LC895199K Pin Functions (When pin 103 (ATPINSEL) is high) Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 TEST0 XTALCK VSS0 IOP0 IOP1 IOP2 IOP3 IOP4 IOP5 IOP6 IOP7 Pin name VSS0 ZRAS0 ZCAS0 ZCAS1 VSS0 ZOE ZUWE ZLWE VSS0 RA0 RA1 RA2 RA3 RA4 RA5 RA6 RA7 VDD0 VSS0 RA8 IO0 IO1 IO2 IO3 IO4 IO5 VSS0 IO6 IO7 IO8 IO9 IO10 IO11 IO12 IO13 VSS0 VDD1 IO14 IO15 Type P O O O P O O O P O O O O O O O O P P O B B B B B B P B B B B B B B B P P B B NC P B B B B B B B B NC I I Test pin. This pin must be connected to VSS in normal operation. Crystal oscillator circuit input General-purpose input and output ports 3.3 V Data buffer DRAM data input and output These pins have built-in pull-up resistors. Data buffer DRAM data input and output These pins have built-in pull-up resistors. Data buffer DRAM data input and output These pins have built-in pull-up resistors. Data buffer DRAM address signal output 5.0 V Data buffer DRAM address signal outputs Buffer DRAM output enable Buffer DRAM upper write enable Buffer DRAM lower write enable Buffer DRAM RAS signal output Buffer DRAM CAS signal output 0 (Normally held fixed at 0 (low).) Buffer DRAM CAS signal output 1 Type I O INPUT OUTPUT B P Pin functions BIDIRECTION POWER NC NOT CONNECT Continued on next page. No. 6238-9/12 LC895199K Continued from preceding page. Pin No. 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 Pin XTAL VDD VSS0 MCK TEST1 DSDATA DLRCK DBCK C2PO SDATA BCK LRCK EXCK WFCK SBSO SCOR PLL1 PLL2 PLL3 VSS0 VDD1 ZRESET MCK3 CSCTRL ZRD ZWR ZCS SUA0 SUA1 SUA2 SUA3 SUA4 SUA5 SUA6 D0 D1 D2 VDD0 VSS0 D3 D4 D5 D6 D7 ZINT0 ZINT1 ZSWAIT ZRSTCPU CSEL DD7 ATPINSEL DD8 DD6 DD9 DD5 P P I O I I I I I I I I I I I B B B P P B B B B B O O O O I B I B B B B ATAPI data bus Interrupt request signal output to the microcontroller Wait signal output to the microcontroller CPU reset signal ATAPI control signal ATAPI data bus ATAPI pin layout selection. (This pin must be connected to VDD0.) Microcontroller data signals These pins have built-in pull-up resistors. Microcontroller data signals These pins have built-in pull-up resistors. 5.0 V Microcontroller register selection signals (This is an analog VSS pin in the LC895199 built-in PLL version.) 3.3 V (This is an analog VDD pin in the LC895199 built-in PLL version.) IC reset XTALCLK 1/1, 1/5, 2/5, 1/512, and stop output Microcontroller CS pin active low/active high selection Microcontroller data read signal input Microcontroller data write signal input Register chip select input from the microcontroller PLL circuit connections I/O O P P O I O O O I I I I O I I I Subcode input and output CD DSP interface D/A converter outputs XTALCLK 1/1, 1/2, and stop output Test pin. This pin must be connected to VSS in normal operation. Crystal oscillator circuit output 5.0 V Function Continued on next page. No. 6238-10/12 LC895199K Continued from preceding page. Pin No. 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 Pin VSS1 VDD1 DD10 DD4 DD11 DD3 DD12 DD2 VSS1 DD13 DD1 DD14 DD0 VSS1 DD15 DMARQ ZDIOW ZDIOR VDD0 VSS1 IORDY ZDMACK HINTRQ ZIOCS16 VSS1 DA1 ZPDIAG DA0 VSS1 VDD0 DA2 ZCS1FX ZCS3FX VSS1 ZDASP ZHRST VDD1 I/O P P B B B B B B P B B B B P B O I I P P O I O O P I B I P P I I I P B I P 3.3 V ATAPI control signal 5.0 V ATAPI control signal ATAPI control signal 5.0 V ATAPI control signal ATAPI data bus ATAPI data bus ATAPI data bus 3.3 V Function Unused (“NC”) pins must be left open. Pins whose name begin with Z operate with inverted (negative) logic. VSS0 is the logic system ground and VSS1 is the IDE interface driver ground. Applications must supply 5.0 V for VDD0 and 3.3 V for VDD1. No. 6238-11/12 LC895199K Specifications of any and all SANYO products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer’s products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer’s products or equipment. SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO products (including technical data, services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of SANYO Electric Co., Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the “Delivery Specification” for the SANYO product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of February, 2000. Specifications and information herein are subject to change without notice. PS No. 6238-12/12