LC89585

Ordering number : EN 5160A CMOS LSI LC89585 CD Encoder LSI for CD-R Systems Overview The LC89585 is an LSI that implements the digital processing required for CD-R recording in conformance with the orange book specifications. The LC89585 adds subcode data to record data processed by an A/D converter and the built-in DIR (digital audio interface receiver), FS decoder, and CD decoder circuits, and converts that data to CIRC (cross-interleave reed-solomon code) data. The LC89585 then performs EFM (eight-tofourteen modulation encoding) conversion in real time. Package Dimensions unit: mm 3151-QFP100E [LC89585] Features • A/D converter clock generation • Built-in DIR (conforming to the IEC958 standard) and DIT (Digital audio interface transmitter) • Built-in fader and muting circuits • On-chip buffer RAM for encoder processing • Automatic linking position processing function • CCB CPU interface SANYO: QIP100E Specifications Absolute Maximum Ratings at VSS = 0 V Parameter Maximum supply voltage I/O voltages Operating temperature Storage temperature Soldering temperature resistance Symbol VDD max VI, VO Topr Tstg 10 seconds (pins only) Ta = 25°C Ta = 25°C Conditions Ratings –0.3 to +7.0 –0.3 to VDD + 0.3 –30 to +70 –55 to +125 260 Unit V V °C °C °C Allowable Operating Ranges at Ta = –30 to +70°C, VSS = 0 V Parameter Supply voltage Input voltage Symbol VDD VIN Conditions min 4.5 0 typ — — max 5.5 VDD Unit V V SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-0005 JAPAN 13098HA (OT)/71595HA (OT) No. 5160-1/6 LC89585 DC Electrical Characteristics at Ta = –30 to +70°C, VDD = 4.5 to 5.5 V, VSS = 0 V Parameter High-level input voltage Low-level input voltage High-level input voltage Low-level input voltage High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage High-level output voltage Low-level output voltage Symbol VIH1 VIL1 VIH2 VIL2 VIH3 VIL3 VOH1 VOL1 VOH2 VOL2 *1 *1 *2 *2 *3 *3 IOH = –1 µA, *4 IOL = +1 µA, *4 IOH = –20 µA, *5 IOL = +20 µA, *5 Conditions min 2.2 –0.3 0.7 VDD –0.3 0.8 VDD –0.3 VDD – 0.05 — VDD – 0.05 — typ — — — — — — — — — — max VDD + 0.3 +0.8 VDD + 0.3 0.3 VDD VDD + 0.3 0.2 VDD — VSS + 0.05 — VSS + 0.05 Unit V V V V V V V V V V Note: 1. The DIN1 to DIN4, ENCVCOIN, JITVCOIN, A0 to A9, DQ1 to DQ4, RAS, CAS, OE and WR input pins. 2. Input pins other than DIN1 to DIN4, ENCVCOIN, JITVCOIN, A0 to A9, DQ1 to DQ4, RAS, CAS, OE, WR, RESET, CCB, CE, CL, DI, DIRRC1 and XTALIN. 3. The RESET, CCB, CE, CL, DI, DIRRC1 and XTALIN input pins. 4. Output pins other than JITLPFO and ENCLPFO. 5. The JITLPFO and ENCLPFO output pins. Pin Assignment Top view No. 5160-2/6 LC89585 System Block Diagram No. 5160-3/6 LC89585 Pin Functions Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Symbol DIN1 DIN2 DIN3 DIN4 DIRRC1 DIRRC2 AVDD DIRRS AGND DIRVCO DIRLPF VSS VDD DIRCK DIRBCK DIRLRCK DIRDATA DIRWDCK DIRU DIRERR DRAMSW CJSDATA CJSBCK CJSLRCK JITVCOIN JITLPFO JITLPFI JITPCO JITERR DACDATA DACBCK DACLRCK ADCDATA ADCCLK ADCBCK ADCLRCK ADCSTBY XTALIN XTALOUT VSS VDD DACCKOUT ENCCKOUT CDDATA CDBCK CDLRCK CDTX DITOUT TP6 RESET I/O I I I I I O — I — I O — — O O O O O O O O I I I I O I O O O O O I O O O O I O — — O O I I I I O I I Optical module data input Optical module data input Optical module data input Optical module data input RC oscillator input RC oscillator output Analog system power supply VCO oscillation band adjustment input Analog system ground VCO free-running frequency setting input PLL low-pass filter connection Ground +5 V power supply DIR system clock output DIR bit clock output DIR L/R clock output DIR demodulated data output DIR word clock output U-bit output Data error and lock state monitor output External DRAM capacity setting output Clock jitter sub-laser data input Clock jitter sub-laser bit clock input Clock jitter sub-laser L/R clock input VCO input Low-pass filter output Low-pass filter input Phase comparator output Lock state monitor output D/A converter data output D/A converter bit clock output D/A converter L/R clock output A/D converter record data input A/D converter clock output A/D converter bit clock output A/D converter L/R clock output A/D converter standby signal output System clock input System clock output Ground +5 V power supply D/A converter system clock output CD decoder system clock output CD decoder data input CD decoder bit clock input CD decoder L/R clock input Signal input from the CD decoder output Biphase modulation output Test pin System reset input Function Continued on next page. No. 5160-4/6 LC89585 Continued from preceding page. Pin No. 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Symbol TP7 CAS OE A8 A7 A6 A5 A4 A3 A2 VDD VSS A1 A0 A9 RAS WR DQ2 DQ1 DQ4 DQ3 TP0 TP1 TP2 TP3 ENCVCOIN ENCLPFO ENCLPFI ENCPCO ENCERR TP4 TP5 RFDET RECEN TP8 DET4T DET3T EFM VDD VSS ENCCK EXTACK EXTSYNC ATIPSYNC SUBSYNC CCB CE CL DI DO I/O I O O O O O O O O O — — O O O O O I/O I/O I/O I/O I I I O I O I O O O I I I O O O O — — O O I I O I I I I O Encoder circuit clock input Low-pass filter output Low-pass filter input Phase comparator output Lock state monitor output Test pin RF signal input Record enable signal input Test pin 4T detection signal output 3T detection signal output EFM signal output +5 V power supply Ground Encoder clock output ATIP synchronization reporting signal output ATIP synchronization enable signal input ATIP synchronization signal input Subcode synchronization signal output CPU interface type switching signal input CPU interface chip enable signal input CPU interface data transfer clock input CPU interface data input CPU interface data output Test pin DRAM data I/O DRAM row address strobe signal output DRAM read/write signal output DRAM address outputs +5 V power supply Ground DRAM address outputs Test pin DRAM column address strobe signal output DRAM output enable signal output Function No. 5160-5/6 LC89585 s No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. s Anyone purchasing any products described or contained herein for an above-mentioned use shall: Œ Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use:  Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. s Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of January, 1998. Specifications and information herein are subject to change without notice. PS No. 5160-6/6