LE24CB1283

Ordering number : ENA1887 CMOS IC LE24CB1283 Overview Two Wire Serial Interface EEPROM (128K EEPROM) The LE24CB1283 (hereinafter referred to as ‘this device’) is two-wire serial interface EEPROM (Electrically Erasable and Programmable ROM). This device realizes high speed and a high level reliability by SANYO’s high performance CMOS EEPROM technology. This device is compatible with I2C memory protocol, therefore it is best suited for application that requires re-writable nonvolatile parameter memory. Functions • Capacity : 128K bits (16k × 8 bits) • Single supply voltage : 2.7V to 5.5V. • Interface : Two wire serial interface (I2C Bus*) • Operating clock frequency : 400kHz • Low power consumption : Standby: 2μA (max), Active(read): 1mA (max.) • Automatic page write mode: 64 bytes • Read mode : Sequential read and random read • Erase/Write cycles : 106 cycles • Data Retention : 20 years • High reliability : Adopts SANYO’s proprietary symmetric memory array configuration (USP6947325) Noise filters connected to SCL and SDA pins Incorporates a feature to prohibit write operations under low voltage conditions. • Package : LE24CB1283M MFP8 (225mil) * : I2C Bus is a trademark of Philips Corporation. * This product is licensed from Silicon Storage Technology, Inc. (USA), and manufactured and sold by SANYO Semiconductor Co., Ltd. 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To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer' s products or equipment. 10511 SY 20100330-S00005 No.1887-1/12 LE24CB1283 Package Dimensions unit:mm (typ) 3032D 5.0 8 5 [LE24CB1283M] 4.4 6.4 1 (0.65) 1.27 4 0.35 0.15 SANYO : MFP8(225mil) Pin Assignment S0 S1 S2 GND 1 2 3 4 8 7 6 5 VDD WP SCL SDA 0.1 (1.5) 1.7max 0.63 Pin Descriptions PIN.1 PIN.2 PIN.3 PIN.4 PIN.5 PIN.6 PIN.7 PIN.8 S0 S1 S2 GND SDA SCL WP VDD Slave Device Address 0 Slave Device Address 1 Slave Device Address 2 Ground Serial data input/output Serial clock input Write protect Power supply Block Diagram WP Input Buffer Condition detector Write controller Serial controller High voltage generator S0 S1 S2 SCL Address generator X decoder EEPROM Array I/O Buffer Y decoder & Sense Amp Serial-Parallel converter SDA No.1887-2/12 LE24CB1283 Specifications Absolute Maximum Ratings Parameter Supply voltage DC input voltage Over-shoot voltage Storage temperature Tstg Below 20ns Symbol Conditions Ratings -0.5 to +6.5 -0.5 to +5.5 -1.0 to +6.5 -65 to +150 Unit V V V °C Operating Conditions Parameter Operating supply voltage Operating temperature Symbol Conditions Ratings 2.7 to 5.5 -40 to +85 Unit V °C DC Electrical Characteristics Parameter Power supply current at reading Power supply current at writing Symbol ICC1 ICC2 ISB Conditions f=400kHz, VDD=VDD max f=400kHz, tWC=5ms, VDD=VDD max VIN=VDD or GND, (VDD= 2.7V) VIN=VDD or GND, (VDD= 5.5V) ILI ILO VIL VIH VOL Output low voltage IOL=0.7mA, VDD1=2.7V IOL=2.0mA, VDD1=2.7V IOL=3.0mA, VDD1=5.5V VDD*0.7 0.2 0.4 0.4 VIN=GND to VDD, VDD=VDD max VIN=GND to VDD, VDD=VDD max -2.0 -2.0 typ. min. max 1 5 2 5 +2.0 +2.0 VDD*0.3 Unit mA mA μA μA μA μA V V V V V CMOS standby current Input leakage current Output leakage current Input low voltage Input high voltage Capacitance/Ta=25°C, f=1.0MHz Parameter In/Output capacitance Input capacitance Symbol CI/O CI Conditions VI/O=0V (SDA) VIN=0V min typ max 10 10 Unit pF pF Note: This parameter is sampled and not 100% tested. AC Electric Characteristics Input pulse level Input rise / fall time Input / output timing level Output load 0.1*VDD to 0.9*VDD 20ns 0.5*VDD 50pF + Pull up resistor 3.0kΩ VDD R=3.0k SDA C=50pF No.1887-3/12 LE24CB1283 Fast Mode Parameter SCL clock frequency SCL pulse with Low SCL pulse with High Access time Data output hold time Start condition setup time Start condition hold time Data in setup time Data in hold time Stop condition setup time SCL, SDA rise time SCL, SDA fall time Bus free time for next mode Noise suppression time Write time Symbol min fSCLS tLOW tHIGH tAA tDH tSU.STA tHD.STA tSU.DAT tHD.DAT tSU.STO tR tF tBUF tSP tWC 1200 100 5 0 1200 600 100 100 600 600 100 0 600 300 300 900 Spec typ max 400 kHz ns ns ns ns ns ns ns ns ns ns ns ns ns ms unit Standard Mode Parameter SCL clock frequency SCL pulse with Low SCL pulse with High Access time Data output hold time Start condition setup time Start condition hold time Data in setup time Data in hold time Stop condition setup time SCL, SDA rise time SCL, SDA fall time Bus free time for next mode Noise suppression time Write time Symbol min fSCLS tLOW tHIGH tAA tDH tSU.STA tHD.STA tSU.DAT tHD.DAT tSU.STO tR tF tBUF tSP tWC 4700 100 5 0 4700 4000 100 100 4700 4000 250 0 4000 1000 300 3500 Spec typ max 100 kHz ns ns ns ns ns ns ns ns ns ns ns ns ns ms unit No.1887-4/12 LE24CB1283 Bus Timing tF tHIGH tLOW tR tSP tSU.STA tHD.STA tHD.DAT tHD.STA tSU.STO tSP tBUF tAA tDH SCL SDA/IN SDA/OUT Write Timing tWC SCL SDA D0 Write data Acknowledge Stop condition Start condition Pin Functions SCL (serial clock) The SCL signal is used to control serial input data timing. The SCL is used to latch input data synchronously at the rising edge and read output data synchronously at the falling edge. SDA (serial input/output data) The SDA pin is bidirectional for serial data transfer. It is an open-drain structure that needs to be pulled up by resistor. WP (Write protect) When the WP signal is high, write protections are enabled. When this signal is low, write operation for all memory arrays are allowed. The read operation is always activated irrespective of the WP pin status. S0/S1/S2 (Slave address) When many devices are connected on the same bus, the S0/S1/S2 are used to select the device. The S0/S1/S2 must be tied to VDD or GND. No.1887-5/12 LE24CB1283 Functional Description The device supports the I2C protocol. Any device that sends data on to the bus is defined to be a transmitter, and any device that reads the data to a receiver. The device that controls the data transfer is known as the bus master, and the other as the slave device. 1. Start condition A Start condition is needs to start the EEPROM operation, it is to set falling edge of the SDA while the SCL is stable in the high status. 2. Stop condition A Start condition is identified by rising edge of the SDA signal while the SCL is stable in the high status. The device becomes the standby mode from a Read operation by a Stop condition. In a write sequence, a stop condition is trigger to start the internal write cycle. After the internally write cycle time which is specified as tWC, the device enters a standby mode. tSU.STA tHD.STA tSU.STO SCL SDA Start condition Stop condition 3. Data Input During data input, the device latches the SDA on the rising edge of the SCL. For correct the operation, the SDA must be stable during the rising edge of the SCL. tSU.DAT tHD.DAT SCL SDA 4. Acknowledge The Acknowledge Bit is used to indicate a successful byte data transfer. The receiver sends a zero to acknowledge that it has received each word (Device Code, Slave Address etc) from the transmitter. SCL (EEPROM input) SDA (Master output) SDA (EEPROM output) Start condition 1 8 9 Acknowledge bit output tAA tDH No.1887-6/12 LE24CB1283 5. Device addressing To transmit between the bus master and slave device (EEPROM), the master must send a Start condition to the EEPROM. The device address word of the EEPROM consists of 4-bit Device Code, 3-bit Slave Device address code and 1-bit read/write code. By sending these, it becomes possible to communicate between the bus master and the EEPROM. The upper 4-bit of the device address word are called the Device Code, the Device Code of the EEPROM uses 1010b fixed code. This device has the 3-bit of the Slave Device address as the Slave address (S0, S1, S2), so it can connect up to eight device on the bus. When the Device Code is received on the SDA, the device only responds if Slave address pin tied to VDD or GND is the same as the Slave address signal input. The 8th bit is the read/write bit. The bit is set to 1 for Read operation and 0 for Write operation. If a match occurs on the Device Code, the corresponding device gives an acknowledgement on SDA during the 9th bit time. If device does not match the Device Code, it deselects itself from the bus, and goes into the Standby mode. Use the Random Read command when you execute reading after the slave device was switched. Device code 1 MSB 0 1 0 S2 Slave Address S1 S0 R/W LSB Device Address word No.1887-7/12 LE24CB1283 6 EEPROM write operation 6-1. Byte writes The write operation requires a 7-bit device address word with the 8th bit = 0(write). Then the EEPROM sends acknowledgement 0 at the 9th clock cycle. After these, the EEPROM receives word address (A15 to A8), and the EEPROM outputs acknowledgement 0. And then, the EEPROM receives word address (A7 to A0), and the EEPROM outputs acknowledgement 0. Then the EEPROM receives 8-bit write data, the EEPROM outputs acknowledgement 0 after receipt of write data. If the EEPROM receives a stop condition, the EEPROM enters an internally timed (tWC) write cycle and terminates receipt of inputs until completion of the write cycle. Word Address Start Data D7 D6 D5 D4 D3 D2 D1 D0 ACK Stop SDA 1 0 1 0 S2 S1 S0 W AAAAAA 15 14 13 12 11 10 A9 A8 ACK R/W A7 A6 A5 A4 A3 A2 A1 A0 ACK ACK Access from master 6-2. Page writes The Page write allows up to 64 bytes to be written in a single write cycle. The page write is the same sequence as the byte writes except for inputting the more write data. The page write is initiated by a start condition, device code, device address, memory address (n) and write data (n) with every 9th bit acknowledgement. The device enters the page write operation if this device receives more write data (n+1) instead of receiving a stop condition. The page address (A0 to A5) bits are automatically incremented on receiving write data (n+1). The device can continue to receive write data up to 64 bytes. If the page address bits reach the last address of the page, the page address bits will roll over to the first address of the same page and previous write data will be overwritten. After these, if the device receives a stop condition, the device enters an internally timed (tWC × (n+x)) write cycle and terminates receipt of inputs until completion of the write cycle. Word Address(n) Data(n) D7 D6 D5 D4 D3 D2 D1 D0 ACK ACK SDA Start 1 0 1 0 S2 S1 S0 W AAAAAA 15 14 13 12 11 10 A9 A8 ACK R/W A7 A6 A5 A4 A3 A2 A1 A0 ACK Data(n+1) D7 D6 D1 D0 D7 D6 D1 D0 D7 D6 D1 D0 Data(n+x) D7 D6 D1 D0 ACK ACK ACK Access from master 6-3. Acknowledge polling The Acknowledge polling operation is used to show if the EEPROM is in an internally timed write cycle or not. This operation is initiated by the stop condition after inputting write data. This requires the 8-bit device address word with the 8th bit = 0 (write) following the start condition during an internally timed write cycle. If the EEPROM is busy with the internal write cycle, no acknowledge will be returned. If the EEPROM has terminated the internal write cycle, it responds with an acknowledge. The terminated write cycle of the EEPROM can be known by this operation. During Write Start Start During Write Start Stop ACK End of Write SDA 1 0 1 0 S2 S1 S0 W 1 0 1 0 S2 S1 S0 W 1 0 1 0 S2 S1 S0 W ACK R/W Access from master NO ACK R/W NO ACK R/W No.1887-8/12 LE24CB1283 7 EEPROM read operations 7-1. Current address reading The device has an internal address counter. It maintains that last address during the last read or write operation, with incremented by one. The current address read accesses the address kept by the internal address counter. After receiving a start condition and the device address word with the 8th bit = 1 (read), the EEPROM outputs the 8-bit current address data from following acknowledgement 0. If the EEPROM receives acknowledgement 1 and a following stop condition, the EEPROM stops the read operation and is returned to a standby mode. In case the EEPROM has accessed the last address of the last page at previous read operation, the current address will roll over and returns to zero address. In case EEPROM has accessed the last address of the last page at previous write operation, the current address roll over within page addressing and returns to the first address in the same page. The current address is valid while power is ON. After power on, the current address will be reset (all 0). Note: After the page writes operation, the current address is the specified memory address in the last page write. If the write data is more than 64-bytes. Device Address Data(n+1 Address) D7 D6 D5 D4 D3 D2 D1 D0 ACK R/W Start SDA 1 0 1 0 S2 S1 S0 R NO ACK Access from master 7-2. Random read The random read requires a dummy write to set read address. The EEPROM receives a start condition and the device address word with the 8th bit = 0 (write), the memory address. The EEPROM outputs acknowledgement 0 after receiving memory address then enters a current address read with receiving a start condition. The EEPROM outputs the read data of the address which was defined in the dummy write operation. After receiving no acknowledgement and a following stop condition, the EEPROM stop the random read operation and returns to standby mode. Word Address(n) SDA Start 1 0 1 0 S2 S1 S0 W AAAAAA 15 14 13 12 11 10 A9 A8 ACK R/W Dummy Write Device Address Stop A7 A6 A5 A4 A3 A2 A1 A0 ACK ACK Data(n) D7 D6 D1 D0 Start 1 0 1 0 S2 S1 S0 R ACK ACK R/W Current Address Read Access from master NO ACK 7-3. Sequential read The sequential read operation is initiated by either a current address read or random read. If the EEPROM receives acknowledgement 0 after 8-bit read data, the read address is incremented and the next 8-bit read data outputs. The current address will roll over and returns address zero if it reaches the last address of the last page. The sequential read can be continued after roll over. The sequential read is terminated if the EEPROM receives no acknowledgement and a following stop condition. Device Address Data(n) D7 D6 D1 D0 Data(n+1) D7 D6 D1 D0 Data(n+2) D7 D6 D1 D0 Data(n+x) D7 D6 D1 D0 Start Stop SDA 1 0 1 0 S2 S1 S0 R ACK R/W ACK ACK ACK NO ACK Access from master Stop No.1887-9/12 LE24CB1283 Application Notes 1) Software reset function Software reset (start condition + 9 dummy clock cycles + start condition), shown in the figure below, is executed in order to avoid erroneous operation after power-on and to reset while the command input sequence. During the dummy clock input period, the SDA bus must be opened (set to high by a pull-up resistor). Since it is possible for the ACK output and read data to be output from the EEPROM during the dummy clock period, forcibly entering H will result in an overcurrent flow. Note that this software reset function does not work during the internal write cycle. Dummy clock ×9 SCL 1 2 8 9 SDA Start condition Start condition 2) Pull-up resistor of SDA pin Due to the demands of the I2C bus protocol function, the SDA pin must be connected to a pull-up resistor (with a resistance from several kΩ to several tens of kΩ) without fail. The appropriate value must be selected for this resistance (RPU) on the basis of the VIL and IIL of the microcontroller and other devices controlling this product as well as the VOL–IOL characteristics of the product. Generally, when the resistance is too high, the operating frequency will be restricted; conversely, when it is too low, the operating current consumption will increase. RPU maximum resistance The maximum resistance must be set in such a way that the bus potential, which is determined by the sum total (IL) of the input leaks of the devices connected to the SDA bus and by RPU, can completely satisfy the input high level (VIH min) of the microcontroller and EEPROM. However, a resistance value that satisfies SDA rise time tR and fall time tF must be set. RPU maximum value = (VDD - VIH)/IL Example: When VDD=3.0V and IL= 2μA RPU maximum value = (3.0V − 3.0V × 0.8)/2μA = 300kΩ RPU minimum value A resistance corresponding to the low-level output voltage (VOL max) of SANYO’s EEPROM must be set. RPU minimum value = (VDD − VOL)/IOL Example: When VDD=3.0V, VOL = 0.4V and IOL = 1mA RPU minimum value = (3.0V − 0.4)/1mA = 2.6kΩ Recommended RPU setting RPU is set to strike a good balance between the operating frequency requirements and power consumption. If it is assumed that the SDA load capacitance is 50pF and the SDA output data strobe time is 500ns, RPU will be about RPU = 500ns/50pF = 10kΩ. SDA RPU Master Device IL EEPROM CBUS IL No.1887-10/12 LE24CB1283 3) Precautions when turning on the power This product contains a power-on reset circuit for preventing the inadvertent writing of data when the power is turned on. The following conditions must be met in order to ensure stable operation of this circuit. No data guarantees are given in the event of an instantaneous power failure during the internal write operation. Item Power rise time Power off time Power bottom voltage Symbol tRISE tOFF Vbot 10 0.2 min typ max 100 unit ms ms V tRISE VDD tOFF Vbot 0V Notes: 1) The SDA pin must be set to high and the SCL pin to low or high. 2) Steps must be taken to ensure that the SDA and SCL pins are not placed in a high-impedance state. A. If it is not possible to satisfy the instruction 1 in Note above, and SDA is set to low during power rise After the power has stabilized, the SCL and SDA pins must be controlled as shown below, with both pins set to high. VDD tLOW VDD SCL SDA tDH tSU .DAT tSU.DAT SCL SDA B. If it is not possible to satisfy the instruction 2 in Note above After the power has stabilized, software reset must be executed. C. If it is not possible to satisfy the instructions both 1 and 2 in Note above After the power has stabilized, the steps in A must be executed, then software reset must be executed. 4) Noise filter for the SCL and SDA pins This product contains a filter circuit for eliminating noise at the SCL and SDA pins. Pulses of 100ns or less are not recognized because of this function. 5) Function to inhibit writing when supply voltage is low This product contains a supply voltage monitoring circuit that inhibits inadvertent writing below the guaranteed operating supply voltage range. The data is protected by ensuring that write operations are not started at voltages (typ.) of 1.3V and below. No.1887-11/12 LE24CB1283 6) Notes on write protect operation This product prohibits all memory arrays writing when the WL pin is high. To ensure full write protection, the WP is set high for all periods from the start condition to the stop condition, and the conditions below must be satisfied. symbol tSU.WP tHD.WP WP Setup time WP Hold time Parameter min 600 600 spec typ max Unit ns ns WP tSU.WP tHD.WP SCL SDA Start condition Stop condition SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein. SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all semiconductor products fail or malfunction with some probability. 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SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's intellectual property rights which has resulted from the use of the technical information and products mentioned above. T his catalog provides information as of January, 2011. Specifications and information herein are subject to change without notice. PS No.1887-12/12