LE24LB1283

Ordering number : ENA1706B CMOS IC LE24LB1283 Overview Two Wire Serial Interface EEPROM (128k EEPROM) The LE24LB1283 is a 2-wire serial interface EEPROM. It realizes high speed and a high level reliability by incorporating SANYO’s high performance CMOS EEPROM technology. This device is compatible with I2C memory protocol, therefore it is best suited for application that requires small-scale re-writable nonvolatile parameter memory. Functions • Capacity: 128k bits (16k × 8 bits) • Single supply voltage: 1.8V to 3.6V • Interface: Two wire serial interface (I2C Bus*) • Operating clock frequency: 400kHz • Low power consumption : Standby: 2μA (max) : Active (Read): 0.5mA (max) • Automatic page write mode: 64 Bytes • Read mode: Sequential read and random read • Erase/Write cycles: 106 cycles • Data Retention: 20 years • High reliability: Adopts SANYO’s proprietary symmetric memory array configuration (USP6947325) Noise filters connected to SCL and SDA pins Incorporates a feature to prohibit write operations under low voltage conditions. • Package : LE24LB1283M : MFP8(225mil) * I2C Bus is a trademark of Philips Corporation. * This product is licensed from Silicon Storage Technology, Inc. (USA), and manufactured and sold by SANYO Semiconductor Co., Ltd. Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment (home appliances, AV equipment, communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee thereof. 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To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer' s products or equipment. 33111 SY/10511 SY/42810 SY 20100330-S00006 No.A1706-1/14 LE24LB1283 Pin Assignment S0 S1 S2 GND 1 2 3 4 8 7 6 5 VDD WP SCL SDA Pin Descriptions PIN.1 PIN.2 PIN.3 PIN.4 PIN.5 PIN.6 PIN.7 PIN.8 S0 S1 S2 GND SDA SCL WP VDD Slave device address 0 Slave device address 1 Slave device address 2 Ground Serial data input/output Serial clock input Write protect Power supply Package Dimensions unit:mm (typ) 3032E 5.0 8 [LE24LB1283M] 4.4 6.4 1 (0.6) 2 1.27 0.35 0.15 SANYO : MFP8(225mil) Block Diagram 0.1 (1.5) 1.7 MAX 0.63 Write controller WP Condition detector High voltage generator S0 S1 S2 SCL Input Buffer Serial controller Address generator X-decoder EEPROM Array I/O Buffer Y decoder & Sense AMP Serial-Parallel converter SDA No.A1706-2/14 LE24LB1283 Specifications Absolute Maximum Ratings Parameter Supply voltage DC input voltage Over-shoot voltage Storage temperature Tstg Below 20ns Symbol Conditions Ratings -0.5 to +4.6 -0.5 to VDD+0.5 -1.0 to VDD+1.0 -65 to +150 unit V V V °C Note: If an electrical stress exceeding the maximum rating is applied, the device may be damaged. Operating Conditions Parameter Operating supply voltage Operating temperature Symbol Conditions Ratings 1.8 to 3.6 -40 to +85 unit V °C DC Electrical Characteristics Parameter Supply current at reading Supply current at writing Standby current Input leakage current Output leakage current (SDA) Input low voltage Input low voltage (CMOS) Input high voltage Input high voltage (CMOS) Symbol ICC1 ICC2 ISB ILI ILO VIL VILC VIH VIHC IOL=0.7mA, VDD=1.8V Output low voltage VOL IOL=1.0mA, VDD=1.8V IOL=2.0mA, VDD=2.5V VDD*0.7 VDD-0.2 0.2 0.4 0.4 Conditions min f=400kHz, VDD=VDD max f=400kHz, tWC=10ms, VDD=VDD max VIN=VDD or GND, VDD=VDD max VIN=GND to VDD, VDD=VDD max VOUT=GND to VDD, VDD=VDD max -2.0 -2.0 Standard value typ max 0.5 5 2 +2.0 +2.0 VDD*0.3 0.2 mA mA μA μA μA V V V V V V V unit Capacitance/Ta=25°C, f=1MHz Parameter In/Output pin capacitance Input pin capacitance Symbol CI/O CI VI/O=0V (SDA) VIN=0V (other than SDA) Conditions max 10 10 unit pF pF Note: This parameter is sampled and not 100% tested. AC Electric Characteristics Input pulse level Input pulse rise / fall time Output detection voltage Output load 0.1×VDD to 0.9×VDD 20ns 0.5×VDD 50pF+Pull up resistor 3.0kΩ VDD R=3.0kΩ SDA C=50pF Output Load Circuit No.A1706-3/14 LE24LB1283 Fast Mode Parameter Slave mode SCL clock frequency SCL clock low time SCL clock high time SDA output delay time SDA data output hold time Start condition setup time Start condition hold time Data in setup time Data in hold time Stop condition setup time SCL SDA rise time SCL SDA fall time Bus release time Noise suppression time Write cycle time Symbol min fSCLS tLOW tHIGH tAA tDH tSU.STA tHD.STA tSU.DAT tHD.DAT tSU.STO tR tF tBUF tSP tWC 1200 100 5 0 1200 600 100 100 600 600 100 0 600 300 300 900 Standard value typ max 400 kHz ns ns ns ns ns ns ns ns ns ns ns ns ns ms unit Standard Mode Parameter Slave mode SCL clock frequency SCL clock low time SCL clock high time SDA output delay time SDA data output hold time Start condition setup time Start condition hold time Data in setup time Data in hold time Stop condition setup time SCL SDA rise time SCL SDA fall time Bus release time Noise suppression time Write cycle time Symbol min fSCLS tLOW tHIGH tAA tDH tSU.STA tHD.STA tSU.DAT tHD.DAT tSU.STO tR tF tBUF tSP tWC 4700 100 5 0 4700 4000 100 100 4700 4000 250 0 4000 1000 300 3500 Standard value typ max 100 kHz ns ns ns ns ns ns ns ns ns ns ns ns ns ms unit No.A1706-4/14 LE24LB1283 Bus Timing tF tHIGH tLOW tR SCL tSU.STA tHD.STA tHD.DAT tSU.DAT tSU.STO tSP SDA/IN tAA tDH tBUF tSP SDA/OUT Write Timing tWC SCL SDA D0 Write data Acknowledge Stop condition Start condition Pin Functions SCL (serial clock input) pin The SCL pin is a serial clock input pin that processes signals at the rising and falling edges of SCL clock signals. The SCL pin must be pulled up by a resistor to the VDD level and wired-ORed with an open drain (or open collector) output device for use. SDA (serial data input/output) pin The SDA pin is used to transfer serial data to the input/output, and it consists of a signal input pin and n-channel transistor open drain output pin. Like the SCL pin, the SDA pin must be pulled up by a resistor to the VDD level and wired-ORed with an open drain (or open collector) output device for use. WP (write protect) pin When the WP pin is high, write protection is enabled, and writing into the all memory areas is prohibited. When the pin is low, writing is possible to all memory areas. Read operations can be performed regardless of the WP pin status. S0, S1, S2 (slave device address) pin An individual product is selected by using S0 pin, S1 pin and S2 pin when it connects on the same bus. This product can set the slave address by connecting S0 pin, S1 pin and S2 pin with VDD or GND when the substrate is mounted. It is necessary to fix the terminal not used as a slave address to VDD or GND on the substrate. No.A1706-5/14 LE24LB1283 Functional Description 1 Start condition When the SCL line is at the high level, the start condition is established by changing the SDA line from high to low. The operation of the EEPROM as a slave starts in the start condition. 2 Stop condition When the SCL line is at the high level, the stop condition is established by changing the SDA line from low to high. When the device is set up for the read sequence, the read operation is suspended when the stop condition is received, and the device is set to standby mode. When it is set up for the write sequence, the capture of the write data is ended when the stop condition is received, and the EEPROM internal write operation is started. tSU.STA tHD.STA tSU.STO SCL SDA Start condition Stop condition 3 Data transfer Data is transferred by changing the SDA line while the SCL line is low. When the SDA line is changed while the SCL line is high, the resulting condition will be recognized as the start or stop condition. tSU.DAT tHD.DAT SCL SDA No.A1706-6/14 LE24LB1283 4 Acknowledge During data transfer, 8-bits are transferred in succession, and then in the ninth clock cycle period the device on the system bus receiving the data sets the SDA line to low, and sends the acknowledge signal indicating that the data has been received. The acknowledge signal is not sent during an EEPROM internal write operation. SCL (EEPROM input) 1 8 9 SDA (Master output) SDA (EEPROM output) Acknowlwdge bit output Start condition tAA tDH 5 Device addressing For the purposes of communication, the master device in the system generates the start condition for the slave device (EEPROM). Communication with a particular slave device is enabled by sending along the SDA bus the device address, which is 7-bits long, and the read/write command code, which is 1 bit long, immediately following the start condition. The upper four bits of the device address are called the device code which, for this product, is fixed as “1010.” Two or more pieces cannot be connected about this IC because there is no slave address. This product can connect EEPROM devices up to eight on the system bus by having slave address S0, S1, and S2 in three bits following the device code, and setting the slave address with S0 pin, S1 pin and S2 pin when the substrate is mounted. Device code + slave address input from SDA and the slave address set when this product device code + slave address for mounted are compared, this product returns the acknowledge for the period of the ninth clock cycle when agreeing, and the Read or the Write operates according to Read/Write instruction code. It becomes a standby mode if not agreeing. When reading is executed immediately after the slave device was switched, the random lead command is used. Device Code LE24LB1283 1 0 1 0 S2 Slave Address S1 S0 R/W MSB Device address word LSB No.A1706-7/14 LE24LB1283 6 EEPROM write operation 6-1. Byte writing When the EEPROM receives the 7-bit device address and write command code "0" after the start condition, it generates an acknowledge signal. After this, if it receives word address (A15 to A8) generates an acknowledge signal, receives the word address (A7 to A0), and generates an acknowledge signal when it receives the stop condition, the rewrite operation of the EEPROM in the designated memory address will start. Rewriting is completed in the tWC period after the stop condition. During an EEPROM rewrite operation, no input is accepted and no acknowledge signals are generated. Word Address Data D7 D6 D5 D4D3 D2 D1 D0 ACK Start SDA 1 0 1 0 S2 S1 S0 W AAAAAA 15 14 13 12 11 10 A9 A8 ACK R/W A7 A6 A5 A4 A3 A2 A1 A0 ACK Access from master side 6-2. Page writing This product enables pages with up to 64 bytes to be written. The basic data transfer procedure is the same as for byte writing: Following the start condition, the 7-bit device address and write command code “0,” word address (n), and data (n) are input in this order while confirming acknowledge “0” every 9 bits. The page write mode is established if, after data (n) is input, the write data (n+1) is input without inputting the stop condition. After this, the write data equivalent to the largest page size can be received by a continuous process of repeating the receiving of the 8-bit write data and generating the acknowledge signals. At the point when the write data (n+1) has been input, the lower 6 bits (A0-A5) of the word addresses are automatically incremented to form the (n+1) address. In this way, the write data can be successively input, and the word address on the page is incremented each time the write data is input. If the write data exceeds 64 bytes or the last address of the page is exceeded, the word address on the page is rolled over. Write data will be input into the same address two or more times, but in such cases the write data that was input last will take effect. Finally, the EEPROM internal write operation corresponding to the page size for which the write data is received starts from the designated memory address when the stop condition is received. Word Address SDA Start Data(n) D7 D6 D5 D4D3 D2 D1 D0 ACK Data(n+x) ACK 1 0 1 0 S2 S1 S0 W AAAAAA 15 14 13 12 11 10 A9 A8 ACK R/W A7 A6 A5 A4 A3 A2 A1 A0 ACK Data(n+1) D7 D6 D1 D0 ACK D7 D6 ACK D1 D0 D7 D6 D1 D0 D7 D6 ACK D1 D0 ACK Access from master side Stop No.A1706-8/14 Stop LE24LB1283 6-3. Acknowledge polling Acknowledge polling is used to find out when the EEPROM internal write operation is completed. When the stop condition is received and the EEPROM starts rewriting, all operations are prohibited, and no response can be given to the signals sent by the master device. Therefore, in order to find out when the EEPROM internal write operation is completed, the start condition, device address and write command code are sent from the master device to the EEPROM (slave device), and the response of the slave device is detected. In other words, if the slave device does not send the acknowledge signal, it means that the internal write operation is in progress; conversely, if it does send the acknowledge signal, it means that the internal write operation has been completed. Execute "0" of the write instruction when you do write or ramdom read continuously by the code that the master device sends in the acknowledge polling and execute "1" of the lead instruction when you continuously do current read or sequential read. Moreover, the command is canceled by inputting the start condition / stop condition after "0" of the write instruction is executed and ACK=L is confirmed, and it shifts to the standby mode. Write timing SDA Write timing Writting end Start Start Start 1 0 1 0 S2 S1 S0 W 1 0 1 0 S2 S1 S0 W NO ACK R/W 1 0 1 0 S2 S1 S0 W ACK R/W Access from master side NO ACK R/W No.A1706-9/14 LE24LB1283 7 EEPROM read operations 7-1. Current address reading The address equivalent to the memory address accessed last +1 is held as the internal address of the EEPROM for both write* and read operations. Therefore, provided that the master device has recognized the position of the EEPROM address pointer, data can be read from the memory address with the current address pointer without specifying the word address. As with writing, current address reading involves receiving the 7-bit device address and read command code “1” following the start condition, at which time the EEPROM generates an acknowledge signal. After this, the 8-bit data of the (n+1) address is output serially starting with the highest bits. After the 8 bits have been output, by not sending an acknowledge signal and inputting the stop condition, the EEPROM completes the read operation and is set to standby mode. If the previous read address is the last address, the address for the current address reading is rolled over to become address 0. *: If the write data is 1 or more bytes but less than 64 bytes, the current address after page writing is the address equivalent to the number of bytes to be written in the specified word address +1. If the write data is 64 or more bytes, it is the designated word address. If the last address (A5-A0=1111b) on the page has been designated by byte write as the word address, the first address (A5-A0=0000b) on the page serves as the internal address after writing. Device Address SDA Data(n+1 address) Start 1 0 1 0 S2 S1 S0 R D7 D6 D5 D4D3 D2 D1 D0 ACK R/W NO ACK Access from master side 7-2. Random read Random read is a mode in which a selected memory address is specified and its data is read. The address is specified by a dummy write input. First, when the EEPROM receives the 7-bit device address and write command code "0" following the start condition, it generates an acknowledge signal. It then receives word address (A15 to A8) and generates an acknowledge signal, and receives word address (A7 to A0) and generates an acknowledge signal. These operations are used to load the word address to the address counter in the EEPROM. Next, the start condition is input again, and the current read is performed. This generates the word address data that was input using the dummy write input. After the data is generated, if the stop condition is input without the input of an acknowledge signal, reading is completed, and standby mode is established. Device Address Word Address AAAAAA 15 14 13 12 11 10 A9 A8 ACK R/W Dummy Write Device Address Data(n) D7 D6 D1 D0 A7 A6 A5 A4 A3 A2 A1 A0 ACK ACK SDA Start 1 0 1 0 S2 S1 S0 W Stop Start 1 0 1 0 S2 S1 S0 R ACK ACK R/W Current Read NO ACK Access from master side Stop No.A1706-10/14 LE24LB1283 7-3. Sequential read In this mode, the data is read continuously, and sequential read operations can be performed with both current address read and random read. If, after the 8-bit data has been output, acknowledge “0” is input and reading is continued without issuing the stop condition, the address is incremented, and the data of the next address is output. If acknowledge “0” continues to be input after the data has been output in this way, the data is successively output while the address is incremented. When the last address is reached, it is rolled over to address 0, and the data continues to be read. As with current address read and random read, the operation is completed by inputting the stop condition without sending an acknowledge signal. Device Address SDA Start Data(n) D7 D6 ACK R/W D1 D0 Data(n+1) D7 D6 ACK D1 D0 Data(n+2) D7 D6 ACK D1 D0 Data(n+x) D7 D6 ACK D1 D0 Stop 1 0 1 0 S2 S1 S0 R ACK Access from master side No.A1706-11/14 LE24LB1283 Application Notes 1) Software reset function Software reset (start condition + 9 dummy clock cycles + start condition), shown in the figure below, is executed in order to avoid erroneous operation after power-on and to reset while the command input sequence. During the dummy clock input period, the SDA bus must be opened (set to high by a pull-up resistor). Since it is possible for the ACK output and read data to be output from the EEPROM during the dummy clock period, forcibly entering H will result in an overcurrent flow. Note that this software reset function does not work during the internal write cycle. Dummy clock cycle × 9 SCL 1 2 8 9 SDA Start condition Start condition 2) Pull-up resistor of SDA pin Due to the demands of the I2C bus protocol function, the SDA pin must be connected to a pull-up resistor (with a resistance from several kΩ to several tens of kΩ) without fail. The appropriate value must be selected for this resistance (RPU) on the basis of the VIL and IIL of the microcontroller and other devices controlling this product as well as the VOL–IOL characteristics of the product. Generally, when the resistance is too high, the operating frequency will be restricted; conversely, when it is too low, the operating current consumption will increase. RPU maximum resistance The maximum resistance must be set in such a way that the bus potential, which is determined by the sum total (IL) of the input leaks of the devices connected to the SDA bus and by RPU, can completely satisfy the input high level (VIH min) of the microcontroller and EEPROM. However, a resistance value that satisfies SDA rise time tR and fall time tF must be set. RPU maximum value = (VDD - VIH)/IL Example: When VDD=3.0V and IL= 2μA RPU maximum value = (3.0V − 3.0V × 0.8)/2μA = 300kΩ RPU minimum value A resistance corresponding to the low-level output voltage (VOL max) of SANYO’s EEPROM must be set. RPU minimum value = (VDD − VOL)/IOL Example: When VDD=3.0V, VOL = 0.4V and IOL = 1mA RPU minimum value = (3.0V − 0.4)/1mA = 2.6kΩ Recommended RPU setting RPU is set to strike a good balance between the operating frequency requirements and power consumption. If it is assumed that the SDA load capacitance is 50pF and the SDA output data strobe time is 500ns, RPU will be about RPU = 500ns/50pF = 10kΩ. RPU EEPROM Master device IL SDA CBUS IL No.A1706-12/14 LE24LB1283 3) Precautions when turning on the power This product contains a power-on reset circuit for preventing the inadvertent writing of data when the power is turned on. The following conditions must be met in order to ensure stable operation of this circuit. No data guarantees are given in the event of an instantaneous power failure during the internal write operation. Item Power rise time Power off time Power bottom voltage Symbol min tRISE tOFF Vbot 10 0.2 Standard value typ max 100 ms ms V unit tRISE VDD tOFF Vbot 0V Notes: 1) The SDA pin must be set to high and the SCL pin to low or high. 2) Steps must be taken to ensure that the SDA and SCL pins are not placed in a high-impedance state. A. If it is not possible to satisfy the instruction 1 in Note above, and SDA is set to low during power rise After the power has stabilized, the SCL and SDA pins must be controlled as shown below, with both pins set to high. VDD tLOW SCL VDD SCL SDA tDH tSU.DAT SDA tSU.DAT B. If it is not possible to satisfy the instruction 2 in Note above After the power has stabilized, software reset must be executed. C. If it is not possible to satisfy the instructions both 1 and 2 in Note above After the power has stabilized, the steps in A must be executed, then software reset must be executed. 4) Noise filter for the SCL and SDA pins This product contains a filter circuit for eliminating noise at the SCL and SDA pins. Pulses of 100ns or less are not recognized because of this function. 5) Function to inhibit writing when supply voltage is low This product contains a supply voltage monitoring circuit that inhibits inadvertent writing below the guaranteed operating supply voltage range. The data is protected by ensuring that write operations are not started at voltages (typ.) of 1.3V and below. No.A1706-13/14 LE24LB1283 6) Notes on write protect operation This product prohibits all memory area writing when the WP pin is high. To ensure full write protection, the WP is set high for all periods from the start condition to the stop condition, and the conditions below must be satisfied. Item WP Setup time WP Hold time Symbol min tSU.WP tHD.WP 600 600 Standard value typ max ns ns unit WP tSU.WP tHD.WP SCL SDA Start condition Stop condition SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein. SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO Semiconductor Co.,Ltd. products described or contained herein are controlled under any of applicable local export control laws and regulations, such products may require the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written consent of SANYO Semiconductor Co.,Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO Semiconductor Co.,Ltd. product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. Upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third party. SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's intellctual property rights which has resulted from the use of the technical information and products mentioned above. This catalog provides information as of March, 2011. Specifications and information herein are subject to change without notice. PS No.A1706-14/14