LE25FS406

Ordering number : ENA1577D LE25FS406 Overview CMOS IC 4M-bit (512K×8) Serial Flash Memory The LE25FS406 is a SPI bus flash memory device with a 4M bit (512K × 8-bit) configuration. It uses a single 1.8V power supply. While making the most of the features inherent to a serial flash memory device, the LE25FS406 is housed in an 8-pin ultra-miniature package. All these features make this device ideally suited to storing program in applications such as portable information devices, which are required to have increasingly more compact dimensions. The LE25FS406 also has a small sector erase capability which makes the device ideal for storing parameters or data that have fewer rewrite cycles and conventional EEPROMs cannot handle due to insufficient capacity. Features • Read/write operations enabled by single 1.8V power supply: 1.65 to 2.10V supply voltage range • Operating frequency : 30MHz • Temperature range : 0 to 70°C / –40 to +85°C (at the planning stage) • Serial interface : SPI mode 0, mode 3 supported • Sector size : 4K bytes/small sector, 64K bytes/sector • Small sector erase, sector erase, chip erase functions • Page program function (256 bytes / page) • Block protect function • Data retention period : 20 years • Status functions : Ready/busy information, protect information • Highly reliable read/write Number of rewrite times : 100,000 times Small sector erase time : 40ms (typ.), 150ms (max.) Sector erase time : 80ms (typ.), 250ms (max.) Chip erase time : 300ms (typ.), 3.0s (max.) Page program time : 6.0ms/256 bytes (typ.), 8.0ms/256 bytes (max.) • Package : LE25FS406TT MSOP8 (225mil): planning : LE25FS406LF VSON8N(6.0 × 5.0) : LE25FS406MA MFP8 (225mil) : LE25FS406FQ VSON8(4.0 × 3.0) * This product is licensed from Silicon Storage Technology, Inc. (USA), and manufactured and sold by SANYO Semiconductor Co., Ltd. Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment (home appliances, AV equipment, communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee thereof. If you should intend to use our products for applications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our customer shall be solely responsible for the use. Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer' s products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer' s products or equipment. 10511 SY/N2410 SY/73010 SY/70710 SY 20100630-S00001/31010 SY No.A1577-1/22 LE25FS406 Package Dimensions unit:mm (typ) 3276 5.2 TOP VIEW SIDE VIEW BOTTOM VIEW Package Dimensions [LE25FS406TT] unit:mm (typ) 3391 [LE25FS406LF] 8 5 5.0 8 Exposed Die-Pad Do Not Connect 4.4 6.3 (4.0) 6.0 0.5 1 (0.7) 1.27 4 0.35 0.85max 0.6 (3.4) 0.125 1 2 1.27 SIDE VIEW 0.4 2 1 (0.595) 0.08 0.0 NOM 0.85 MAX (0.65) (0.8) SANYO : VSON8N(6.0x5.0) SANYO : MSOP8(225mil) Package Dimensions unit:mm (typ) 3032E 5.0 8 Package Dimensions [LE25FS406MA] unit:mm (typ) 3392A TOP VIEW 3.0 8 Exposed Die-Pad Do Not Connect SIDE VIEW [LE25FS406FQ] BOTTOM VIEW 4.4 6.4 0.63 4.0 (2.4) 0.5 (1.8) 1 (0.6) 2 1.27 0.35 0.15 1.7 MAX 1 2 0.65 SIDE VIEW 2 1 (0.525) 0.1 SANYO : MFP8(225mil) 0.0 NOM (0.8) 0.85 MAX (1.5) 0.25 SANYO : VSON8(4.0X3.0) Figure 1 Pin Assignments CS SO WP VSS 1 2 3 4 Top view MSOP8 (LE25FS406TT) MFP8 (LE25FS406MA) 8 7 6 5 VDD HOLD SCK SI CS 1 SO 2 WP 3 VSS 4 Top view VSON8N (LE25FS406LF) VSON8 (LE25FS406FQ) 8 VDD 7 HOLD 6 SCK 5 SI No.A1577-2/22 LE25FS406 Figure 2 Block Diagram ADDRESS BUFFERS & LATCHES XDECODER 4M Bit Flash EEPROM Cell Array Y-DECODER CONTROL LOGIC I/O BUFFERS & DATA LATCHES SERIAL INTERFACE CS SCK SI SO WP HOLD Table 1 Pin Description Symbol SCK Pin Name Serial clock This pin controls the data input/output timing. The input data and addresses are latched synchronized to the rising edge of the serial clock, and the data is output synchronized to the falling edge of the serial clock. SI SO CS WP HOLD VDD VSS Serial data input Serial data output Chip select Write protect Hold Power supply Ground The data and addresses are input from this pin, and latched internally synchronized to the rising edge of the serial clock. The data stored inside the device is output from this pin synchronized to the falling edge of the serial clock. The device becomes active when the logic level of this pin is low; it is deselected and placed in standby status when the logic level of the pin is high. The status register write protect (SRWP) takes effect when the logic level of this pin is low. Serial communication is suspended when the logic level of this pin is low. This pin supplies the 1.65 to 2.10V supply voltage. This pin supplies the 0V supply voltage. Description No.A1577-3/22 LE25FS406 Device Operation The read, erase, program and other required functions of the device are executed through the command registers. The serial I/O corrugate is shown in Figure 3 and the command list is shown in Table 2. At the falling CS edge the device is selected, and serial input is enabled for the commands, addresses, etc. These inputs are normalized in 8 bit units and taken into the device interior in synchronization with the rising edge of SCK, which causes the device to execute operation according to the command that is input. The LE25FS406 supports both serial interface SPI mode 0 and SPI mode 3. At the falling CS edge, SPI mode 0 is automatically selected if the logic level of SCK is low, and SPI mode 3 is automatically selected if the logic level of SCK is high. Figure 3 I/O waveforms CS Mode3 SCK Mode0 8CLK SI MSB (Bit7) Farst bass second bass LSB (Bit0) DATA DATA n bass SO Table 2 Command Settings Command Read 1st bus cycle 03h 0Bh Small sector erase Sector erase Chip erase Page program Write enable Write disable Power down Status register read Status register write Read silicon ID 1 *2 Read silicon ID 2 *3 power down Exit power down mode 20h / D7h D8h 60h / C7h 02h 06h 04h B9h 05h 01h 9Fh ABh B9h ABh X X X DATA A23-A16 A15-A8 A7-A0 PD *2 PD *2 PD *2 2nd bus cycle A23-A16 A23-A16 A23-A16 A23-A16 3rd bus cycle A15-A8 A15-A8 A15-A8 A15-A8 4th bus cycle A7-A0 A7-A0 A7-A0 A7-A0 5th bus cycle RD *1 X 6th bus cycle RD *1 RD *1 Nth bus cycle RD *1 RD *1 Explanatory notes for Table 2 "X" signifies "don't care" (that is to say, any value may be input). The "h" following each code indicates that the number given is in hexadecimal notation. Addresses A23 to A19 for all commands are "Don't care". *1: "RD" stands for read data. *2: "PD" stands for page program data. No.A1577-4/22 LE25FS406 Table 2 Command Settings 4M Bit sector(64KB) 7 small sector I27 to I12 I11 to 96 95 to 80 79 to 64 63 to 48 47 to 32 31 to 16 15 to 2 1 0 address space(A23 to A0) 07F000h 07FFFFh 070000h 06F000h 060000h 05F000h 050000h 04F000h 040000h 03F000h 030000h 02F000h 020000h 01F000h 010000h 00F000h 002000h 001000h 000000h 070FFFh 06FFFFh 060FFFh 05FFFFh 050FFFh 04FFFFh 040FFFh 03FFFFh 030FFFh 02FFFFh 020FFFh 01FFFFh 010FFFh 00FFFFh 002FFFh 001FFFh 000FFFh 6 5 4 3 2 1 0 No.A1577-5/22 LE25FS406 Description of Commands and Their Operations A detailed description of the functions and operations corresponding to each command is presented below. 1. Standard SPI read There are two read commands, the standard SPI read command and High-speed read command. 1-1. Read command Consisting of the first through fourth bus cycles, the 4 bus cycle read command inputs the 24-bit addresses following (03h). The data is output from SO on the falling clock edge of fourth bus cycle bit 0 as a reference. "Figure 4-a Read" shows the timing waveforms. Figure 5-a 4 Bus Read CS Mode3 SCK Mode0 8CLK SI 03h Add. Add. Add. N SO High Impedance DATA MSB N+1 DATA MSB N+2 DATA MSB 012345678 15 16 23 24 31 32 39 40 47 1-2. High-speed Read command Consisting of the first through fifth bus cycles, the High-speed read command inputs the 24-bit addresses and 8 dummy bits following (0Bh). The data is output from SO using the falling clock edge of fifth bus cycle bit 0 as a reference. "Figure 4-b High-speed Read" shows the timing waveforms. Figure 4-b High-speed Read CS Mode3 SCK Mode0 8CLK SI MSB N SO High Impedance DATA MSB N+1 DATA MSB N+2 DATA MSB 0Bh Add. Add. Add. X 012345678 15 16 23 24 31 32 39 40 47 48 55 When SCK is input continuously after the read command has been input and the data in the designated addresses has been output, the address is automatically incremented inside the device while SCK is being input, and the corresponding data is output in sequence. If the SCK input is continued after the internal address arrives at the highest address (7FFFFh), the internal address returns to the lowest address (00000h), and data output is continued. By setting the logic level of CS to high, the device is deselected, and the read cycle ends. While the device is deselected, the output pin SO is in a high-impedance state. No.A1577-6/22 LE25FS406 2. Status Registers The status registers hold the operating and setting statuses inside the device, and this information can be read (status register read) and the protect information can be rewritten (status register write). There are 8 bits in total, and "Table 4 Status registers" gives the significance of each bit. Table 4 Status Registers Bit Bit0 Name RDY Logic 0 1 Bit1 WEN 0 1 Bit2 BP0 0 1 Bit3 BP1 0 1 Bit4 BP2 0 1 Bit5 Bit6 Bit7 SRWP 0 1 TB 0 1 Block protect Upper side/Lower side switch Reserved bits Status register write enabled Status register write disabled Nonvolatile information 0 Nonvolatile information Block protect information Protecting area switch Nonvolatile information Function Ready Erase/Program Write disabled Write enabled Nonvolatile information 0 Power-on Time Information 0 Nonvolatile information 2-1. Status register read The contents of the status registers can be read using the status register read command. This command can be executed even during the following operations. • Small sector erase, sector erase, chip erase • Page program • Status register write "Figure 6 Status Register Read" shows the timing waveforms of status register read. Consisting only of the first bus cycle, the status register command outputs the contents of the status registers synchronized to the falling edge of the clock (SCK) with which the eighth bit of (05h) has been input. In terms of the output sequence, SRWP (bit 7) is the first to be output, and each time one clock is input, all the other bits up to RDY (bit 0) are output in sequence, synchronized to the falling clock edge. If the clock input is continued after RDY (bit 0) has been output, the data is output by returning to the bit (SRWP) that was first output, after which the output is repeated for as long as the clock input is continued. The data can be read by the status register read command at any time (even during a program or erase cycle). Figure 6 Status Register Read CS Mode 3 SCK Mode 0 8CLK SI MSB SO High Impedance DATA MSB DATA MSB DATA MSB 05h 012345678 15 16 23 No.A1577-7/22 LE25FS406 2-2. Status register write The information in status registers BP0, BP1, BP2, TB and SRWP can be rewritten using the status register write command. RDY, WEN and bit 6 are read-only bits and cannot be rewritten. The information in bits BP0, BP1, BP2, TB and SRWP is stored in the non-volatile memory, and when it is written in these bits, the contents are retained even at power-down. "Figure 7 Status Register Write" shows the timing waveforms of status register write, and Figure 20 shows a status register write flowchart. Consisting of the first and second bus cycles, the status register write command initiates the internal write operation at the rising CS edge after the data has been input following (01h). Erase and program are performed automatically inside the device by status register write so that erasing or other processing is unnecessary before executing the command. By the operation of this command, the information in bits BP0, BP1, BP2, TB and SRWP can be rewritten. Since bits RDY (bit 0), WEN (bit 1) and bit 6 of the status register cannot be written, no problem will arise if an attempt is made to set them to any value when rewriting the status register. Status register write ends can be detected by RDY of status register read. To initiate status register write, the logic level of the WP pin must be set high and status register WEN must be set to "1". Figure 7 Status Register Write Self-timed Write Cycle tSRW CS tWPS tWPH WP Mode3 SCK Mode0 012345678 15 8CLK SI MSB SO High Impedance 01h DATA 2-3. Contents of each status register RDY (Bit 0) The RDY register is for detecting the write (program, erase and status register write) end. When it is "1", the device is in a busy state, and when it is "0", it means that write is completed. WEN (bit 1) The WEN register is for detecting whether the device can perform write operations. If it is set to "0", the device will not perform the write operation even if the write command is input. If it is set to "1", the device can perform write operations in any area that is not block-protected. WEN can be controlled using the write enable and write disable commands. By inputting the write enable command (06h), WEN can be set to "1"; by inputting the write disable command (04h), it can be set to "0." In the following states, WEN is automatically set to "0" in order to protect against unintentional writing. • At power-on • Upon completion of small sector erase, sector erase or chip erase • Upon completion of page program • Upon completion of status register write * If a write operation has not been performed inside the LE25FS406 because, for instance, the command input for any of the write operations (small sector erase, sector erase, chip erase, page program, or status register write) has failed or a write operation has been performed for a protected address, WEN will retain the status established prior to the issue of the command concerned. Furthermore, its state will not be changed by a read operation. No.A1577-8/22 LE25FS406 BP0, BP1, BP2, TB (Bits 2, 3, 4, 5) Block protect BP0, BP1, BP2 and TB are status register bits that can be rewritten, and the memory space to be protected can be set depending on these bits. For the setting conditions, refer to "Table 5 Protect level setting conditions". BP0, BP1, and BP2 are used to select the protected area and TB to allocate the protected area to the higher-order address area or lower-order address area. Table 5 Protect Level Setting Conditions Status Register Bits Protect Level 0 (Whole area unprotected) T1 (Upper side 1/8 protected) T2 (Upper side 1/4 protected) T3 (Upper side 1/2 protected) B1 (Lower side 1/8 protected) B2 (Lower side 1/4 protected) B3 (Lower side 1/2 protected) 4 (Whole area protected) TB X 0 0 0 1 1 1 X Protected Area BP2 0 0 0 0 1 1 1 1 BP1 0 0 1 1 0 1 1 X BP0 0 1 0 1 1 0 1 X None 07FFFFh to 070000h 07FFFFh to 060000h 07FFFFh to 040000h 00FFFFh to 000000h 01FFFFh to 000000h 03FFFFh to 000000h 07FFFFh to 000000h * Chip erase is enabled only when the protect level is 0. SRWP (bit 7) Status register write protect SRWP is the bit for protecting the status registers, and its information can be rewritten. When SRWP is "1" and the logic level of the WP pin is low, the status register write command is ignored, and status registers BP0, BP1, BP2, TB and SRWP are protected. When the logic level of the WP pin is high, the status registers are not protected regardless of the SRWP state. The SRWP setting conditions are shown in "Table 6 SRWP setting conditions". Table 6 SRWP Setting Conditions WP Pin 0 SRWP 0 1 1 0 1 Status Register Protect State Unprotected Protected Unprotected Unprotected Bit 6 are reserved bits, and have no significance. 3. Write Enable Before performing any of the operations listed below, the device must be placed in the write enable state. Operation is the same as for setting status register WEN to "1", and the state is enabled by inputting the write enable command. "Figure 8 Write Enable" shows the timing waveforms when the write enable operation is performed. The write enable command consists only of the first bus cycle, and it is initiated by inputting (06h). • Small sector erase, sector erase, chip erase • Page program • Status register write No.A1577-9/22 LE25FS406 4. Write Disable The write disable command sets status register WEN to "0" to prohibit unintentional writing. "Figure 9 Write Disable" shows the timing waveforms. The write disable command consists only of the first bus cycle, and it is initiated by inputting (04h). The write disable state (WEN "0") is exited by setting WEN to "1" using the write enable command (06h). Figure 8 Write Enable CS Mode3 SCK Mode0 8CLK SI MSB SO High Impedance SO 06h SI MSB High Impedance CS Figure 9 Write Disable 01234567 SCK Mode3 Mode0 01234567 8CLK 04h 5. Power-down The power-down command sets all the commands, with the exception of the silicon ID read command and the command to exit from power-down, to the acceptance prohibited state (power-down). "Figure 10 Power-down" shows the timing waveforms. The power-down command consists only of the first bus cycle, and it is initiated by inputting (B9h). However, a power-down command issued during an internal write operation will be ignored. The power-down state is exited using the power-down exit command (power-down is exited also when one bus cycle or more of the silicon ID read command (ABh) has been input). "Figure 11 Exiting from Power-down" shows the timing waveforms of the power-down exit command. Figure 10 Power-down Power down mode CS tDP Mode3 SCK Mode0 8CLK SI MSB SO High Impedance SO B9h SI MSB High Impedance 01234567 SCK Mode3 Mode0 8CLK ABh 01234567 CS tPRB Figure 11 Exiting from Power-down Power down mode No.A1577-10/22 LE25FS406 6. Small Sector Erase Small sector erase is an operation that sets the memory cell data in any small sector to "1". A small sector consists of 4Kbytes. "Figure 12 Small Sector Erase" shows the timing waveforms, and Figure 21 shows a small sector erase flowchart. The small sector erase command consists of the first through fourth bus cycles, and it is initiated by inputting the 24-bit addresses following (20h) or (D7h). Addresses A18 to A12 are valid, and Addresses A23 to A19 are "don't care". After the command has been input, the internal erase operation starts from the rising CS edge, and it ends automatically by the control exercised by the internal timer. Erase end can also be detected using status register RDY. Figure 12 Small Sector Erase Self-timed Erase Cycle tSSE CS Mode3 SCK Mode0 8CLK SI MSB SO High Impedance D7h Add. Add. Add. 012345678 15 16 23 24 31 7. Sector Erase Sector erase is an operation that sets the memory cell data in any sector to "1". A sector consists of 64Kbytes. "Figure 13 Sector Erase" shows the timing waveforms, and Figure 21 shows a sector erase flowchart. The sector erase command consists of the first through fourth bus cycles, and it is initiated by inputting the 24-bit addresses following (D8h). Addresses A18 to A16 are valid, and Addresses A23 to A19 are "don't care". After the command has been input, the internal erase operation starts from the rising CS edge, and it ends automatically by the control exercised by the internal timer. Erase end can also be detected using status register RDY. Figure 13 Sector Erase Self-timed Erase Cycle tSE CS Mode3 SCK Mode0 8CLK SI MSB SO High Impedance D8h Add. Add. Add. 012345678 15 16 23 24 31 No.A1577-11/22 LE25FS406 8. Chip Erase Chip erase is an operation that sets the memory cell data in all the sectors to "1". "Figure 14 Chip Erase" shows the timing waveforms, and Figure 21 shows a chip erase flowchart. The chip erase command consists only of the first bus cycle, and it is initiated by inputting (60h) or (C7h). After the command has been input, the internal erase operation starts from the rising CS edge, and it ends automatically by the control exercised by the internal timer. Erase end can also be detected using status register RDY. Figure 14 Chip Erase Self-timed Erase Cycle tCHE CS Mode3 SCK Mode0 8CLK SI MSB SO High Impedance C7h 01234567 9. Page Program Page program is an operation that programs any number of bytes from 1 to 256 bytes within the same sector page (page addresses: A18 to A8). Before initiating page program, the data on the page concerned must be erased using small sector erase, sector erase, or chip erase. "Figure 15 Page Program" shows the page program timing waveforms, and Figure 22 shows a page program flowchart. After the falling CS, edge, the command (02H) is input followed by the 24bit addresses. Addresses A18 to A0 are valid. The program data is then loaded at each rising clock edge until the rising CS edge, and data loading is continued until the rising CS edge. If the data loaded has exceeded 256 bytes, the 256 bytes loaded last are programmed. The program data must be loaded in 1-byte increments, and the program operation is not performed at the rising CS edge occurring at any other timing. Figure 15 Page Program Self-timed Program Cycle tPP CS Mode3 SCK Mode0 8CLK SI MSB SO High Impedance 02h Add. Add. Add. PD PD PD 012345678 15 16 23 24 31 32 39 40 47 2079 No.A1577-12/22 LE25FS406 10. Silicon ID Read ID read is an operation that reads the manufacturer code and device ID information. The silicon ID read command is not accepted during writing. There are two methods of reading the silicon ID, each of which is assigned a device ID. In the first method, the read command sequence consists only of the first bus cycle in which (9Fh) is input. In the subsequent bus cycles, the manufacturer code 62h which is assigned by JEDEC, 2-byte device ID code (memory type, memory capacity), and reserved code are output sequentially. The 4-byte code is output repeatedly as long as clock inputs are present, "Table 7-1 JEDEC ID codes table" lists the silicon ID codes and "Figure 16-a JEDEC ID read" shows the JEDEC ID read timing waveforms. The second method involves inputting the ID read command. This command consists of the first through fourth bus cycles, and the one bite silicon ID can be read when 24 dummy bits are input after (ABh). "Table 7-2 ID codes table" lists the silicon ID codes and "Figure 16-b ID read" shows the ID read timing waveforms. If the SCK input persists after a device code is read, that device code continues to be output. The data output is transmitted starting at the falling edge of the clock for bit 0 in the fourth bus cycle and the silicon ID read sequence is finished by setting CS high. Table 7-1 JEDEC ID read Output code Manufacturer code 2 byte device ID Device code Memory type Memory capacity code 1 62h 16h 13h(4M Bit) 00h 1 byte device ID Table 7-2 ID read Output Code 3E (LE25FS406) Figure 16-a Silicon ID Read 1 CS Mode3 SCK Mode0 012345678 15 16 23 24 31 32 39 8CL SI 9Fh SO High Impedance 62h MSB 16h MSB 13h MSB 00h MSB 62h MSB Figure 16-b Silicon ID Read 2 CS Mode3 SCK Mode0 012345678 15 16 23 24 31 32 39 8CL SI ABh X X X SO High Impedance 3Eh MSB 3Eh MSB No.A1577-13/22 LE25FS406 11. Hold Function Using the HOLD pin, the hold function suspends serial communication (it places it in the hold status). "Figure 17 HOLD" shows the timing waveforms. The device is placed in the hold status at the falling HOLD edge while the logic level of SCK is low, and it exits from the hold status at the rising HOLD edge. When the logic level of SCK is high, HOLD must not rise or fall. The hold function takes effect when the logic level of CS is low, the hold status is exited and serial communication is reset at the rising CS edge. In the hold status, the SO output is in the high-impedance state, and SI and SCK are "don't care". Figure 17 HOLD CS Active tHS HOLD tHS Active SCK tHH HOLD tHHZ SO tHH tHLZ High Impedance 12. Power-on In order to protect against unintentional writing, CS must be within at VDD-0.3 to VDD+0.3 on power-on. After poweron, the supply voltage has stabilized at VDD min. or higher, waits for tPU before inputting the command to start a device operation. The device is in the standby state and not in the power-down state after power is turned on. To put the device into the power-down state, it is necessary to enter a power-down command. Figure 18 Power-on Timing VDD VDD(Max) CS = VDD level Full Access Allowed VDD(Min) tPU 0V No.A1577-14/22 LE25FS406 13. Hardware Data Protection LE25FS406 incorporates a power-on reset function. The following conditions must be met in order to ensure that the power reset circuit will operate stably. No guarantees are given for data in the event of an instantaneous power failure occurring during the writing period. Figure 19 Power-down Timing VDD VDD(Max) VDD(Min) tPD 0V vBOT Power-on timing Parameter Symbol tPU tPD tBOT spec min 100 10 0.2 max unit µs ms V power-on to operation time power-down time power-down voltage 14. Software Data Protection The LE25FS406 eliminates the possibility of unintentional operations by not recognizing commands under the following conditions. • When a write command is input and the rising CS edge timing is not in a bus cycle (8 CLK units of SCK) • When the page program data is not in 1-byte increments • When the status register write command is input for 2 bus cycles or more 15. Decoupling Capacitor A 0.1μF ceramic capacitor must be provided to each device and connected between VDD and VSS in order to ensure that the device will operate stably. No.A1577-15/22 LE25FS406 Specifications Absolute Maximum Ratings Parameter Maximum supply voltage DC voltage (all pins) Storage temperature Tstg Symbol With respect to VSS With respect to VSS Conditions Ratings -0.5 to +2.4 -0.5 to VDD+0.5 -55 to +150 unit V V °C Operating Conditions Parameter Operating supply voltage Operating ambient temperature standard device Temperature enhancing device (at the planning stage) Symbol Conditions Ratings 1.65 to 2.10 0 to 70 -40 to +85 unit V °C Allowable DC Operating Conditions Parameter Read mode operating current Symbol ICCR Conditions min SCK=0.1VDD/0.9VDD, HOLD=WP=0.9VDD, SO=open,25MHz SCK=0.1VDD/0.9VDD, HOLD=WP=0.9VDD, SO=open,30MHz Write mode operating current (erase+page program) CMOS standby current Power-down standby current Input leakage current Output leakage current Input low voltage Input high voltage Output low voltage ISB IDSB ILI ILO VIL VIH VOL IOL=100μA, VDD=VDD min IOL=1.6mA, VDD=VDD min Output high voltage VOH IOH=-100μA, VDD=VDD min VCC-0.2 -0.3 0.7VDD CS=VDD, HOLD=WP=VDD, SI=VSS/VDD, SO=open, CS=VDD, HOLD=WP=VDD, SI=VSS/VDD, SO=open, ICCW tSSE= tSE= tCHE=typ.,tPP=max 8 mA 6 mA Ratings typ max unit 15 50 10 2 2 0.3VDD VDD+0.3 0.2 0.4 mA μA μA μA μA V V V V Data hold, Rewriting frequency Parameter Rewriting frequency Data hold condition Program/Erase Status resister write min 100,000 1,000 20 max unit times/ Sector year Pin Capacitance at Ta=25°C, f=1MHz Parameter Output pin capacitance Input pin Capacitance Symbol CSO CIN VSO=0V VIN=0V Conditions Ratings max 12 6 pF pF unit Note: These parameter values do not represent the results of measurements undertaken for all devices but rather values for some of the sampled devices. No.A1577-16/22 LE25FS406 AC Characteristics Parameter Clock frequency read(03h) other to read(03h) SCK logic high level pulse width SCK logic low level pulse width Input signal rising/falling time CS setup time Data setup time Data hold time CS hold time CS wait pulse width Output high impedance time from CS Output data time from SCK Output data hold time HOLD setup time HOLD hold time Output low impedance time from HOLD Output high impedance time from HOLD WP setup time WP hold time Write status register time Page programming cycle time 256Byte nByte Small sector erase cycle time Sector erase cycle time Chip erase cycle time Power-down time Power-down recovery time Output low impedance time from SCK tSSE tSE tCHE tDP tPRB tCLZ 0 tCLHI tCLLO tRF tCSS tDS tDH tCSH tCPH tCHZ tV tHO tHS tHH tHLZ tHHZ tWPS tWPH tSRW tPP 20 20 8 6 0.15+ N*5.85/356 0.04 0.08 0.3 10 8 0.20+ n*7.80/256 0.15 0.25 3.0 5 5 s s s μs μs ns 1 5 5 12 9 10 14 14 0.1 10 5 5 10 25 15 14 Symbol min fCLK Ratings typ max 25 30 MHz MHz ns ns V/ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ms ms unit Timing waveforms Serial Input Timing tCPH CS tCLS SCK tDS SI tDH tCSS tCLHI tCLLO tCSH tCLH DATA VALID SO High Impedance High Impedance No.A1577-17/22 LE25FS406 Serial Output Timing CS SCK tCLZ SO tHO tCHZ DATA VALID tV SI Hold Timing CS tHH tHS tHH tHS SCK HOLD tHHZ tHLZ High Impedance SO Status resistor write Timing CS tWPS tWPH WP AC Test Conditions Input pulse level··············· 0.2VDD to 0.8VDD Input rising/falling time···· 5ns Input timing level············· 0.3VDD, 0.7VDD Output timing level ·········· 1/2×VDD Output load ······················ 15pF Note: As the test conditions for "typ", the measurements are conducted using 1.8V for VDD at room temperature. input level input / output timing level 0.7VDD 1/2VDD 0.2VDD 0.3VDD 0.8VDD No.A1577-18/22 LE25FS406 Figure 20 Status Register Write Flowchart Status register write Start 06h Write enable 01h Set status register write command Data Program start on rising edge of CS 05h Set status register read command NO Bit 0= “0” ? YES End of status register write * Automatically placed in write disabled state at the end of the status register write No.A1577-19/22 LE25FS406 Figure 21 Erase Flowcharts Sector erase Small sector erase Start Start 06h Write enable 06h Write enable 20h / D7h D8h Set sector erase command Address 1 Set small sector erase command Address 1 Address 2 Address 2 Address 3 Address 3 Start erase on rising edge of CS Start erase on rising edge of CS 05h Set status register read command 05h Set status register read command NO NO Bit 0 = “0” ? YES Bit 0 = “0” ? YES End of erase End of erase * Automatically placed in write disabled state at the end of the erase * Automatically placed in write disabled state at the end of the erase No.A1577-20/22 LE25FS406 Figure 22 Page Program Flowchart Chip erase Start Page program Start 06h 06h Write enable Write enable 60h / C7h Set chip erase command 02h Set page program command Address 1 Start erase on rising edge of CS Address 2 05h Set status register read command Address 3 Data 0 Bit 0 = “0” ? YES NO Data n End of erase Start program on rising edge of CS * Automatically placed in write disabled state at the end of the erase NO 05h Set status register read command Bit 0= “0” ? YES End of programming * Automatically placed in write disabled state at the end of the programming operation. No.A1577-21/22 LE25FS406 SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein. SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO Semiconductor Co.,Ltd. products described or contained herein are controlled under any of applicable local export control laws and regulations, such products may require the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written consent of SANYO Semiconductor Co.,Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO Semiconductor Co.,Ltd. product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. Upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third party. SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's intellectual property rights which has resulted from the use of the technical information and products mentioned above. This catalog provides information as of January, 2011. Specifications and information herein are subject to change without notice. PS No.A1577-22/22