LE25FU206

Ordering number : ENA1191B LE25FU206 Overview CMOS IC 2M-bit (256K×8) Serial Flash Memory The LE25FU206 is a serial interface-compatible flash memory device with a 256K × 8-bit configuration. It uses a single 2.5V power supply for both reading and writing (program and erase functions) and does not require a special power supply. As such, it can support on-board programming. It has three erase functions, each of which corresponds to the size of the memory area in which the data is to be erased at one time: the small sector (4K bytes) erase function, the sector (64K bytes) erase function, and the chip erase function (for erasing all the data together). The memory space can be efficiently utilized by selecting one of these functions depending on the application. A page program method is supported for data writing. The page program method of the LE25FU206 can program any amount of data from 1 to 256 bytes. The program time of 2.0ms (typ.) when programming 256 bytes (1 page) at one time makes for fast data writing. While making the most of the features inherent to a serial flash memory device, the LE25FU206 is housed in an 8-pin ultraminiature package. Serial flash memory devices tend to be at a disadvantage in terms of their read speed, but the LE25FU206 has maximally eliminated this speed-related disadvantage by supporting clocks with frequencies up to 30MHz under SPI bus specifications. All these features make this device ideally suited to storing program codes in applications such as portable information devices and small disk systems, which are required to have increasingly more compact dimensions. Features • Read/write operations enabled by single 2.5V power supply: 2.30 to 3.60V supply voltage range • Operating frequency : 30MHz • Temperature range : 0 to 70°C -40 to +85°C (at the planning stage) Continued on next page. * This product is licensed from Silicon Storage Technology, Inc. (USA), and manufactured and sold by SANYO Semiconductor Co., Ltd. Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment. The products mentioned herein shall not be intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee thereof. If you should intend to use our products for new introduction or other application different from current conditions on the usage of automotive device, communication device, office equipment, industrial equipment etc. , please consult with us about usage condition (temperature, operation time etc.) prior to the intended use. If there is no consultation or inquiry before the intended use, our customer shall be solely responsible for the use. Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer ' s products or equipment. 91411 SY 20110715-S00002/10511 SY/60408 SY IM No.A1191-1/21 LE25FU206 Continued from preceding page. • Serial interface : SPI mode 0, mode 3 supported • Sector size : 4K bytes/small sector, 64K bytes/sector • Small sector erase, sector erase, chip erase functions • Page program function (256 bytes/page) • Block protect function • Highly reliable read/write Number of rewrite times : 10,000 times Small sector erase time : 40ms (typ.), 150ms (max.) Sector erase time : 80ms (typ.), 250ms (max.) Chip erase time : 160ms (typ.), 1.6s (max.) Page program time : 2.0ms/256 bytes (typ.), 2.5ms/256 bytes (max.) • Status functions Ready/busy information, protect information • Data retention period : 20 years • Package : LE25FU206TT MSOP8 (225mil) : LE25FU206MA MFP8 (225mil) Package Dimensions unit:mm (typ) 3276 5.2 8 5 Package Dimensions [LE25FU206TT] unit:mm (typ) 3032E 5.0 8 [LE25FU206MA] 4.4 6.3 4.4 6.4 1 (0.7) 1.27 4 0.35 0.85max 1 (0.6) 0.125 2 1.27 0.35 0.15 (0.65) 0.08 SANYO : MSOP8(225mil) SANYO : MFP8(225mil) Figure 1 Pin Assignments CS SO WP VSS 1 2 3 4 Top view 8 7 6 5 VDD HOLD SCK SI MSOP8 (LE25FU206TT) MFP8 (LE25FU206MA) 0.1 (1.5) 1.7 MAX 0.63 0.5 No.A1191-2/21 LE25FU206 Figure 2 Block Diagram ADDRESS BUFFERS & LATCHES XDECODER 2M Bit Flash EEPROM Cell Array Y-DECODER CONTROL LOGIC I/O BUFFERS & DATA LATCHES SERIAL INTERFACE CS SCK SI SO WP HOLD Table 1 Pin Description Symbol SCK Pin Name Serial clock This pin controls the data input/output timing. The input data and addresses are latched synchronized to the rising edge of the serial clock, and the data is output synchronized to the falling edge of the serial clock. SI SO CS WP HOLD VDD VSS Serial data input Serial data output Chip select Write protect Hold Power supply Ground The data and addresses are input from this pin, and latched internally synchronized to the rising edge of the serial clock. The data stored inside the device is output from this pin synchronized to the falling edge of the serial clock. The device becomes active when the logic level of this pin is low; it is deselected and placed in standby status when the logic level of the pin is high. The status register write protect (SRWP) takes effect when the logic level of this pin is low. Serial communication is suspended when the logic level of this pin is low. This pin supplies the 2.30 to 3.60V supply voltage. This pin supplies the 0V supply voltage. Description No.A1191-3/21 LE25FU206 Table 2 Command Settings Command Read 1st bus cycle 03h 0Bh Small sector erase Sector erase Chip erase Page program Write enable Write disable Power down Status register read Status register write Read silicon ID 1 *2 Read silicon ID 2 *3 Exit power down mode D7h D8h C7h 02h 06h 04h B9h 05h 01h 9Fh ABh ABh X X A7-A0 DATA A23-A16 A15-A8 A7-A0 PD *1 PD *1 PD *1 2nd bus cycle A23-A16 A23-A16 A23-A16 A23-A16 3rd bus cycle A15-A8 A15-A8 A15-A8 A15-A8 4th bus cycle A7-A0 A7-A0 A7-A0 A7-A0 X 5th bus cycle 6th bus cycle Nth bus cycle Explanatory notes for Table 2 "X" signifies "don't care" (that is to say, any value may be input). The "h" following each code indicates that the number given is in hexadecimal notation. Addresses A23 to A18 for all commands are "Don't care". In order for commands other than the read command to be recognized, CS must rise after all the bus cycle input. *1: "PD" stands for page program data. Any amount of data from 1 to 256 bytes in 1-byte unit is input. *2: Of the two silicon ID commands, it is for the command with the 9Fh setting that the manufacturer code 62h is first output. For as long as the clock input is continued, 44h of the device code is output continuously, followed by the repeated output of 62h and 44h. *3: Of the two silicon ID commands, it is for the command with the ABh setting that manufacturer code 62h is first output when address A0 is "0", and the device code 44h is first output when address A0 is "1". Addresses A7 to A1 are "don't care". For as long as the clock input is continued, 62h and 44h are repeatedly output. No.A1191-4/21 LE25FU206 Device Operation The LE25FU206 features electrical on-chip erase functions using a single 2.5V power supply, that have been added to the EPROM functions of the industry standard that support serial interfaces. Interfacing and control are facilitated by incorporating the command registers inside the chip. The read, erase, program and other required functions of the device are executed through the command registers. The command addresses and data input in accordance with "Table 2 Command Settings" are latched inside the device in order to execute the required operations. "Figure 3 Serial Input Timing" shows the timing waveforms of the serial data input. First, at the falling CS edge the device is selected, and serial input is enabled for the commands, addresses, etc. These inputs are introduced internally in sequence starting with bit 7 in synchronization with the rising SCK edge. At this time, output pin SO is in the high-impedance state. The output pin is placed in the low-impedance state when the data is output in sequence starting with bit 7 synchronized to the falling clock edge during read, status register read and silicon ID. Refer to "Figure 4 Serial Output Timing" for the serial output timing. The LE25FU206 supports both serial interface SPI mode 0 and SPI mode 3. At the falling CS edge, SPI mode 0 is automatically selected if the logic level of SCK is low, and SPI mode 3 is automatically selected if the logic level of SCK is high. Figure 3 Serial Input Timing tCPH CS tCLS SCK tDS SI tDH tCSS tCLHI tCLLO tCSH tCLH DATA VALID SO High Impedance High Impedance Figure 4 Serial Output Timing CS SCK tCLZ SO tHO tCHZ DATA VALID tV SI No.A1191-5/21 LE25FU206 Description of Commands and Their Operations "Table 2 Command Settings" provides a list and overview of the commands. A detailed description of the functions and operations corresponding to each command is presented below. 1. Read There are two read commands, the 4 bus cycle read command and 5 bus cycle read command. Consisting of the first through fourth bus cycles, the 4 bus cycle read command inputs the 24-bit addresses following (03h), and the data in the designated addresses is output synchronized to SCK. The data is output from SO on the falling clock edge of fourth bus cycle bit 0 as a reference. "Figure 5-a 4 Bus Read" shows the timing waveforms. Consisting of the first through fifth bus cycles, the 5 bus cycle read command inputs the 24-bit addresses and 8 dummy bits following (0Bh). The data is output from SO using the falling clock edge of fifth bus cycle bit 0 as a reference. "Figure 5-b 5 Bus Read" shows the timing waveforms. The only difference between these two commands is whether the dummy bits in the fifth bus cycle are input. When SCK is input continuously after the read command has been input and the data in the designated addresses has been output, the address is automatically incremented inside the device while SCK is being input, and the corresponding data is output in sequence. If the SCK input is continued after the internal address arrives at the highest address (3FFFFh), the internal address returns to the lowest address (00000h), and data output is continued. By setting the logic level of CS to high, the device is deselected, and the read cycle ends. While the device is deselected, the output pin SO is in a high-impedance state. Figure 5-a 4 Bus Read CS Mode3 SCK Mode0 012345678 15 16 23 24 31 32 39 40 47 8CLK SI 03h Add. Add. Add. N SO High Impedance DATA MSB N+1 DATA MSB N+2 DATA MSB Figure 5-b 5 Bus Read CS Mode3 SCK Mode0 8CLK SI 0Bh Add. Add. Add. X N SO High Impedance DATA MSB N+1 DATA MSB N+2 DATA MSB 012345678 15 16 23 24 31 32 39 40 47 48 55 No.A1191-6/21 LE25FU206 2. Status Registers The status registers hold the operating and setting statuses inside the device, and this information can be read (status register read) and the protect information can be rewritten (status register write). There are 8 bits in total, and "Table 3 Status registers" gives the significance of each bit. Table 3 Status Registers Bit Bit0 Name RDY Logic 0 1 0 Bit1 WEN 1 0 Bit2 BP0 1 0 Bit3 Bit4 Bit5 Bit6 0 Bit7 SRWP 1 Status register write disabled Status register write enabled Nonvolatile information Reserved bits BP1 1 0 0 0 Block protect information See status register descriptions on BP0 and BP1. Nonvolatile information Nonvolatile information Write enabled Function Ready 0 Erase/Program Write disabled 0 Power-on Time Information 2-1. Status Register Read The contents of the status registers can be read using the status register read command. This command can be executed even during the following operations. • Small sector erase, sector erase, chip erase • Page program • Status register write "Figure 6 Status Register Read" shows the timing waveforms of status register read. Consisting only of the first bus cycle, the status register command outputs the contents of the status registers synchronized to the falling edge of the clock (SCK) with which the eighth bit of (05h) has been input. In terms of the output sequence, SRWP (bit 7) is the first to be output, and each time one clock is input, all the other bits up to RDY (bit 0) are output in sequence, synchronized to the falling clock edge. If the clock input is continued after RDY (bit 0) has been output, the data is output by returning to the bit (SRWP) that was first output, after which the output is repeated for as long as the clock input is continued. The data can be read by the status register read command at any time (even during a program or erase cycle). Figure 6 Status Register Read CS Mode 3 SCK Mode 0 8CLK SI 05h 012345678 15 16 23 SO High Impedance DATA MSB DATA MSB DATA MSB No.A1191-7/21 LE25FU206 2-2. Status Register Write The information in status registers BP0, BP1, and SRWP can be rewritten using the status register write command. RDY, WEN, bit 4, bit 5, and bit 6 are read-only bits and cannot be rewritten. The information in bits BP0, BP1, and SRWP is stored in the non-volatile memory, and when it is written in these bits, the contents are retained even at powerdown. "Figure 7 Status Register Write" shows the timing waveforms of status register write, and Figure 20 shows a status register write flowchart. Consisting of the first and second bus cycles, the status register write command initiates the internal write operation at the rising CS edge after the data has been input following (01h). Erase and program are performed automatically inside the device by status register write so that erasing or other processing is unnecessary before executing the command. By the operation of this command, the information in bits BP0, BP1, and SRWP can be rewritten. Since bits RDY (bit 0), WEN (bit 1), bit 4, bit 5, and bit 6 of the status register cannot be written, no problem will arise if an attempt is made to set them to any value when rewriting the status register. Status register write ends can be detected by RDY of status register read. Information in the status registers can be rewritten 1,000 times (min.). To initiate status register write, the logic level of the WP pin must be set high and status register WEN must be set to "1". Figure 7 Status Register Write Self-timed Write Cycle tSRW CS tWPS tWPH WP Mode3 SCK Mode0 012345678 15 8CLK SI 01h DATA SO High Impedance 2-3. Contents of Each Status Register RDY (bit 0) The RDY register is for detecting the write (program, erase and status register write) end. When it is "1", the device is in a busy state, and when it is "0", it means that write is completed. No.A1191-8/21 LE25FU206 WEN (bit 1) The WEN register is for detecting whether the device can perform write operations. If it is set to "0", the device will not perform the write operation even if the write command is input. If it is set to "1", the device can perform write operations in any area that is not block-protected. WEN can be controlled using the write enable and write disable commands. By inputting the write enable command (06h), WEN can be set to "1"; by inputting the write disable command (04h), it can be set to "0". In the following states, WEN is automatically set to "0" in order to protect against unintentional writing. • At power-on • Upon completion of small sector erase, sector erase or chip erase • Upon completion of page program • Upon completion of status register write * If a write operation has not been performed inside the LE25FU206 because, for instance, the command input for any of the write operations (small sector erase, sector erase, chip erase, page program, or status register write) has failed or a write operation has been performed for a protected address, WEN will retain the status established prior to the issue of the command concerned. Furthermore, its state will not be changed by a read operation. BP0, BP1 (bits 2, 3) Block protect BP0 and BP1 are status register bits that can be rewritten, and the memory space to be protected can be set depending on these bits. For the setting conditions, refer to "Table 4 Protect level setting conditions". Table 4 Protect Level Setting Conditions Status Register Bits Protect Level BP1 0 (Whole area unprotected) 1 (1/4 protected) 2 (1/2 protected) 3 (Whole area protected) 0 0 1 1 BP0 0 1 0 1 None 30000h to 3FFFFh 20000h to 3FFFFh 00000h to 3FFFFh Protected Area * Chip erase is enabled only when the protect level is 0. SRWP (bit 7) Status register write protect SRWP is the bit for protecting the status registers, and its information can be rewritten. When SRWP is "1" and the logic level of the WP pin is low, the status register write command is ignored, and status registers BP0, BP1, and SRWP are protected. When the logic level of the WP pin is high, the status registers are not protected regardless of the SRWP state. The SRWP setting conditions are shown in "Table 5 SRWP setting conditions". Table 5 SRWP Setting Conditions WP Pin 0 1 0 1 1 Unprotected Protected Unprotected SRWP 0 Status Register Protect State Unprotected Bits 4, Bits 5, and Bits 6 are reserved bits, and have no significance. No.A1191-9/21 LE25FU206 3. Write Enable Before performing any of the operations listed below, the device must be placed in the write enable state. Operation is the same as for setting status register WEN to "1", and the state is enabled by inputting the write enable command. "Figure 8 Write Enable" shows the timing waveforms when the write enable operation is performed. The write enable command consists only of the first bus cycle, and it is initiated by inputting (06h). • Small sector erase, sector erase, chip erase • Page program • Status register write 4. Write Disable The write disable command sets status register WEN to "0" to prohibit unintentional writing. "Figure 9 Write Disable" shows the timing waveforms. The write disable command consists only of the first bus cycle, and it is initiated by inputting (04h). The write disable state (WEN "0") is exited by setting WEN to "1" using the write enable command (06h). Figure 8 Write Enable CS Mode3 SCK Mode0 8CLK SI 06h SI CS Figure 9 Write Disable 01234567 SCK Mode3 Mode0 01234567 8CLK 04h SO High Impedance SO High Impedance 5. Power-down The power-down command sets all the commands, with the exception of the silicon ID read command and the command to exit from power-down, to the acceptance prohibited state (power-down). "Figure 10 Power-down" shows the timing waveforms. The power-down command consists only of the first bus cycle, and it is initiated by inputting (B9h). However, a power-down command issued during an internal write operation will be ignored. The power-down state is exited using the power-down exit command (power-down is exited also when one bus cycle or more of the silicon ID read command (ABh) has been input). "Figure 11 Exiting from Power-down" shows the timing waveforms of the power-down exit command. Figure 10 Power-down Power down mode CS tDP Mode3 SCK Mode0 8CLK SI B9h SI 01234567 SCK Mode3 Mode0 8CLK ABh 01234567 CS tPRB Figure 11 Exiting from Power-down Power down mode SO High Impedance SO High Impedance No.A1191-10/21 LE25FU206 6. Small Sector Erase Small sector erase is an operation that sets the memory cell data in any small sector to "1". A small sector consists of 4Kbytes. "Figure 12 Small Sector Erase" shows the timing waveforms, and Figure 21 shows a small sector erase flowchart. The small sector erase command consists of the first through fourth bus cycles, and it is initiated by inputting the 24-bit addresses following (D7h). Addresses A17 to A12 are valid, and Addresses A23 to A18 are "don't care". After the command has been input, the internal erase operation starts from the rising CS edge, and it ends automatically by the control exercised by the internal timer. Erase end can also be detected using status register RDY. Figure 12 Small Sector Erase Self-timed Erase Cycle tSSE CS Mode3 SCK Mode0 8CLK SI D7h Add. Add. Add. 012345678 15 16 23 24 31 SO High Impedance 7. Sector Erase Sector erase is an operation that sets the memory cell data in any sector to "1". A sector consists of 64Kbytes. "Figure 13 Sector Erase" shows the timing waveforms, and Figure 21 shows a sector erase flowchart. The sector erase command consists of the first through fourth bus cycles, and it is initiated by inputting the 24-bit addresses following (D8h). Addresses A17 to A16 are valid, and Addresses A23 to A18 are "don't care". After the command has been input, the internal erase operation starts from the rising CS edge, and it ends automatically by the control exercised by the internal timer. Erase end can also be detected using status register RDY. Figure 13 Sector Erase Self-timed Erase Cycle tSE CS Mode3 SCK Mode0 8CLK SI D8h Add. Add. Add. 012345678 15 16 23 24 31 SO High Impedance No.A1191-11/21 LE25FU206 8. Chip Erase Chip erase is an operation that sets the memory cell data in all the sectors to "1". "Figure 14 Chip Erase" shows the timing waveforms, and Figure 21 shows a chip erase flowchart. The chip erase command consists only of the first bus cycle, and it is initiated by inputting (C7h). After the command has been input, the internal erase operation starts from the rising CS edge, and it ends automatically by the control exercised by the internal timer. Erase end can also be detected using status register RDY. Figure 14 Chip Erase Self-timed Erase Cycle tCHE CS Mode3 SCK Mode0 8CLK SI C7h 01234567 SO High Impedance 9. Page Program Page program is an operation that programs any number of bytes from 1 to 256 bytes within the same sector page (page addresses: A17 to A8). Before initiating page program, the data on the page concerned must be erased using small sector erase, sector erase, or chip erase. "Figure 15 Page Program" shows the page program timing waveforms, and Figure 22 shows a page program flowchart. After the falling CS, edge, the command (02H) is input followed by the 24-bit addresses. Addresses A17 to A0 are valid. The program data is then loaded at each rising clock edge until the rising CS edge, and data loading is continued until the rising CS edge. If the data loaded has exceeded 256 bytes, the 256 bytes loaded last are programmed. The program data must be loaded in 1-byte increments, and the program operation is not performed at the rising CS edge occurring at any other timing. The page program time is 2.0ms (typ.) when 256 bytes (1 page) are programmed at one time. Figure 15 Page Program Self-timed Program Cycle tPP CS Mode3 SCK Mode0 8CLK SI 02h Add. Add. Add. PD PD PD 012345678 15 16 23 24 31 32 39 40 47 2079 SO High Impedance No.A1191-12/21 LE25FU206 10. Silicon ID Read Silicon ID read is an operation that reads the manufacturer code and device code information. "Table 6 Silicon ID codes table" lists the silicon ID codes. The silicon ID read command is not accepted during writing. Two methods are used for silicon ID reading. The first method involves inputting the 9Fh command: the setting is completed with only the first bus cycle input, and in subsequent bus cycles the manufacturer code 62h and device code 44h are repeatedly output in succession so long as the clock input is continued. Refer to "Figure 16-a Silicon ID read 1" for the waveforms. The second method involves inputting the ABh command. This command consists of the first through fourth bus cycles, and the silicon ID can be read when 16 dummy bits and an 8-bit address are input after (ABh). When address A0 is "0", the manufacturer code 62h is read in the fifth bus cycle, and the device code 44h is read in the sixth bus cycle. "Figure 16-b Silicon ID read 2" shows the timing waveforms. If, after the manufacturer code or device code has been read, the SCK input is continued, the manufacturer code and device code are output alternately with each bus cycle. When address A0 is "1", reading starts with device code 44h in the fifth bus cycle. Table 6 Silicon ID Codes Address A0 Manufacturer code Device code 0 1 Output Code 62h 44h The data is output starting with the falling clock edge of the fourth bus cycle bit 0, and silicon ID reading ends at the rising CS edge. Figure 16-a Silicon ID Read 1 CS Mode3 SCK Mode0 012345678 15 16 23 8CLK SI 9Fh N SiID MSB N+1 SiID MSB N SiID MSB High Impedance SO Figure 16-b Silicon ID Read 2 CS Mode3 SCK Mode0 012345678 15 16 23 24 31 32 39 40 47 8CLK SI ABh X X Add. N SO High Impedance SiID MSB N+1 SiID MSB N SiID MSB No.A1191-13/21 LE25FU206 11. Hold Function Using the HOLD pin, the hold function suspends serial communication (it places it in the hold status). "Figure 17 HOLD" shows the timing waveforms. The device is placed in the hold status at the falling HOLD edge while the logic level of SCK is low, and it exits from the hold status at the rising HOLD edge. When the logic level of SCK is high, HOLD must not rise or fall. The hold function takes effect when the logic level of CS is low, the hold status is exited and serial communication is reset at the rising CS edge. In the hold status, the SO output is in the high-impedance state, and SI and SCK are "don't care". Figure 17 HOLD CS Active tHS HOLD tHS Active SCK tHH HOLD tHHZ SO tHH tHLZ High Impedance 12. Power-on In order to protect against unintentional writing, CS must be kept at VCC At power-on. After power-on, the supply voltage has stabilized at 2.30V or higher, wait for 100μs (tPU_READ) before inputting the command to start a read operation. Similarly, wait for 10ms (tPU_WRITE) after the voltage has stabilized before inputting the command to start a write operation. Figure 18 Power-on Timing Program, Erase and Write Command not Allowed VDD VDD(Max) Full Access Allowed Chip selection not Allowed Read Access Allowed VDD(Min) tPU_READ tPU_WRITE 0V No.A1191-14/21 LE25FU206 13. Hardware Data Protection In order to protect against unintentional writing at power-on, the LE25FU206 incorporates a power-on reset function. The following conditions must be met in order to ensure that the power reset circuit will operate stably. No guarantees are given for data in the event of an instantaneous power failure occurring during the writing period. Figure 19 Power-down Timing Program, Erase and Write Command not Allowed VDD VDD(Max) No Device Access Allowed VDD(Min) tPU_READ tPU_WRITE tPD 0V vBOT 14. Software Data Protection The LE25FU206 eliminates the possibility of unintentional operations by not recognizing commands under the following conditions. • When a write command is input and the rising CS edge timing is not in a bus cycle (8 CLK units of SCK) • When the page program data is not in 1-byte increments • When the status register write command is input for 2 bus cycles or more 15. Decoupling Capacitor A 0.1μF ceramic capacitor must be provided to each device and connected between VDD and VSS in order to ensure that the device will operate stably. No.A1191-15/21 LE25FU206 Specifications Absolute Maximum Ratings Parameter Maximum supply voltage DC voltage (all pins) Storage temperature Tstg Symbol With respect to VSS With respect to VSS Conditions Ratings -0.5 to +4.6 -0.5 to VDD+0.5 -55 to +150 unit V V °C Operating Conditions Parameter Operating supply voltage Operating ambient temperature Symbol Conditions Ratings 2.30 to 3.60 0 to 70 -40 to +85 (at the planning stage) unit V °C Allowable DC Operating Conditions Ratings Parameter Read mode operating current Symbol ICCR Conditions min CS=0.1VDD, HOLD=WP=0.9VDD SI=0.1VDD/0.9VDD, SO=open operating frequency=30MHz, Write mode operating current (erase+page program) CMOS standby current ISB ICCW VDD=VDD max VDD=VDD max, tSSE=40ms, tSE=80ms, tCHE=160ms, tPP=2.5ms CS=HOLD=WP=VDD, SI=VSS/VDD, SO=open, VDD=VDD max CS=HOLD=WP=VDD, SI=VSS/VDD, SO=open, Input leakage current Output leakage current Input low voltage Input high voltage Output low voltage ILI ILO VIL VIH VOL VDD=VDD max VIN=VSS to VDD, VDD=VDD max VIN=VSS to VDD, VDD=VDD max VDD=VDD max VDD=VDD min IOL=100μA, VDD=VDD min IOL=1.6mA, VDD=VDD min Output high voltage VOH IOH=-100μA, VDD=VDD min VCC-0.2 -0.3 0.7VDD 10 2 2 0.3VDD VDD+0.3 0.2 V 0.4 V μA μA μA V V 50 μA 15 mA typ max unit 6 mA Power-down standby current IDSB Power-on Timing Ratings Parameter Time from power-on to read operation Time from power-on to write operation Power-down time Power-down voltage tPU_READ tPU_WRITE tPD vBOT Symbol min 100 10 10 0.2 max μs ms ms V unit Pin Capacitance at Ta=25°C, f=1MHz Ratings Parameter Output pin capacitance Input pin capacitance Symbol CDQ CIN VDQ=0V VIN=0V Conditions max 12 6 pF pF unit Note: These parameter values do not represent the results of measurements undertaken for all devices but rather values for some of the sampled devices. No.A1191-16/21 LE25FU206 AC Characteristics Ratings Parameter Clock frequency SCK logic high level pulse width SCK logic low level pulse width Input signal rising/falling time CS setup time SCK setup time Data setup time Data hold time CS hold time SCK hold time CS wait pulse width Output high impedance time from CS Output data time from SCK Output data hold time HOLD setup time HOLD hold time Output low impedance time from HOLD Output high impedance time from HOLD WP setup time WP hold time Write status register time Page programming cycle time Small sector erase cycle time Sector erase cycle time Chip erase cycle time Power-down time Power-down recovery time Output low impedance time from SCK Symbol min fCLK tCLHI tCLLO tRF tCSS tCLS tDS tDH tCSH tCLH tCPH tCHZ tV tHO tHS tHH tHLZ tHHZ tWPS tWPH tSRW tPP tSSE tSE tCHE tDP tPRB tCLZ 0 20 20 5 2.0 0.04 0.08 0.16 15 2.5 0.15 0.25 1.6 3 3 1 7 3 9 9 10 10 10 5 5 10 10 25 15 15 16 16 20 typ max 30 MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ms s s s μs μs ns unit AC Test Conditions Input pulse level ··············· 0V, 2.5V Input rising/falling time···· 5ns Input timing level ············· 0.3VDD, 0.7VDD Output timing level ·········· 1/2×VDD Output load ······················ 30pF Note: As the test conditions for "typ," the measurements are conducted using 2.5V for VDD at room temperature. No.A1191-17/21 LE25FU206 Figure 20 Status Register Write Flowchart Status register write Start 06h Write enable 01h Set status register write command Data Program start on rising edge of CS 05h Set status register read command NO Bit 0= “0” ? YES End of status register write * Automatically placed in write disabled state at the end of the status register write No.A1191-18/21 LE25FU206 Figure 21 Erase Flowcharts Sector erase Small sector erase Start Start 06h Write enable 06h Write enable D7h D8h Set sector erase command Address 1 Set small sector erase command Address 1 Address 2 Address 2 Address 3 Address 3 Start erase on rising edge of CS Start erase on rising edge of CS 05h Set status register read command 05h Set status register read command NO NO Bit 0 = “0” ? YES Bit 0 = “0” ? YES End of erase End of erase * Automatically placed in write disabled state at the end of the erase * Automatically placed in write disabled state at the end of the erase No.A1191-19/21 LE25FU206 Figure 22 Page Program Flowchart Chip erase Start Page program Start 06h 06h Write enable Write enable C7h Set chip erase command 02h Set page program command Address 1 Start erase on rising edge of CS Address 2 05h Set status register read command Address 3 Data 0 Bit 0 = “0” ? YES NO Data n End of erase Start program on rising edge of CS * Automatically placed in write disabled state at the end of the erase NO 05h Set status register read command Bit 0= “0” ? YES End of programming * Automatically placed in write disabled state at the end of the programming operation. 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Upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third party. SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's intellctual property rights which has resulted from the use of the technical information and products mentioned above. This catalog provides information as of September, 2011. Specifications and information herein are subject to change without notice. PS No.A1191-21/21