LV0221CS

Ordering number : ENA1823 Monolithic Linear IC LV0221CS Overview For Optical Pickups Front Monitor OE-IC The LV0221CS is a front monitor optoelectronic IC for optical pickups that has a built-in photo diode compatible with three waveforms. LV0221CS is small size and type CSP packages. Functions • PIN photodiode compatible with three wavelengths incorporated. • Gain adjustment (-6dB to +6dB in 256 steps) through serial communication. • Amplifier to amplify differential output. Specifications Parameter Maximum Ratings at Ta = 25°C Symbol VCC Pd1 Pd2 Operating temperature Storage temperature Topr Tstg Glass epoxy one-side substrate 55mm × 45mm × 0.8mm Copper foil area (about 80%), Ta=75˚C Glass epoxy one-side substrate 55mm × 45mm × 0.8mm Copper foil area (head: about 85% Tail: about 90%), Ta=75˚C -20 to +85 -40 to +100 ˚C ˚C 100 mW Conditions Ratings 6 136 Unit V mW Maximum supply voltage Allowable power dissipation Recommended Operating Conditions at Ta = 25°C Parameter Operating supply voltage Output load capacitance Output load resistance Symbol VCC CO ZO Conditions min 4.5 12 3 Ratings typ 5 20 max 5.5 33 V pF kΩ Unit Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment (home appliances, AV equipment, communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee thereof. If you should intend to use our products for applications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our customer shall be solely responsible for the use. Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer' s products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer' s products or equipment. 82510 SY 20100803-S00005 No.A1823-1/6 LV0221CS Electrical Characteristics at Ta = 25°C, VCC = 5V, RL=6kΩ, CL=20pF Parameter Current dissipation Sleep current Output voltage when shielded Output offset voltage Temperature dependence of offset voltage *1 Optical output voltage *1 Voltage between VOP-VON Symbol ICC Islp VC Vofs Vofs VLC VLD VLB VMC VMD VMB VHC VHD VHB Light output voltage adjustment range *1 D range *1 Frequency characteristics *1, *2 G VoD FcC FcD FcB Settling time *1 Response time *1 Overshoot *1 Undershoot *1 Linearity *1 Light-output voltage temperature dependence Voltage between VOP-VON *1, *3 Tset Tr, Tf Ovst Unst Lin TC TD TB Light-output voltage spectral sensitivity Voltage between VOP-VON *1 Vf Vo=0.9Vp-p, output level 10 to 90% fc=10MHz, duty=50% Vo=0.9Vp-p Vo=0.9Vp-p At output voltage 0.5V and 1.0V (Between VOP-VON) λ=780nm, 25˚C reference λ=650nm, 25˚C reference λ=405nm, 25˚C reference λ=785nm ±10nm λ=660nm ±10nm λ=405nm ±10nm Step-step voltage ratio *1 DG (Vn-Vn-1) / Vn *100 *4 Deviation from the ideal curve of above equation Item with *1 mark indicate the design reference value. Item with *2 mark indicate the frequency characteristics when VOP and VON are applied individually. The frequency characteristics are for the case of High / Middle / Low gain and for the case when the output voltage adjustment range is -6 to +6dB Item with *3 mark indicates the temperature dependence for the case of High / Middle / Low gain and for the case when the temperature is 25 to 85˚C for the output voltage adjustment range of -6 to +6dB Vn in Item with *4 mark is Vn = (sensitivity / 2 ) × 5400 / (5400-16 × GCAstep ) × light intensity (μW) GCA = Gain Control Amplifier 10 0 0 -0.8 -0.4 0 -3 0 13 3 3 16 6 6 0.1 0.4 1.2 3 % % % %/nm %/nm %/nm % -1 0 15 15 1 % % % At shielding At shielding, voltage between VOP-VON Ta=-10 to +85˚C Low Gain, λ=780nm, G=0dB Low Gain, λ=650nm, G=0dB Low Gain, λ=405nm, G=0dB Middle Gain, λ=780nm, G=0dB Middle Gain, λ=650nm, G=0dB Middle Gain, λ=405nm, G=0dB High Gain, λ=780nm, G=0dB High Gain, λ=650nm, G=0dB High Gain, λ=405nm, G=0dB G=0dB reference, absolute value of adjustment width Voltage between VOP-VON -3dB(1MHz reference), λ=780nm Light input = 40μW(DC) + 20μW(AC) -3dB(1MHz reference), λ=650nm Light input = 40μW(DC) + 20μW(AC) -3dB(1MHz reference), λ=405nm Light input = 40μW(DC) + 20μW(AC) 15 10 ns ns 60 85 MHz 60 85 MHz 1.8 -30 -60 0.21 0.22 0.14 0.66 0.70 0.43 1.97 2.07 1.29 5.5 1700 50 2.0 0 0 0.262 0.275 0.172 0.83 0.87 0.54 2.46 2.58 1.62 6.0 2200 75 Conditions min Ratings typ 18 max 23.4 1 2.2 30 60 0.31 0.33 0.21 0.99 1.05 0.65 2.95 3.10 1.94 6.5 mA mA V mV μV/˚C mV/μW mV/μW mV/μW mV/μW mV/μW mV/μW mV/μW mV/μW mV/μW dB mV MHz Unit No.A1823-2/6 LV0221CS Package Dimensions unit : mm (typ) 3402 TOP VIEW SIDE VIEW 0.275 BOTTOM VIEW 0.55 1.75 0.875 3 1.75 2 1 A B SIDE VIEW C 0.68 MAX C B A 0.1 (0.52) SANYO : ODCSP8(1.75X1.75) Pin Assignment TOP VIEW Pin No. 1A 1B 1C 2A 2C 1 0.875 0.55 2 3 Pin name SDIO VOP VON SCLK SSEL Function Serial communication Data pin Positive side output pin Negative side output pin Serial communication Clock pin Register selection pin SSEL = Low, Open : Address 00 to 0Fh used SSEL = High : Address 10 to 1Fh used 3 SEN GND VCC 2 SCLK SSEL 1 SDIO VOP VON 3A 3B 3C SEN GND VCC Serial communication Enable pin GND pin Power supply voltage pin A B C PD assignment 1.75mm 0.875mm Center of PD 0.875mm *PD size for reference to be used for design 1.75mm No.A1823-3/6 LV0221CS Block diagram and Test circuit diagram Control VCC SEN SCLK SDIO SSEL VCC Low Middle High + + Serial Vref Bias Regulator Vo+ GND Vref VoVref Resister table Enable selection of the register group from the SSEL pin. SSEL = Low, Open Address Name Default Value 00h 7 POWER 00 11: Power on 00 01 10: Sleep Name Default Value Name Default Value Name Default Value Name Name 0Eh 0Fh 03h 1 1 1 1 TEST1 (*1) TEST2 (*1) 02h 1 1 1 1 CD GAIN 1 1 1 1 00000000 to 11111111 01h 1 1 1 1 DVD GAIN 1 1 1 1 00000000 to 11111111 6 5 IV GAIN SEL 00 00 01: High 10: Middle 11: Low BD GAIN 1 1 1 1 00000000 to 11111111 4 3 GAIN SEL 00 00 01: BD 10: DVD 11: CD x x 2 1 0 SSEL = High Address Name Default Value 10h 7 POWER 00 11: Power on 00 01 10: Sleep Name Default Value Name Default Value Name Default Value Name Name 1Eh 1Fh 13h 1 1 1 1 TEST1 (*1) TEST2 (*1) 12h 1 1 1 1 CD GAIN 1 1 1 1 00000000 to 11111111 11h 1 1 1 1 DVD GAIN 1 1 1 1 00000000 to 11111111 6 5 IV GAIN SEL 00 00 01: High 10: Middle 11: Low BD GAIN 1 1 1 1 00000000 to 11111111 4 3 GAIN SEL 00 00 01: BD 10: DVD 11: CD x x 2 1 0 *1 TEST1 and TEST2 are either the time when power is applied or “00000000” is set. Do not attempt to change “00000000” during operation. “00000000” is returned when reading is made. *2 No problem in terms of operation occurs even when writing is made to the address 04h to 0Dh and 14h to 1Dh. “00000000” is returned when this address is read. 20pF 20pF No.A1823-4/6 LV0221CS Serial protocol WRITE timing chart (HOST) SEN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 (HOST) SCLK MSB LSB MSB LSB (HOST) SDIO A7 Mode A6 A5 A4 A3 Address A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 Data (Output Data from Host) READ timing chart (HOST) SEN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 (HOST) SCLK MSB LSB (HOST) SDIO A7 Mode A6 A5 A4 A3 Address A2 A1 A0 MSB LSB SDIO D7 D6 D5 D4 D3 D2 D1 D0 Data (Output Data from Host) SDIO pin load / CL=20pF (The table below shows the design reference value.) Parameter SCL clock frequency Write SCL clock frequency Read SDIO data setup time SDIO data hold time SDIO output delay SEN “H” period SEN “L” period SCL rise time after SEN rise SEN fall time after final SCL rise Serial input “H” voltage Serial input “L” voltage SDIO output “H” voltage SDIO output “L” voltage Symbol fSCL fSCL tDSU tDHO tDDLY tENH tENL tSTA tSTO VIH VIL VOH VOL Min. 0 0 50 50 10 1.6 200 60 100 2.4 0.6 2.5 0 2.9 0.3 3.3 0.8 80 Typ. Max. 10 4 Unit MHz MHz ns ns ns μs ns ns ns V V V V WRITE (HOST) SEN tSTA tENH tENL tSTO (HOST) SCLK (HOST) SDIO tDSU tDHO READ (HOST) SEN (HOST) SCLK (HOST) SDIO tDDLY SDIO No.A1823-5/6 LV0221CS Pin SDIO Input Output Type Equivalent circuit diagram 3V 3V VOP VON Output SCLK SSEL SEN Input SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein. SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all semiconductor products fail or malfunction with some probability. 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SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's intellctual property rights which has resulted from the use of the technical information and products mentioned above. This catalog provides information as of August, 2010. Specifications and information herein are subject t o change without notice. PS No.A1823-6/6