Ordering number : ENA1919
Monolithic Linear IC
LV0223CV
Overview
For Optical Pickups
Front Monitor OE-IC
The LV0223CV is a front monitor optoelectronic IC for optical pickups that has a built-in photo diode compatible with three waveforms. LV0223CV is small size and type CSP packages.
Functions
• PIN photodiode compatible with three wavelengths incorporated. • Gain adjustment (-6dB to +6dB in 256 steps) through serial communication. • Amplifier to amplify differential output.
Specifications
Parameter
Maximum Ratings at Ta = 25°C
Symbol VCC Pd Topr Tstg Glass epoxy both-side substrate 55mm × 45mm × 1.6mm Copper foil area (head: about 90% Tail: about 90%), Ta=75˚C Operating temperature Storage temperature -20 to +75 -40 to +100 ˚C ˚C Conditions Ratings 6 143 Unit V mW Maximum supply voltage Allowable power dissipation
Recommended Operating Conditions at Ta = 25°C
Parameter Operating supply voltage Output load capacitance Output load resistance Symbol VCC CO ZO Conditions min 4.5 12 3 Ratings typ 5 20 max 5.5 33 V pF kΩ Unit
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20911 SY 20110127-S00004 No.A1919-1/8
LV0223CV
Electrical Characteristics at Ta = 25°C, VCC = 5V, RL=6kΩ, CL=20pF
Parameter Current dissipation Sleep current Output voltage when shielded Output offset voltage Temperature dependence of offset voltage *1 Optical output voltage *1 Voltage between VOP-VON Symbol ICC Islp VC Vofs Vofs VLC VLD VLB VM1C VM1D VM1B VM2C VM2D VM2B VH1C VH1D VH1B VH2C VH2D VH2B Light output voltage adjustment range *1 D range *1 Frequency characteristics *1, *2 G VoD FcC FcD1 At shielding At shielding, voltage between VOP-VON Ta=-10 to +75˚C Low Gain, λ=780nm, G=0dB Low Gain, λ=650nm, G=0dB Low Gain, λ=405nm, G=0dB Middle1 Gain, λ=780nm, G=0dB Middle1 Gain, λ=650nm, G=0dB Middle1 Gain, λ=405nm, G=0dB Middle2 Gain, λ=780nm, G=0dB Middle2 Gain, λ=650nm, G=0dB Middle2 Gain, λ=405nm, G=0dB High1 Gain, λ=780nm, G=0dB High1 Gain, λ=650nm, G=0dB High1 Gain, λ=405nm, G=0dB High2 Gain, λ=780nm, G=0dB High2 Gain, λ=650nm, G=0dB High2 Gain, λ=405nm, G=0dB G=0dB reference, absolute value of adjustment width Voltage between VOP-VON -3dB(1MHz reference), λ=780nm Light input = 40μW(DC) + 20μW(AC) -3dB(1MHz reference), λ=650nm Light input = 40μW(DC) + 20μW(AC) Low/Middle1/2 Gain FcD2 -3dB(1MHz reference), λ=650nm Light input = 40μW(DC) + 20μW(AC) High1/2 Gain FcB1 -3dB(1MHz reference), λ=405nm Light input = 40μW(DC) + 20μW(AC) Low/Middle1/2 Gain FcB2 -3dB(1MHz reference), λ=405nm Light input = 40μW(DC) + 20μW(AC) High1/2 Gain Settling time *1 Response time *1 Overshoot *1 Undershoot *1 Linearity *1 Light-output voltage temperature dependence Voltage between VOP-VON *1, *3 Tset Tr, Tf Ovst Unst Lin TC TD TB Item with *1 mark indicate the design reference value. Item with *2 mark indicate the frequency characteristics when VOP and VON are applied individually. The frequency characteristics are for the output voltage adjustment range is -6 to +6dB Item with *3 mark indicates the temperature dependence for the case of High2 / High1 / Middle2 / Middle1 / Low gain and for the case when the temperature is 25 to 75˚C for the output voltage adjustment range of -6 to +6dB [Expression of output voltage] VN = (sensitivity / 2 ) × 5400 / (5400-16 × GCAstep ) × light intensity (μW) Vo=0.9Vp-p, output level 10 to 90% fc=10MHz, duty=50% Vo=0.9Vp-p, G=0dB Vo=0.9Vp-p, G=0dB At output voltage 0.5V and 1.0V (Between VOP-VON) λ=780nm, 25˚C reference λ=650nm, 25˚C reference λ=405nm, 25˚C reference 7 -1 -1 10 2 2 13 5 5 % % % -1 0 15 15 1 % % % 10 4 15 10 ns ns 60 80 MHz 60 85 MHz 60 80 MHz 60 85 MHz 1.85 -30 -60 0.21 0.22 0.14 0.66 0.70 0.43 1.97 2.07 1.29 3.35 3.52 2.20 5.72 6.02 3.76 5.5 1700 60 2.0 0 0 0.262 0.275 0.172 0.83 0.87 0.54 2.46 2.58 1.62 4.19 4.40 2.75 7.15 7.52 4.70 6.0 2200 80 Conditions min 13.3 Ratings typ 17 max 22.1 0.6 2.15 30 60 0.31 0.33 0.21 0.99 1.05 0.65 2.95 3.10 1.94 5.02 5.28 3.30 8.58 9.02 5.64 6.5 mA mA V mV μV/˚C mV/μW mV/μW mV/μW mV/μW mV/μW mV/μW mV/μW mV/μW mV/μW mV/μW mV/μW mV/μW mV/μW mV/μW mV/μW dB mV MHz Unit
No.A1919-2/8
LV0223CV
Package Dimensions
unit : mm (typ) 3407
TOP VIEW SIDE VIEW 0.2 BOTTOM VIEW 0.5
3
1.45
3
1.45
2
1
0.5
A
B SIDE VIEW
C
0.67 MAX
C
B
A
0.08
(0.52)
SANYO : ODCSP8(1.45X1.45)
Pin Assignment
TOP VIEW
Pin No. 1A 1B 1C 2A 2C
1
2
Pin name SDIO VOP VON SCLK SSEL
Function Serial communication Data pin Positive side output pin Negative side output pin Serial communication Clock pin Register selection pin SSEL = Low : Address 00 to 0Fh used
3
SEN
GND
VCC
2
SCLK
SSEL
1
SDIO
VOP
VON
SSEL = High : Address 10 to 1Fh used SSEL = Open : Address 70 to 7Fh used 3A 3B 3C SEN GND VCC Serial communication Enable pin GND pin Power supply voltage pin
A
B
C
PD assignment
1.45mm
0.725mm
Center of PD
0.725mm
*PD size for reference to be used for design
1.45mm
No.A1919-3/8
LV0223CV
Block diagram and Test circuit diagram
Control VCC
High2 VCC High1 Middle2 Middle1 Low
+ +
SEN SCLK SDIO SSEL
Serial
Vref Bias Regulator
Vo+
20pF
GND
Vref
VoVref
20pF
Resister table
Enable selection of the register group from the SSEL pin. SSEL = Low
Address Name Default Value 00h 7 POWER 00 11: Power on 00/01/10: Sleep Name Default Value Name Default Value Name Default Value Name Name 0Eh 0Fh 03h 1 1 1 1 TEST1 (*1) TEST2 (*1) 02h 1 1 1 1 CD GAIN 1 1 1 1 00000000 to 11111111 01h 1 1 1 1 DVD GAIN 1 1 1 1 00000000 to 11111111 BD GAIN 1 1 1 1 00000000 to 11111111 6 5 IV GAIN SEL 00 *4 4 3 GAIN SEL 00 00/01: BD 10: DVD 11: CD 2 1 IV GAIN2 1 *4 0 0
SSEL = High
Address Name Default Value 10h 7 POWER 00 11: Power on 00/01/10: Sleep Name Default Value Name Default Value Name Default Value Name Name 1Eh 1Fh 13h 1 1 1 1 TEST1 (*1) TEST2 (*1) Continued on next page. 12h 1 1 1 1 CD GAIN 1 1 1 1 00000000 to 11111111 11h 1 1 1 1 DVD GAIN 1 1 1 1 00000000 to 11111111 BD GAIN 1 1 1 1 00000000 to 11111111 6 5 IV GAIN SEL 00 *4 4 3 GAIN SEL 00 00/01: BD 10: DVD 11: CD 2 1 IV GAIN2 1 *4 0 0
No.A1919-4/8
LV0223CV
Continued from preceding page.
SSEL = Open
Address Name Default Value 70h 7 POWER 00 11: Power on 00/01/10: Sleep Name Default Value Name Default Value Name Default Value Name Name 7Eh 7Fh 73h 1 1 1 1 TEST1 (*1) TEST2 (*1) 72h 1 1 1 1 CD GAIN 1 1 1 1 00000000 to 11111111 71h 1 1 1 1 DVD GAIN 1 1 1 1 00000000 to 11111111 BD GAIN 1 1 1 1 00000000 to 11111111 6 5 IV GAIN SEL 00 *4 4 3 GAIN SEL 00 00/01: BD 10: DVD 11: CD 2 1 IV GAIN2 1 *4 0 0
*1 TEST1 and TEST2 are either the time when power is applied or “00000000” is set. Do not attempt to change “00000000” during operation. “00000000” is returned when reading is made. *2 No problem in terms of operation occurs even when writing is made to the address 04h to 0Dh and 14h to 1Dh and 74h to 7Dh. “00000000” is returned when this address is read. *3 When I performed address reading except the register group set by an SSEL terminal, I keep Hi-Z without paying a value. *4 Please set the gain setting of the I/V amplifier referring to the table below.
I/V amplifier gain setting table
00h/10h/70h Name Default High2 High1 IV GAIN Middle2 Middle1 Low 5 4 IV GAIN1 SET 00 00/01 10/11 00/01 10 11 1 IV GAIN2 1 1 1 0 0 0
No.A1919-5/8
LV0223CV
Serial protocol
WRITE timing chart (HOST) SEN
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
(HOST) SCLK
MSB LSB MSB LSB
(HOST) SDIO
A7
Mode
A6
A5
A4
A3
Address
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
Data (Output Data from Host)
READ timing chart (HOST) SEN
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
(HOST) SCLK
MSB LSB
(HOST) SDIO
A7
Mode
A6
A5
A4
A3
Address
A2
A1
A0
MSB LSB
SDIO
D7
D6
D5
D4
D3
D2
D1
D0
Data (Output Data from Host)
SDIO pin load / CL=20pF (The table below shows the design reference value.)
Parameter SCL clock frequency Write SCL clock frequency Read SDIO data setup time SDIO data hold time SDIO output delay SEN “H” period SEN “L” period SCL rise time after SEN rise SEN fall time after final SCL rise Serial input “H” voltage Serial input “L” voltage SDIO output “H” voltage SDIO output “L” voltage Symbol fSCL fSCL tDSU tDHO tDDLY tENH tENL tSTA tSTO VIH VIL VOH VOL Min. 0 0 50 50 10 1.6 200 60 100 2.4 2.5 0 2.9 0.3 3.7 0.6 3.3 0.8 80 Typ. Max. 10 4 Unit MHz MHz ns ns ns μs ns ns ns V V V V
WRITE (HOST) SEN
tSTA
tENH
tENL
tSTO
(HOST) SCLK
(HOST) SDIO
tDSU tDHO
READ (HOST) SEN
(HOST) SCLK
(HOST) SDIO
tDDLY
SDIO
No.A1919-6/8
LV0223CV
Pin SDIO Input Output Type Equivalent circuit diagram
3V
3V
VOP VON
Output
SCLK SEN
Input
3V
SSEL
Input
No.A1919-7/8
LV0223CV
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This catalog provides information as of February, 2011. Specifications and information herein are subject to change without notice. PS No.A1919-8/8
