Ordering number : ENA1046
Bi-CMOS IC
LV1117N/NV
Overview
Surround Processor ICs for
Electronic Volume Control
The LV1117N/NV are sound processor ICs developed for use in TV sets. They incorporate the surround processing functions including (AViSS), pseudo stereo function, (L+R) output, and the major functional blocks of an electronic volume control IC.
Features
• Input function SW (4ch stereo inputs [L, R]). • Line out (through output). • Input gain control (−6dB, −4dB, 0dB, 4dB, 6dB: 5 positions). • AViSS (ON/OFF/6-stage level control). • Tone control (BASS: ±20dB, TREBLE: ±18dB [in 2dB steps]). • Volume control (0dB to −14dB: 1dB step/−14dB to −80dB: 2dB steps/−∞=−82dB). • Balance control. • Through mode/Mute mode. • Pseudo stereo function (ON/OFF/MONO). • L+R output with LPF (Mute + 7-stage level control: 8 positions). • I2C bus control. • Parallel output ports (4pin). * Initial gain of L+R AMP can be controlled by the resistance value of external resistor.
Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment (home appliances, AV equipment, communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee thereof. If you should intend to use our products for applications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our customer shall be solely responsible for the use. Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer' s products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer' s products or equipment.
22008 TI IM 20051207-S00008 No.A1046-1/18
LV1117N/1117NV
Specifications
Maximum Ratings at Ta = 25°C
Parameter Maximum supply voltage Allowable power dissipation 1 Allowable power dissipation 2 Operating temperature Storage temperature Symbol VCC max Pd max1 Pd max2 Topr Tstg Ta ≤ 70°C, DIP Ta ≤ 70°C *, SSOP Conditions Ratings 10.5 700 700 -25 to +70 -40 to +125 Unit V mW mW °C °C
Note *: Mounted on a specified board: 114.3mm×76.1mm×1.6mm, glass epoxy board Operating Condtions at Ta = 25°C
Parameter Recommended supply voltage Operating supply voltage 1 Operating supply voltage 2 Control data “H” level voltage “L” level voltage Pulse width Hold time Operating frequency VIH VIL tφw thold fopg 2.0 to 5.5 0.0 to 1.0 1.0 1.0 100 V V μs μs kHz Symbol VCC VCC opg1 VCC opg2 DIP SSOP Conditions Ratings 9.0 5.0 to 10.0 5.0 to 9.0 Unit V V V
Electrical Characteristics at Ta = 25°C, VCC = 9.0V, fin = 1kHz, VIN = 300mVrms = 0dB, RL = 10kΩ (Input=L/Rch-A, Output=L/R-VROUT)
Parameter Quiescent current Symbol ICCO VGT VOT THDT VNOT CTT VGF VOM THDM VNOM CTM VOS THDS VNOS VOS THDS VNOS VOS THDS VNOS THD=1% DIN AUDIO DIN AUDIO DIN AUDIO 85 THD=1% DIN AUDIO DIN AUDIO DIN AUDIO 85 -1.6 2.0 Conditions Ratings min typ 48 max Unit mA
Total through (Total through mode, Volume control: 0dB) Voltage gain Maximum output voltage Total harmonic distortion Output noise voltage Cross talk -0.6 2.6 0.03 -93 93 0.1 -85 +0.6 dB Vrms % dBV dB
Matrix through (Matrix mode, Input gain: 0dB, Volume control: 0dB) Voltage gain Maximum output voltage Total harmonic distortion Output noise voltage Cross talk -1.7 1.5 -0.7 2.0 0.04 -92 91 0.1 -83 +0.7 dB Vrms % dBV dB
MONO mode (MONO mode, Input gain: 0dB, Volume control: 0dB) Maximum output voltage Total harmonic distortion Output noise voltage THD=1% DIN AUDIO DIN AUDIO 1.5 2.0 0.04 -92 0.5 -82 Vrms % dBV
Surround (Surround mode-A, Input gain: 0dB, Volume control: 0dB) Maximum output voltage Total harmonic distortion Output noise voltage THD=1% DIN AUDIO DIN AUDIO 1.5 2.0 0.2 -90 0.5 -81 Vrms % dBV
Pseudo stereo (Pseudo stereo mode, Input gain: 0dB, Volume control: 0dB) Maximum output voltage Total harmonic distortion Output noise voltage THD=1% DIN AUDIO DIN AUDIO 1.5 2.0 0.07 -90 0.5 -82 Vrms % dBV
Continued on next page.
No.A1046-2/18
LV1117N/1117NV
Continued from preceding page.
Parameter Symbol Conditions Ratings min ±17 1.0 typ ±20 2.0 max ±23 3.0 Unit
Bass band EQ (Matrix through mode, Input gain: 0dB, Volume control: 0dB) Control Range Step resolution GeqB EstepB GeqT EstepT VGF VOF THDF VNOF VOL IO THD=1% DIN AUDIO DIN AUDIO Max. Boost/Cut Max. Boost/Cut dB dB
Treble band EQ (Matrix through mode, Input gain: 0dB, Volume control: 0dB) Control Range Step resolution ±15 1.0 ±18 2.0 ±21 3.0 dB dB
L+R output (Output=L+R-OUT, Step=0dB, L+R_Step=Step4) Voltage gain Maximum output voltage Total harmonic distortion Output noise voltage Port Output (20/21/22/23pin) Low level output voltage Port output sink Current IO=1mA 0.3 1.0 V mA -2.3 2.0 -1.3 2.5 0.03 -99 0.1 -85 -0.3 dB Vrms % dBV
Note: The output wave form becomes big depending on the surround or tone control setting. Please make sure the output waveform is not distorted. If the waveform is distorted, reduce the gain setting of surround, tone control, or input signal level.
Package Dimensions
unit : mm (typ) 3025C
37.7
[LV1117N]
42
22
0.95
3.8 5.1max (4.25)
0.51min
1.78
0.48
(1.05)
SANYO : DIP42S(600mil)
0.25
1
21
15.24
13.8
No.A1046-3/18
LV1117N/1117NV
Package Dimensions
unit : mm (typ) 3277
15.0 44 23
[LV1117NV]
5.6
7.6
1 (0.68)
0.65
0.22
22
0.2
SANYO : SSOP44(275mil)
0.1
(1.5) 1.7max
0.5
No.A1046-4/18
AGND HPFC 34 28 26 25 24 33 32 31 30 29 27 23 L-TC1 40 38 39 37 36 35
Lch-A
Lch-B
Lch-C
Lch-D L-DC ST-2 L-BC1 L+R LPF CLK DATA OUT0
L Line out L-BC2 L-OUT L-VRIN VSS
42
41
TONE CONT DC DATA CONTROL CONTROL + Matrix Bypass Bypass MUTE TOTAL + -
Block Diagram [LV1117N]
Pseud Stereo (AViSS) SURROUND
ANALOG + -
LV1117N/1117NV
+ Bypass Matrix
Bypass TOTAL
DC TONE CONT
1 3 5 6 R-DC 7 Rch-D R Line out Rch-B Rch-C 4
2
8 ST-1
9
10 LPFC R-TC1
11 R-BC1
12
13
GND
Rch-A
R-BC2 R-OUT R-VRIN +
+ OUT1 22 + MUTE 14 15 L+R 16 17 VREF 18 VCC 19 VDD 20 OUT2 21 OUT3
No.A1046-5/18
AGND HPFC 36 30 28 26 27 25 35 34 33 32 31 29 24 L-TC1 41 40 39 38 37
Lch-A
Lch-B
Lch-C
Lch-D L-DC ST-2 L-BC1 L+R LPF CLK NC DATA OUT0
L Line out L-BC2 L-OUT L-VRIN VSS
44
43
42
TONE CONT DC CONTROL + Matrix Bypass Bypass MUTE TOTAL + DATA CONTROL
Block Diagram [LV1117NV]
Pseud Stereo (AViSS) SURROUND
ANALOG + -
LV1117N/1117NV
+ Bypass Bypass Matrix
TOTAL
DC TONE CONT
1 4 5 6 R-DC ST-1 7 8 Rch-D R Line out Rch-C
2
3
9
10
11 R-BC1
12
13
GND
Rch-A
Rch-B
LPFC R-TC1
R-BC2 R-OUT R-VRIN +
+ OUT1 23 + MUTE 14 15 L+R 16 17 VREF 18 VCC 19 NC 20 VDD 21 OUT2 22 OUT3
No.A1046-6/18
LV1117N/1117NV
I2C BUS Control Signal
tHIGH tR tF SCL tLOW tHD:DAT tSU:DAT
tSU:STA SDA
tHD:STA
tSU:STO
tBUF
Figure1 I2C BUS Control Signal timing chart
I2C BUS register
1) The explanation of I2C Bus I2C Bus (Inter IC Bus) is the bus system which the PHILIPS company developed. It does controls such as the start, the stop by two control signals of SDA (Serial Data) and SCL (Serial Clock). The output of each signal is open drain and forms out of wired OR.
S: Start condition P: Stop condition ACK: Acknowledge Data is transmitted in the MSB first. 1 unit is composed of 8 bits and ACK is put back from the slave to confirm. Slave IC reads data with rising edge of SCL. Master IC changes data by falling edge in SCL. 2) The control register Table1 Slave Address
MSB 1 1 1 0 1 1 1 LSB 0
Note; LV1117N/NV are reception exclusive use. It depends and it uses LSB by the "0" fixation. Table2 I2C Bus transmission
Function Input control/Gain control Volume control Output/Surround/MODE control Tone control [Bass] Tone control [TREBLE] Output port control Sub Address BINARY 0000 0001 0000 0010 0000 0011 0000 0100 0000 0101 0000 0110 HEX 01 02 03 04 05 06 0 0 0 D7 0 D6 0 D5 D4 Gain Volume Surround 0 0 0 0 OUT3 Bass TREBLE OUT2 OUT1 OUT0 MODE Data D3 D2 D1 Input D0
Channel L+R out gain 0 0 0
Table3 Input Selection
Sub Address A7 Mute In A In B In C In D 0 0 0 0 0 0 0 1 A6 A5 A4 A3 A2 A1 A0 D7 0 0 0 0 0 D6 0 0 0 0 0 D5 * * * * * D4 * * * * * Data D3 * * * * * D2 0 0 0 0 1 D1 0 0 1 1 0 D0 0 1 0 1 0
No.A1046-7/18
LV1117N/1117NV
Table4 Gain control
Sub Address A7 -6dB -4dB 0dB +4dB +6dB 0 0 0 0 0 0 0 1 A6 A5 A4 A3 A2 A1 A0 D7 0 0 0 0 0 D6 0 0 0 0 0 D5 0 0 0 1 1 D4 1 1 0 1 1 Data D3 1 0 0 0 1 D2 * * * * * D1 * * * * * D0 * * * * *
Table5 Mode control
Sub Address A7 Total Matrix Mono Pseudo 0 0 0 0 0 0 1 1 A6 A5 A4 A3 A2 A1 A0 D7 * * * * D6 * * * * D5 * * * * D4 * * * * Data D3 * * * * D2 * * * * D1 0 0 1 1 D0 0 1 0 1
Table6 Surround control
Sub Address A7 OFF MODE-C MODE-B MODE-A MODE-F MODE-E MODE-D * * * 0 0 0 0 0 0 1 1 A6 A5 A4 A3 A2 A1 A0 D7 * * * * D6 * * * * D5 * * * * D4 0 0 0 0 1 1 1 Data D3 0 1 1 0 1 1 0 D2 0 1 0 1 1 0 1 * * D1 * * * * D0 * * * *
Note; At the time of forced mono mode, there is not surround effect. Note; Output gain = Step1 < Step7 Table7 L+R Output Gain control
Sub Address A7 MUTE Step1 Step2 Step3 Step4 Step5 Step6 Step7 0 0 0 0 0 0 1 1 A6 A5 A4 A3 A2 A1 A0 D7 0 0 0 0 1 1 1 1 D6 0 0 1 1 0 0 1 1 D5 0 1 0 1 0 1 0 1 D4 * * * * * * * * Data D3 * * * * * * * * D2 * * * * * * * * D1 * * * * * * * * D0 * * * * * * * *
Note; Output gain = Step1 < Step7
No.A1046-8/18
LV1117N/1117NV
Table8 Tone control [Bass control]
Sub Address A7 +20dB +18dB +16dB +14dB +12dB +10dB +8dB +6dB +4dB +2dB 0dB -2dB -4dB -6dB -8dB -10dB -12dB -14dB -16dB -18dB -20dB 0 0 0 0 0 1 0 0 A6 A5 A4 A3 A2 A1 A0 D7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D4 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 Data D3 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 D2 0 0 0 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 0 0 0 D1 1 0 0 1 1 0 0 1 1 0 0 0 1 1 0 0 1 1 0 0 1 D0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
Table9 Tone control [TREBLE control]
Sub Address A7 +18dB +16dB +14dB +12dB +10dB +8dB +6dB +4dB +2dB 0dB -2dB -4dB -6dB -8dB -10dB -12dB -14dB -16dB -18dB 0 0 0 0 0 1 0 1 A6 A5 A4 A3 A2 A1 A0 D7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D4 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 Data D3 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 D2 0 0 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 0 0 D1 0 0 1 1 0 0 1 1 0 0 0 1 1 0 0 1 1 0 0 D0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
No.A1046-9/18
LV1117N/1117NV
Table10 Volume control
Sub Address A7 0dB -1dB -2dB -3dB -4dB -5dB -6dB -7dB -8dB -9dB -10dB -11dB -12dB -13dB -14dB -16dB -18dB -20dB -22dB -24dB -26dB -28dB -30dB -32dB -34dB -36dB -38dB -40dB -42dB -44dB -46dB -48dB -50dB -52dB -54dB -56dB -58dB -60dB -62dB -64dB -66dB -68dB -70dB -72dB -74dB -76dB -78dB -80dB -∞dB 0 0 0 0 0 0 1 0 A6 A5 A4 A3 A2 A1 A0 D7 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * D6 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * D5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 D4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Data D3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 D2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 D1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 D0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
No.A1046-10/18
LV1117N/1117NV
Table11 Volume channel control
Sub Address A7 L-ch R-ch L/R 0 0 0 0 0 0 1 0 A6 A5 A4 A3 A2 A1 A0 D7 0 1 1 D6 1 0 1 D5 * * * D4 * * * Data D3 * * * D2 * * * D1 * * * D0 * * *
Table12 Output port control
Sub Address A7 On (sink) Off (open) 0 A6 0 A5 0 A4 0 A3 0 A2 1 A1 1 A0 0 D7 0 0 D6 0 0 D5 0 0 D4 0 0 Data D3 0 1 D2 0 1 D1 0 1 D0 0 1
Pin Functions [LV1117N]
Pin No 1 2 41 3 40 4 39 5 38 6 GND INPUT-A(R) INPUT-A(L) INPUT-B(R) INPUT-B(L) INPUT-C(R) INPUT-C(L) INPUT-D(R) INPUT-D(L) LINE-OUT(R) VREF Function SW Output ro=700Ω Function Voltage 0 VREF Input Impedance ri=50kΩ Remarks Internal equivalent circuit
37
LINE-OUT(L)
7
DC Cut(R)
VREF
DC offset cancellation capacitor connection pin
36
DC Cut(L)
8
ST-1
VREF
Pseudo stereo phase shift capacitor connection pin
35
ST-2
9
AViSS LPF
VREF
Capacitor connection pin for surround low pass filter
Continued on next page.
No.A1046-11/18
LV1117N/1117NV
Continued from preceding page.
Pin No 10 Function TREBLE(R) Voltage VREF treble filter Remarks Capacitor connection pin for configuring Internal equivalent circuit
33
TREBLE(L)
11 32 12 31 13
BASS-1(R) BASS-1(L) BASS-2(R) BASS-2(L) OUT(R)
VREF
Bass band filter configuration capacitor and resistor connection pins
VREF
Output Impedance ro=100Ω
30
OUT(L)
14
EVR-IN(R)
VREF
Input Impedance ri=50kΩ
29
EVR-IN(L)
15
EVR-OUT(R)
VREF
Output Impedance ro=100Ω
28
EVR-OUT(L)
16
L+R OUT
VREF
Output Impedance ro=10kΩ
17
VREF
0.5VCC
Reference voltage
VCC
Continued on next page.
No.A1046-12/18
LV1117N/1117NV
Continued from preceding page.
Pin No 18 19 20 21 22 23 24 25 26 27 VCC VDD Output 2 Output 3 Output 1 Output 0 I2C-DATA I2C-CLK VSS L+R LPF 0 VREF Internal resistor I2C control data input Function Voltage VCC VDD Nch open drain port output Remarks Internal equivalent circuit
34
AViSS HPF
VREF
42
ANALOG GND
VREF
No.A1046-13/18
LV1117N/1117NV
Treble / Bass Band Block Equivalent Circuit Diagram
From L-Input Block + SW2 SW1 0dB ±2dB ±4dB ±6dB ±8dB ±10dB ±12dB ±14dB ±16dB ±18dB R1=10.633kΩ R2=8.446kΩ R3=6.709kΩ R4=5.329kΩ R5=4.233kΩ R6=3.363kΩ R7=2.671kΩ R8=2.122kΩ R9=1.665kΩ R10=6.510kΩ Total=51.7kΩ 0dB ±2dB ±4dB ±6dB ±8dB ±10dB ±12dB ±14dB ±16dB ±18dB ±20dB R12=100Ω L-TC1 L-BC2 R1=15.220kΩ R2=12.089kΩ R3=9.603kΩ R4=7.628kΩ R5=6.059kΩ R6=4.813kΩ R7=3.823kΩ R8=3.037kΩ R9=2.412kΩ R10=1.916kΩ R11=100Ω Total=66.7kΩ SW4 SW1 SW3 + SW2 SW4 SW3 To L-OUT Block
L-BC1
Same for Right channel
During boost, SW1 and SW3 are ON, during cut, SW2 and SW4 are ON, when 0dB, 0dBSW and SW2 and SW3 are ON.
L+R Block Equivalent Circuit Diagram
From L-VROUT + -
R1=50kΩ
Mute + -
R4=10kΩ
L+R
R2=50kΩ From R-VROUT + Step1 Step2 Step3 Step4 Step5 Step6 Step7 R3=50kΩ R5=10.284kΩ R6=8.169kΩ R7=6.489kΩ R8=5.154kΩ R9=4.094kΩ R10=3.252kΩ R11=12.559kΩ Total=50kΩ
L+R_LPF
AGND
ILV00257
No.A1046-14/18
LV1117N/1117NV
Tone Circuit Constant Calculation Examples
Treble Band Circuit: The shelving characteristics can be obtained for the treble band. The equivalent circuit and calculation formula during boost are indicated below. • Calculation example 1 Specification Set frequency: f = 10000Hz Gain during maximum boost: G+18dB = 17.5dB Let us use R1 = 6.51kΩ and R2 = 45.19kΩ The above constants are inserted in the following formula G = 20 × Log10 1+ R2 R12+(1/ ω C)2 1 C= 2πf R2 10G/20-1
2
+ R2 R1 C
-R12 1
= 2π24000
45190 7.50 - 1
2
≈2700 (pF)
2
- 6510
Bass Band Circuit: The equivalent circuit and the formula for calculating the external RC with a mean frequency of 100Hz are shown below. • Base band equivalent circuit diagram • Calculation example 1 specification Mean frequency: f0 = 100Hz Gain during maximum boost: G+20dB = 20dB Let us use R1 = 0kΩ and R2 = 66.7kΩ, and C1 = C2 = C.
C1 + R1 R2 C2
We obtain R2 from G = 20dB G = 20 × Log10 1+ R2 2 (10
G+20dB/20
R2 2R3 - 1) = 66700 2 (10 - 1) ≈3.6kΩ
R3
R3 =
We obtain C from mean frequency f0 = 100Hz f0 = 2π 1 (R3R2C1C2) 1 2πf0 R3R2 = 1 66700 × 3600 ≈0.1μF
C=
2π × 100
We obtain Q Q= R3R2 2R3 × 1 R3R2 ≈2.15
Note item when using (1) When turning on the power, the setting inside is unsettled. Before setting control data, it does a mute. (2) To prevent the digital noise of the high frequency influence a terminal. (SCL, SDA) It can be protected by a signal line in the ground pattern or by the shielding cable. (3) To prevent the noise in changing a mode, please set the mute ON.
No.A1046-15/18
LV1117N/1117NV
Volume Control Step Characteristics
0 10
Vcc = 9.0V Vin = 0dBV Input = VRIN Output = VROUT
Gain - Frequency
Vcc = 9.0V Vin = -10dBV Input = L/R Ch-A Output = L/R OUT
Volume attenuation (dB)
-10 -20 -30 -40 -50 -60 -70 -80 -90 -90
8
Gain Attenetion (dB)
-60 -50 -40 -30 -20 -10 0
6 4 2 0 -2 -4 -6 -8 -10
-80
-70
Step Setting (dB)
-6
-4
-2
0 2 Gain Step (dB)
4
6
Bass Band Frequency Characteristics
5 0 -5 -10 -15 -20 -25 -30 -35 -40 -45 10 100 1000 10000 100000
Vcc = 9.0V Vin = -20dBV C = 0.1uF R = 3.6kΩ Input = L/R Ch-A Output = L/R OUT
Treble Band Frequency Characteristics
5 0 -5
Vcc = 9.0V Vin = -20dBV C = 2700pF Input = L/R Ch-A Output = L/R OUT
Gain (dBV)
Gain (dBV)
-10 -15 -20 -25 -30 -35 -40 -45 10
100
1000
10000
100000
Frequency (Hz)
Frequency (Hz)
Surround Mode Frequency Characteristics
-5
Vcc = 9.0V Vin = -20dBV Input = L/R Ch-A Output = L/R OUT
L+R Frequency Characteristics
10 0 -10
Vcc = 9.0V Vin = 0dBV Input = VRIN Output = VROUT
-10
Gain (dBV)
Gain (dBV)
10 100 1000 10000 100000
-15 -20
-20 -30 -40 -50
-25
-60 10 100 1000 10000 100000
Frequency (Hz) Pseud Lch vs Rch Phese Shift vs Frequency Characteristics
180
Vcc = 9.0V Vin = -20dBV Input = L/R Ch-A Output = L/R OUT
Frequency (Hz)
Vcc - Vomax Characteristics (1)
100.0
Phase Shift (DEG )
Vomax (dBV)
10.0
Total
90
Matrix
1.0
THD = 1% Input = L/R Ch-A Output = L/R OUT
0 10 100
0.1
Frequency (Hz)
1000
10000
100000
5
6
7
8 Vcc (V)
9
10
No.A1046-16/18
LV1117N/1117NV
THD - Vin characteristics
1 1
THD - Vin characteristics (Surround)
Vcc=9.0V fin=1kHz Mode_A
Total harmonic distotion (%)
Total harmonic distotion (%)
Vcc=9.0V fin=1kHz
0.1
0.1
0.01
Total Matrix Mono Psudo
0.01
0.001 -40
-30
-20
-10
0
0.001 -40
-30
-20
-10
0
Vin (dBV)
Vin (dBV)
THD - Frequency Characteistics
1 1
THD - Supply Voltage Characteristics
Vin=-10dBV fin=1kHz
Total harmonic distotion (%)
Total harmonic distotion (%)
Vcc=9.0V Vin=-10dBV
0.1
Total Matrix Mono Psudo Surround
0.1
Total Matrix Mono Psudo Surround
0.01 100
1000
10000
100000
0.01 4.0
5.0
6.0
7.0
8.0
9.0
10.0
11.0
Frequency (Hz)
Supply Voltage (V)
VCC - VREF
6.0 5.5 5.0 3.1 4.5 4.0 3.5 3.0 2.5 2.0 1.5 4.0 5.0 6.0 7.0 8.0 9.0 10.0 11.0 2.5 4.0 5.0 6.0 3.3
VCC - VDD
VREF (V)
VDD (V)
2.9
2.7
7.0
8.0
9.0
10.0
11.0
VCC (V)
VCC (V)
VCC - AGND
6.0 5.5 5.0 65.0 60.0 55.0
VCC - ICCO
4.0 3.5 3.0 2.5 2.0 1.5 4.0 5.0 6.0 7.0 8.0 9.0 10.0 11.0
ICCO (mA)
AGND (V)
4.5
50.0 45.0 40.0 35.0 30.0 25.0 20.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 11.0
VCC (V)
VCC (V)
No.A1046-17/18
LV1117N/1117NV
SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein. SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO Semiconductor Co.,Ltd. products described or contained herein are controlled under any of applicable local export control laws and regulations, such products may require the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written consent of SANYO Semiconductor Co.,Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO Semiconductor Co.,Ltd. product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. Upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third party. SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's intellectual property rights which has resulted from the use of the technical information and products mentioned above.
This catalog provides information as of February, 2008. Specifications and information herein are subject to change without notice.
PS No.A1046-18/18
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