Ordering number : ENA1746
Bi-CMOS IC
LV23401V
Overview
For Home Stereo System 1-chip Tuner IC Incorporating PLL
The LV23401V is a AM/FM one-chip tuner IC for home stereo system.
Functions
• AM tuner • FM tuner • MPX stereo decoder • FLL tuning system
Features
• All the adjustment work of external parts is unnecessary. • CCB control with easy command base • External parts are reduced by LOW-IF frequency (FM=225kHz, AM=53kHz) adoption. • The high sensitivity reception is achieved in low noise MIX input circuit. • All bands of Japan-U.S.-Euro can be received by the soft program change (76MHz to 108MHz). • With built-in FLL(Frequency Locked Loop) tune function • Soft mute and stereo blend function (seven stages programmed control possible) • With built-in adjacent channel obstruction removal function • With built-in stereo pilot cancellation function • For EN55020-S1 standard (European immunity) • With built-in power save function
Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment (home appliances, AV equipment, communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee thereof. If you should intend to use our products for applications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our customer shall be solely responsible for the use. Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer' s products or equipment.
61610 SY 20100428-S00002 No.A1746-1/24
LV23401V
Specifications
Maximum Ratings at Ta = 25 °C
Parameter Maximum supply voltage Maximum output voltage Maximum input voltage Allowable power dissipation Operating temperature Storage temperature Symbol VCC max VO max VIN1 max VIN2 max Pd max Topr Tstg Conditions Analog block supply voltage Digital block supply voltage CE, DI, CL CLK IN Ta≤70°C *2) Ratings 10.0 4.5 *1) Vref2+0.35 4.5 450 -20 to +70 -40 to +125 Unit V V V V mW °C °C
*1) Vref2 = 22 pin voltage *2) When mounted on the specified printed circuit board (114.3mm × 76.1mm × 1.6mm), glass epoxy
Operating Condition at Ta = 25 °C
Parameter Recommended supply voltage Operating supply voltage range Symbol VCC VCC op Conditions Analog block supply voltage Resister 1Eh Bit 1(LEVSHIF)=0 Resister 1Eh Bit 1(LEVSHIF)=1 * Stabilize the service voltage so as not to cause the voltage charge by the noise etc. Ratings 9.0 4.5 to 6.5 8.5 to 9.5 Unit V V V
Interface block allowable operation range at Ta = -20 to +70°C, VSS = 0V
Parameter Input “H” level voltage Input “L” level voltage Output voltage Crystal frequency Crystal frequency deflection Symbol VIH1 VIH2 VIL1 VIL2 VO fIN f devi1 f devi2 Crystal vibrator load capacity CL CE, DI, CL CLK IN CE, DI, CL CLK IN D0 CLK IN For the standard European immunity When standard non-corresponds European immunity * 4 12.5 pF * The evaluation request to the crystal maker is recommended because it changes by the substrate and the circuit constant used. -50 -150 Conditions Ratings min 2.3 2.3 0 0 0 32.768 +50 +150 typ max 3.435 3.435 0.5 0.3 4.0 Unit V V V V V kHz ppm ppm
Operating Characteristics at Ta = 25°C, VCC = 9.0V with the designated circuit.
Parameter Current drain (at no input) Power save current drain VDD output voltage VDD drop-out voltage Symbol ICCFM ICCAM I standby VDD VDD_drop Conditions No input in FM mode. 15 pin supply current. No input in AM mode. 15 pin supply current. 15 pin supply current power save : Register 1Fh_bit0 = 0 22 pin voltage (reference value) 22 pin voltage. Drive mode at 10mA. *Drive current maximum = 10mA [FM receive characteristics] : fc = 98MHz, VIN = 60dBμV, fm = 1kHz, De-emphasis = 50μs, IF = 225kHz, BW = 50% MONO : 75kHz dev. S/N 50dB Sensitivity S/N 30dB Sensitivity IHF Sensitivity Signal-to-noise ratio Total harmonic distortion STEREO : L+R = 67.5kHz dev., Pilot = 7.5kHz dev. SN50 SN30 IHF SN SN-ST1 THD1 THD1-ST THD2 THD3 Input level that becomes S/N=50dB Input level that becomes S/N=30dB Input level that becomes THD=3% MONO STEREO MONO STEREO MONO, 150kHz dev. MONO, VIN = 120dBμV 62 58 17 12 12 70 66 0.5 0.5 1.5 0.6 1.5 2.5 5 2.5 24 18 20 dBμV dBμV dBμV dB dB % % % % Volume level = 3, Soft mute = off, Soft stereo = off, Resister 1Eh Bit 1(LEVSHIF) = 1, 9 pin output, IHF-BPF (2.772) 3.3 0.15 (3.435) V V Ratings min 25 14 typ 35 24 0.25 max 45 34 0.7 Unit mA mA mA
Continued on next page.
No.A1746-2/24
LV23401V
Continued from preceding page.
Parameter Demodulation output Symbol VO0 VO1 VO2 VO3 MPX output Channel balance SD operation level Stereo operation level Stereo separation Sep De-emphasis deflection Carrier leakage Pilot margin (Pilot lighting sensitivity) AM suppression ratio Mute attenuation Deemp50 Deemp75 CL ST-ON AMR MUTE VO_MPX CB SD ST Conditions MONO, VOL = 0 (reference value) MONO, VOL = 1 (reference value) MONO, VOL = 2 (reference value) MONO, VOL = 3 (reference value) *In-house management = Typ ±3.0dB 6 pin output 10 pin output / 9 pin output FS_S = 4 FS_S = 4 Both channels of 9 pins and 10 pins are measured. *In-house management value ≥25dB fm = 10kHz, 15kHz LPF OFF fm = 10kHz, 15kHz LPF OFF STEREO S/N, 15kHz LPF OFF L+R = 67.5kHz, Pilot-mod 400Hz AM 30% mod. 30 0.6 40 60 65 75 -12.5 -10 -13 40 5.5 -7.5 dB dB dB % dB dB 25 40 dB Ratings min (218) (291) (366) 518 100 -1 17 17 typ (327) (436) (549) 775 200 0 25 25 max (489) (652) (821) 1160 300 +0 33 33 Unit mVrms mVrms mVrms mVrms mVrms dB dBμV dBμV
[AM receive characteristics] : fc = 1MHz, VIN = 94dBμV, fm = 400Hz, 30% mod, IF = 53kHz, BW = 50% Volume level = 3, Soft mute = 4, Resister 1Eh Bit 1(LEVSHIF) = 1, 9 pin output, 15kHz LPF OFF S/N 20dB Sensitivity SN20 SN20-L SN20-H Signal-to-noise ratio Total harmonic distortion Detected output SN THD1 THD2 VO0 VO1 VO2 VO3 Channel balance AGC response CB AGC1 AGC2 Frequency response SD operation level Mute attenuation Hi-cut SD MUTE VIN = 104dBμV VOL = 0 (reference value) VOL = 1 (reference value) VOL = 2 (reference value) VOL = 3 10 pin output / 9 pin output Input level difference that output level becomes -10dB. Soft mute = 3 (reference value) Soft mute = 4 fm = 4kHz AGC = ON, FS = 4 *In-house management =46 to 65dBμV 15kHz LPF ON (55) (69) (87) 110 -1 (52) 47 -22 46 50 Input level that becomes S/N=20dB fc = 603kHz (reference value) fc = 1404kHz (reference value) 42 49 (55) (49) 50 0.6 0.8 (78) (98) (123) 155 0 (62) 57 -17 54 65 -12 65 2.8 2.8 (109) (138) (173) 218 +1 65 (65) (65) dBμV dBμV dBμV dB % % mVrms mVrms mVrms mVrms dB dB dB dB dBμV dB
Package Dimensions
unit : mm 3191B
9.75 30 16
5.6
7.6
1 0.65 (0.33) 0.22
15 0.15
SANYO : SSOP30(275mil)
0.1
(1.3)
1.5max
0.5
No.A1746-3/24
LV23401V
Pin function
pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 pin name AM ANT AM ref AM CAP GND1 Vref1 MPX OUT AM AGC GND2 L OUT R OUT VCC Low AM LCF SD OUT ST OUT VCC CLK IN ST ADJ CE CL DI DO Vref2 GND3 L1 Vref3 L2 SD ADJ FLL CAP GND4 FM ANT Description AM antenna AM reference voltage AM capacitor bank AM antenna GND Analog reference voltage Detected output AM AGC Analog GND L-ch audio output R-ch audio output Low voltage mode AM low cutting filter SD detecting phase output ST detecting phase output Supply voltage Reference clock input Pilot margin adjustment pin address/data switching timing Communication clock Data input Data output VDD voltage output Logic GND Local oscillation circuit Reference voltage for local oscillation circuit Local oscillation circuit SD = ON sensitivity adjustment pin FLL low pass filter FM antenna GND FM antenna It connects it to 25 pin through 0.1μF. Connect to GND Input impedance 75Ω. It connects it to 25 pin through 33nF. It connects it to GND through 22kΩ It connects it to 22 pin through 10kΩ 3.3V voltage output pin. It is also possible to supply the current to other IC up to 10mA. Connect to GND It connects it to 25 pin through 33nF. It connects it to GND through the capacitor of 100μF The crystal is recommended to be used. It is also possible to input directly clock signals (square wave GND standard). It connects it to GND through 180kΩ Remark It connects it to 2pin through the matching coil or the bar antenna. It connects it to 1pin through the matching coil or the bar antenna. It connects it to GND through an external inductor of recommendation 240μH. Connect to GND It connects it to GND through the capacitor of 1μF. LC72725 and connection when RDS is used It connects it to GND through the capacitor of 4.7μF Connect to GND The DC level changes by setting Resistor 1Eh bit1 (LEVSHIF) to adjust the output level according to the VCC potential. It is short with 15pin when using it with VCC < 6.0V or less. It connects it to GND through the capacitor of 0.047μF 2.0V DC_bias
No.A1746-4/24
LV23401V
Description of Pin Functions
No. 1 Pin name AM-ANT Voltage (V) 2.2V Internal Equivalent Circuit Remarks AM antenna input pin. The AM antenna coil is connected between 2pin. R = 100Ω
1 R R
2
2
AM-REF
2.2V
AM standard bias pin.
15 2.2V Regulator 2
3 AM-CAP AM Tuning for tune pin.
3
CAP-BANK
(AM Capacitor Bank)
4 5
GND1 VREF1
0V 4.3V
Analog (AM_FE) GND pin.
15 4.3V Regulator 5
Analog (tuner area) standard bias pin. VREF = 4.3V
6
MPX-OUT
2.5V
FM demodulation output pin.
R2 6 R1 R3
R1 = 100Ω R2 = 23kΩ R3 = 1kΩ
7
AM RF-AGC
-
AGC pin for AM-RF department Gain control. R1 = 2MΩ R2 = 5kΩ
R2 7 R1
R4 R3
R3 = 250Ω R4 = 1kΩ
8 9 10
GND2 L-OUT R-OUT
0V 2.5V (It is 3.3V for LEVSHIF = 1)
Analog (tuner) GND pin.
15
L-ch (R-ch) output pin. R = 100Ω ROUT = 150Ω
R
10 9
Continued on next page.
No.A1746-5/24
LV23401V
Continued from preceding page.
No. 11 Pin name VCC-Low Voltage (V) Internal Equivalent Circuit Remarks It is short 11pin with 15pin when using it with VCC < 6.0V.
15
11
Regulator
12
AM LCF
2.2V
AM Low-cut Filter pin.
12
R1 R2 R3
R4
R1 = 250Ω R2 = 100kΩ R3 = 100kΩ R4 = 50kΩ
R5
R5 = 50kΩ
13
SD-OUT
VDD
22 R SD SW 13
SD indicator output pin. Active Low output R = 100kΩ
14
ST-OUT
VDD
22 R ST SW 14
FM stereo indicator output pin. Active Low output R = 100kΩ
15
VCC
VCC
Analog area supply voltage pin. 8.5 to 9.5V are impressed at Resister 1Eh bit 1(LEVSHIF) = 1, and it is short at “0” with VCC_Low.
16
CLK_IN
2.1V
16
R
Clock connection pin for internal standard.
Crystal oscillator
32.768kHz crystal is connected. R = 100Ω Stereo lighting sensitivity adjustment pin.
17
ST-ADJ
3.7V
R 17
R
It connects it to GND through 180kΩ. R = 24kΩ
18
CE
−
Chip enable pin. Pin assumed to be high-level when serial data input (DI) and serial data output (DO).
18
19
CL
−
Data clock input pin Clock that takes data and synchronization when serial data input (DI) and serial data
19
output (DO).
Continued on next page.
No.A1746-6/24
LV23401V
Continued from preceding page.
No. 20 DI Pin name Voltage (V) − Internal Equivalent Circuit Remarks Serial data input pin. Input pin of the serial data transmitted by controller.
20
21
DO
−
Serial data output pin.
21
Serial data output pin to controller.
22 23 24 26
VDD GND3 L1 L2
3.3V 0V 4.3V
Logic area standard bias pin. VDD = 3.3V Digital area (control block) GND pin. OSC coil connect pin. 33nH is connected between 25pin.
24
26
CAP BANK
CAP BANK
25
VREF2
4.3V
12 4.3V Regulator 25
OSC area standard bias pin. VREF2 = 4.3V
27
SD-ADJ
0.1V
SD lighting sensitivity adjustment pin.
COMP
It connects it to GND through 22kΩ. R = 100Ω
27
R
28
FLL-CAP
−
LPF pin for internal FLL control. R = 80kΩ
28
29 30
GND4 FM-ANT
0V 0.9V
Analog (FMRF) GND pin. FM antenna input pin. R = 1.5kΩ RIN = 75Ω
30 R 29
No.A1746-7/24
LV23401V
Block Diagram
30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FLL LNA Divider
Osc cap Local oscillator Tuning system AGC DET BPF
Ref. osc GND Power management
LDO
State machine
SD out Demodulator Stereo decoder De-emphasis ST out Audio amp. Stereo blend
LNA Ant cap 1 2 3 4 5
Image det
6
7
8
9
10
11
12
13
14
15
Measurement circuit
DO
L2 33nH L1 33nH
DI
CL
CE
X1 32.768kHz
BPF C9 10pF
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Vref3(4.3V)
L1
FLL CAP
GND3
Vref2(3.3V)
DO
FM ANT
GND4
CE
SD adj
ST adj ST OUT
14
ST
L2
LV23401V
Vref1(4.3V)
MPX OUT
VCC_Low
AM_LCF
AM AGC
AM CAP
SD OUT
AM ANT
L OUT
GND1
R OUT
AM ref
GND2
T1 Dummy ANT
1
2
3
4
5
6
7
8
9
10
11
12
13
MPX OUT GND Lout Rout
SD
VCC=9V
VCC
15
No.A1746-8/24
CLK IN
CL
DI
LV23401V
Example of applied circuit 1
DO
L2 33nH L1 33nH
DI
CL
CE
X1 32.768kHz
Optional
BPF
C9 10pF
30
FM ANT
29
GND4
28
FLL CAP
27
SD adj
26
L2
25
Vref3(4.3V)
24
L1
23
GND3
22
Vref2(3.3V)
21
DO
20
DI
19
CL
18
CE
17
ST adj ST OUT
16
CLK IN
VCC=9V(5V)
LV23401V
Vref1(4.3V)
MPX OUT
VCC_Low
AM_LCF
AM AGC
AM CAP
SD OUT
AM ANT
L OUT
GND1
R OUT
AM ref
GND2
T1 L3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
For AM Loop antenna
AM CAP AM ref AM ANT GND
VCC=5V:short VCC=9V:open MPX OUT GND Lout Rout SD ST
LO1
For AM Ferrite antenna
VCC
15
No.A1746-9/24
LV23401V
Example of applied circuit 2
DO
L2 33nH L1 33nH
DI
CL
CE
X1 32.768kHz
BPF
Optional
C9 10pF
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Vref3(4.3V)
L1
FLL CAP
GND3
Vref2(3.3V)
GND4
FM ANT
DO
CE
LV23401V
Vref1(4.3V)
MPX OUT
VCC_Low
AM_LCF
AM AGC
AM CAP
SD OUT
AM ANT
ST OUT
14
ST
L OUT
GND1
R OUT
AM ref
GND2
T1 L3
1
2
3
4
5
6
7
8
9
10
11
12
13
For AM Loop antenna
VCC=5V:short VCC=9V:open C18 15pF X2 C17 4.332MHz 15pF MPX OUT GND Lout Rout SD VCC=9V
16
15
14
13
12
11
10
9
RDCL
XOUT
RST
LC72725KV
RDSID READY
MPXIN
RDDA
VREF
VDDa
VSSa
FLOUT
MODE
VDDd
VSSd
1
2
3
4
5
6
7
C15 330pF
C16 560pF
CIN
TEST
XIN
8
VCC
15
No.A1746-10/24
CLK IN
SD adj
ST adj
L2
CL
DI
LV23401V
Used parts
Component
L1 L2 L3 T1 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 R1 R2 R3 R4 R5 BPF X1 X2 LO1
Parameter
Local Osc Coil Local Osc Coil AM Loop antenna AM RF matching Ripple Filter Ripple Filter AM RF AGC Capacitor Coupling Capacitor Coupling Capacitor AM Low-cut Filter Supply Bypass Capacitor Supply Bypass Capacitor Correction Capacitor Supply Bypass Capacitor Ripple Filter Osc Filter Ripple Filter Ripple Filter Coupling Capacitor Coupling Capacitor Correction Capacitor Correction Capacitor Reference Resistor Pulled-up Resistor Reference Resistor Reference Resistor Pulled-up Resistor FM ANT BPF Crystal Crystal AM Ferrite antenna
Value
33nH 33nH 18.1μH 0.1μF 1μF 4.7μF 1μF 1μF 0.047μF 0.1μF 22μF 10pF 22μF 0.1μF 0.1μF 0.1μF 10μF 330pF 560pF 15pF 15pF 180Ω 10kΩ 22kΩ 33kΩ 10kΩ 32.768kHz 4.332MHz 260μH
Tolerance
5% 5% 5% -
Type
LL2012-FHL33NJ LL2012-FHL33NJ 4910-CSL18R1JN1 A90326057 #7003RNS-A1109YZS
Supplier
TOKO TOKO SAGAMI COILS TOKO
100ppm 100ppm TBD
GFMB7 VT-200-F(12.5pF) AT-49 -
SOSHIN SEIKO DAISHINKI -
* L1 must be used when you receive an Eastern European band (65MHz to 75MHz) and L2 must use 39nH. * Inquire match (C9, C17, C18) of X1 and the X2 crystal of the crystal maker together with the substrate used.
No.A1746-11/24
LV23401V
Interface specification 1) LV23401 Interface specification LV23401 is controlled by the C2B (Computer Control Bus) cereal bus format. C2B is a bus to achieve it economically surely format as for the communications between LSI in the system with two or more LSI. Because it is single master's system, the processing of a complex arbitration is unnecessary. Therefore, the load of hardware is reduced, and the system configuration that is economically abundant becomes possible. Moreover, neither a lot of kinds of controller and interface doing nor special hardware is easily needed by serial I/O with software. C2B is thought between LSI in the equipment, and the communications between equipment that need a long line are not targeted. 2) C2B data composition DI control data (cereal data input) composition IN mode
Address B0 B1 B2 B3 A0 A1 A2 A3 00000011
DI
LV23401V is controlled by the bus format composed of the sub-address (register) that stores the data of the device address of 8bit (address) and each 8bit. "C0" is input from LSB to the start as an address when the serial data is input to LV23401V, the device that controls is specified, and the mode as the data input is fixed. It inputs from LSB in order of data (bit setting)→ register synchronizing with data clock (CL) after the address is input and the data input can be concluded. Composition of the DO control data (serial data output) OUT mode
DI DO
Address B0 B1 B2 B3 A0 A1 A2 A3 10000011
R01_B0 R02_B0 R00_B0 R01_B5 R01_B7 R01_B1 R01_B3 R02_B1 R00_B1 R00_B3 R00_B5 R00_B7 R01_B2 R01_B6 R02_B2 R02_B3 R02_B5 R01_B4 R00_B2 R00_B4 R00_B6 R02_B4 R03_B6 R03_B7
D0 D1 D2 D3 D4 D5 D6 D7 R0 R1 R2 R3 R4 R5 R6 R7
Data Resister
Reg00h Data
Reg01h Data
Reg02h Data
"C1" is input from LSB to the start as an address when the serial data is output from LV23401V, the controlled device is specified, and the mode as the data output is fixed. The subsequent data is output from DO pin synchronizing with lock (CL) after the address is input LSB from one with small register number. The output of data is ended by setting CE pin to Low.
No.A1746-12/24
LV23401V
3) Description of the Register of LV23401 Register 00h – CHIP_ID – Chip identify register (Read-Only)
7 ID[7:0] Bit 7-0 : ID[7:0] : 8-bit CHIP ID. LV23400 : 18h Note : To abort the command, write any value in this register. 6 5 4 3 2 1 0
Register 01h – CHIP_REV – Chip Revision identify resister (Read-Only)
7 Revision[7:0] Bit 7-0 : ID[7:0] : 8-bit Chip revision ES1 : 00h Note : To abort the command, write any value in this register. 6 5 4 3 2 1 0
Register 02h – RADIO_STAT – Radio station status (Read-Only)
7 IM_STAT Bit 7 : 6 IM_FS[1:0] 5 4 MO_ST 3 FS[2:0] 2 1 0 TUNED
IM_STAT : State of image evasion code 0 = Eternal operation (It is possible to write it.) 1 = The image evasion is being processed. (Writing is improper.)
Note : This bit operates only when Resister 14h_bit7 (IM_EVAS) is set to "1". The data writing processing to LV23401 when this bit is "1" is prohibited. Bit 6 - 5 : IM_FS : Image bureau electric field strength 0 : Image bureau none 1:0 2 : 0dB to 10dB compared with the hope bureau. 3 : The level of the image bureau is +10dB or more stronger than that of the hope bureau. Bit 4 : MO_ST : MONAURAL/STEREO display 0 = Stereo reception (Compelling the monaural setting is also the same.) 1 = Receiving in stereo mode. Bit 3 - 1 : FS[2:0] : Field strength 0 : Field strength < 10dBμV 1 : Field strength 10 to 20dBμV 2 : Field strength 20 to 30dBμV ••• 3 : Field strength > 70dBμV Bit 0 : TUNED : Radio-tuning flag 0 = No tuning. 1 = The tuning. Note : When the frequency tuning succeeds, this bit is set. This flag is cleared under the following three conditions. 1. PW_RAD = 0 2. Do the tuning of the frequency. 3. When FLL becomes outside the correction range Only when the TUNED flag is changed from one into 0, the RAD_IF interrupt flag is set. When the status of TUNED changes from 0 into one, the interrupt is not generated.
Register 04h – TNPL – Tune position low (Read-Only)
7 TUNEPOS[7:0] Bit 7-0 : TUNEPOS[7:0] : Current RF frequency (Low 8bit) 6 5 4 3 2 1 0
No.A1746-13/24
LV23401V
Register 05h – TNPH_STAT – Tune position high / status (Read-Only)
7 ERROR[1:0] Bit 7 - 6 : ERROR[1:0] 0 1 2 3 Bit 5 – 0 : 6 5 TUNEPOS[12:8] ERROR[1:0] : Error code Remark OK, Command end (No Error) DAC Limit Error Command forced End Command busy (executing it) 4 3 2 1 0
TUNEPOS[13:8] : Current RF frequency (High 5 bit)
Register 06h – COUNT_L – Counter low (Read-Only)
7 COUNT[7:0] Bit 7 – 0 : COUNT[7:0] : Counter value (Low 8bit) 6 5 4 3 2 1 0
Register 07h – COUNT_H – Counter High (Read Only)
7 COUNT[15:8] Bit 7 – 0 : COUNT[15:8] : Counter value (High 8bit) 6 5 4 3 2 1 0
Register 08h – IF_OSC – DAC for IF OSC (Read/Write)
7 IFOSC[7:0] Bit 7 – 0 : IFOSC[7:0] : IF Oscillator DAC 6 5 4 3 2 1 0
Register 09h – IFBW – DAC for IF – Filter Band width (Read/Write)
7 IFBW[7:0] Bit 7 – 0 : IFBW[7:0] : IF Band-pass Filter Band DAC 6 5 4 3 2 1 0
Register 0Bh – STEREO_OSC – DAC for Stereo Decoder OSC (Read/Write)
7 SDOSC[7:0] Bit 7 – 0 : SDOSC[7:0] : Stereo Decoder Oscillator DAC 6 5 4 3 2 1 0
Register 0Ch – RF_OSC – DAC for RF OSC (Read/Write)
7 RFCAP[7:0] Bit 7 – 0 : RFOSC[7:0] : RF Oscillator DAC 6 5 4 3 2 1 0
Register 0Dh – RFCAP – RF Cap bank (Read/Write)
7 RFCAP[7:0] Bit 7 – 0 : RFCAP[7:0] : RF Oscillator Capacitor bank 6 5 4 3 2 1 0
Register 0Eh – AMCAP1 – AM-ANT Cap bank1 (Read/Write)
7 AMCAP[7:0] Bit 7 – 0 : AMCAP[7:0] : AM Antenna Capacitor bank Note : The AM antenna capacitor bank is composed of 12 bits. High 4 bits are arranged in AMCTRL resister. 6 5 4 3 2 1 0
No.A1746-14/24
LV23401V
Register 0Fh – AMCTRL – AM Station Control (Read/Write)
7 AMDIV[2:0] Bit 7 – 5 : Bit 7 : Bit 6 : Bit 5 : AMDIV[2:0] : AM Clock Divider AM_CD2 : AM Clock Divider bit 2. AM_CD1 : AM Clock Divider bit 1. AM_CD0 : AM Clock Divider bit 0. 6 5 4 AM_CAL 3 ACAP11 2 ACAP10 1 ACAP9 0 ACAP8
Note : AMCD[2:0] uses the frequency of FM belt even for the AM belt to lower. Set the machine of the AM dividing frequency to turning off at FM mode. AM_CD[2:0] 0,1 2 3 4 5 6 7 Bit 4 : Bit 3 – 0 : Bit 3 : Bit 2 : Bit 1 : Bit 0 : NA ( 0 Fixation) AMCAP[11:8] : AM antenna capacitor bank. AMCAP_bit11 AMCAP_bit10 AMCAP_bit9 AMCAP_bit8 Rate of dividing frequency Divider OFF 224 160 112 80 64 48 Rough estimate AM-RF frequency (In kHz) 0 (FM mode) 338 – 483 474 – 676 676 – 966 947 – 1353 1183 – 1692 1578 - 2256
Register 10h – DO_REF_CLK_CNF – Do output mode and reference clock configuration (Read/Write)
7 IPOL Bit 7 : 6 DO_SEL[1:0] 5 4 3 2 FS_S[2:0] 1 0 EXT_CLK_CFG[1:0]
IPOL : Indicator (DO pin _SD/ST mode) polarity 0 = SD/ST Active Low (The same state change as 13pin – SD pin / 14pin – ST pin ) 1 = SD/ST Active High (State change opposite to 13pin – SD pin / 14pin – ST pin )
Note : This bit doesn't influence the polarity of the serial data. Bit 6 -5 : DO_SEL : DO pin select (DO pin output mode select) DO_SEL[1:0] 00 01 10 11 OSC. * The state of DO pin changes synchronizing with SD pin / ST pin when DO_SEL is set to (01b) or (10b). * The state of DO pin changes by the position of Local OSC when DO is set to (11b). Lower heterodyne = 0, Upper heterodyne = 1 * Set DO_SEL to (00b) when you output the serial data. Bit 4 – 3 : EXT_CLK_CFG[1:0] : External clock setting EXT_CLK_CFG[1:0] 00 01 10 11 Bit 2 – 0 : Reference clock Off The external clock is supplied. 32768Hz Crystal oscillation Unused DO pin Serial data output mode ST pin mode SD pin mode Local position confirmation mode
DO pin is used by observing the position (Upper heterodyne / Lower heterodyne) of a state of SD pin/ST pin besides the serial data output and local
FS_S[2:0] : SD(Station Detector) operate level setting (distinguishes at the FS level )
No.A1746-15/24
LV23401V
Register 11h – IF_SEL – IF frequency selection (Read/Write)
7 FLL_MOD Bit 7 : 6 AMIF[2:0] FLL_MOD : FLL operation mode 0 : Smoothing filter = OFF 1 : Smoothing filter = ON Bit 6 -4 : AMIF[2:0] : IF frequency setting when AM mode is selected AMIF[2:0] 0 20kHz Bit 3 – 0 :
SE_ AM 0 0 RF_ SEL 0 1 0 112.5 112.5 1 125 127.5 2 137.5 142.5 3 150 157.5 4 162.5 157.5 5 175 172.5 6 187.5 187.5
5
4
3 FMIF[3:0]
2
1
0
1 31kHz
2 42kHz
3 53kHz
4 64kHz
5 75kHz
6 86kHz
7 97kHz
FMIF[3:0] : IF frequency setting when FM mode is selected (kHz)
FMIF[3:0] 7 212.5 202.5 8 225 217.5 9 237.5 232.5 10 250 247.5 11 262.5 262.5 12 275 277.5 13 287.5 292.5 14 312.5 307.5 15 325 322.5
Register 12h – REF_CLK_MOD – Slope correction (Read/Write)
7 REFMOD[7:0] Bit 7 – 0 : REFMOD[7:0] : Reference clock correction 6 5 4 3 2 1 0
Note : As for this register, a set value is different according to the crystal connected with 16pin and the input clock. Inform of a set value of this register when you adopt the applications other than an example of applied circuit and recommended parts of this specifications.
No.A1746-16/24
LV23401V
Register 13h – SM_CTRL – Statemachine control (Read/Write)
7 FLL_ON Bit 7 : 6 CLKS_SE[2:0] FLL_ON : FLL control 0 = FLL OFF 1 = FLL ON Bit 6 – 4 : CLKS_SE : Clock course select 0 = No select 1 = The source of the stereo decoder oscillator is effective. 2 = The source of the IF oscillator is effective. 3 = The source of the AM antenna oscillator is effective. 4 = The source of the FM-RF oscillator is effective. 5 = The source of the AM-RF oscillator is effective. 6 – 7 = no select Note : Bit[6-4] selects the source of the oscillator. Select the arbitrary source that to be adjusted and to be measured. Bit 3 : nSD_PM : Stereo decoder clock PLL mute 0 = SD PLL OFF (Adjustment) 1 = SD PLL ON (Operation usually) Bit 2 : nIF_PM : IF PLL mute 0 = IF PLL OFF (Adjustment) 1 = IF PLL ON (Operation usually) Bit 1 – 0 : CM_SE : Command mode select 0 = Command no select 1 = Measurement mode 2 = Adjustment mode 3 = Radio tuning (reception frequency adjustment) mode Note : This bit is used to select the command mode. Select the arbitrary command to be executed. The command is executed by setting TARGET_VAL_L/H. Command execution time : SD calibration = 540ms IF calibration = 134ms RF(FM) tuning = 105ms RF(AM) tuning = 158ms * Stand-by at time to have provided for the above-mentioned before all processing including reading the register value after having executed the command. 5 4 3 nSD_PM 2 nIF_PM 1 DM_SE[1:0] 0
Register 14h – REF_CLK_PRS – Reference clock pre-scalar (Read/Write)
7 IM_EVAS Bit 7 : 6 Reserved 5 WAIT_SEL 4 A
