LV23411V

Ordering number : EN*A1990 LV23411V Overview Bi-CMOS LSI For Home Stereo Systems FM/AM Tuner IC The LV23411V is single chip tuner IC, and FM/AM radio is able to be realized with few external parts. Functions • FM tuner • AM tuner • MPX Stereo Decoder • Tuning system Features • No alignments necessary • Reduction of external component counts • Large audio output signal is available for home stereo systems • Worldwide FM band support (64 to 108MHz) • Worldwide AM band support (520 to 1710kHz) • Soft-mute, Stereo-blend function • LV23411 corresponds to Europe Immunity standard (EN55020-S1) • I2C control interface Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment. The products mentioned herein shall not be intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee thereof. If you should intend to use our products for new introduction or other application different from current conditions on the usage of automotive device, communication device, office equipment, industrial equipment etc. , please consult with us about usage condition (temperature, operation time etc.) prior to the intended use. If there is no consultation or inquiry before the intended use, our customer shall be solely responsible for the use. Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer ' s products or equipment. O2611 SY PC No.A1990-1/23 LV23411V Specifications Absolute Maximum Ratings at Ta = 25°C, GND1 = GND2 = GND3 = GND4 = GND5 = 0V Parameter Maximum supply voltage Digital output voltage Digital input voltage Symbol VCC max VO max VIN1 max VIN2 max Allowable power dissipation Operating temperature Storage temperature Pd max Topr Tstg SDA SDA, SCL CLK IN Ta ≤ 70°C *1 Conditions Ratings 10.0 3.6 3.6 3.6 450 -20 to +70 -40 to +125 Unit V V V V mW °C °C *1 : Mounted on a specified board. Board size is 114.3mm × 76.1mm × 1.6mm, glass epoxy. Operating Conditions at Ta = 25°C, GND1 = GND2 = GND3 = GND4 = GND5 = 0V Parameter Recommended supply voltage Operating supply voltage Range * Note * Note : supply the stabilized voltage. Symbol VCC VCC op Register 1Eh bit 1 (LEVSHIF) = 0 Register 1Eh bit 1 (LEVSHIF) = 1 Conditions Ratings 9.0 4.5 to 6.5 8.5 to 9.5 Unit V V V Interface Conditions at Ta = -20 to +70°C, GND1 = GND2 = GND3 = GND4 = GND5 = 0V Parameter High level input voltage Symbol VIH1 VIH2 Low level input voltage VIL1 VIL2 Output voltage Crystal frequency Crystal frequency accuracy VO fin faccuracy SDA, SCL CLK IN SDA, SCL CLK IN SDA CLK IN -100 Conditions min 2.3 2.3 0 0 0 32.768 +100 Ratings typ max 3.5 3.5 0.5 0.3 3.5 V V V V V kHz ppm Unit Operating Characteristics at Ta = 25°C, VCC = 9.0V, with the designated circuit. Parameter Symbol Conditions min [FM characteristics ; MONO] : fc = 98MHz, VIN = 60dBμV, fm = 1kHz, De-emphasis = 50μs, IF = 225KHz, BW = 45% MONO : 75kHz dev STEREO : L+R = 67.5kHz dev, Pilot = 7.5kHz dev Volume level = 3, Register 1Eh bit 1 (LEVSHIF) = 1, Pin 9 output, Audio filter = IHF-BP F, Soft mute = off ,Soft stereo = off Current drain 30dB S/N sensitivity Signal-to-noise ratio Total harmonic distortion ICC FM SN30 SNR THD THD-ST Demodulation output SD operation level Mute attenuation Stereo separation Carrier leak Stereo on level VO3 SD Mute Sep CL ST-ON No input S/N = 30dB input level MONO MONO STEREO MONO FS = 4 MONO Pin 10 output/Pin 9 output STEREO SNR, Audio filter = OFF L+R = 67.5kHz dev, Pilot level 518 17 60 20 30 62 35 40 10 70 0.5 0.5 775 25 75 35 40 3.0 6.5 1.5 2.5 1160 33 45 15 mA dBμV dB % % mVrms dBμV dB dB dB % Ratings typ max Unit [AM characteristics] : fc = 1MHz, VIN = 94dBμV, fm = 400Hz, mod = 30% IF = 53KHz, BW = 50% Volume level = 2, Register 1Eh bit 1 (LEVSHIF) = 1, Pin 9 output, Audio filter = 15kHz LPF OFF Current drain 20dB S/N sensitivity Signal-to-noise ratio Total harmonic distortion Demodulation output SD operation level Mute attenuation ICC AM SN20 SNR THD VO2 SD Mute FS = 4 15kHz LPF ON 122 46 50 No input S/N = 20dB input level 42 30 35 48 50 0.8 173 54 65 2.8 245 64 40 65 mA dBμV dB % mVrms dBμV dB No.A1990-2/23 LV23411V Package Dimensions unit : mm (typ) 3259 9.75 30 16 5.6 7.6 1 0.65 (0.33) 0.22 15 0.15 0.08 Block Diagram 30 29 28 (1.0) 1.2max SANYO : TSSOP30(275mil) 27 26 0.5 25 24 23 22 21 20 19 18 17 16 Ref .osc FLL LNA Divider Osc cap GND Local oscillator LDO Power management State machine Tuning system AGC DET BPF Demodulator Stereo decoder SD out De-emphasis ST out Stereo blend LNA Image det Audio amp. Ant cap 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 No.A1990-3/23 LV23411V Pin descriptions Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Pin name AM-ANT AM-REF AM-CAP GND1 VREF1 MPX IN_OUT AM RF-AGC GND2 L-OUT R-OUT VCC-Low AM LCF SD-OUT ST-OUT VCC CLK_IN I/O I O I O O O O O O O O I Descriptions AM antenna input Reference voltage for AM part AM capacitor bank AM antenna GND Reference voltage for analog Demodulato output AM RF AGC output Analog GND Audio Lch output Audio Rch output Voltage supply pin at low voltage operation mode AM low_cut filter SD indicator output ST indicator output Voltage supply pin Reference clock input 32.768kHz crystal connected to GND. It is Also applicable to input directly clock signals ( square wave GND_reference) 17 18 19 20 21 22 IF AGC CAP SD-ADJ NC SCL SDA VREF2 I I I/O O I2C interface CLK input I2C interface Data input/output Output voltage pin for VDD VDD output_pin of 3.0V. This pin is applicable to supply the current other IC up to 10mA. 23 24 25 26 27 28 29 30 GND3 L1 VREF3 L2 GND4 FLL-CAP GND5 FM-ANT O I Digital GND for control part Local oscillator Reference voltage for local OSC part Local oscillator Analog GND for OSC part Oscillator tuning voltage output Analog GND for FMRF part FM antenna input 1 39nH connected to pin 25 Connected to GND Capacitor of 0.1μF is connected between this pin and GND. Connected to GND Input impedance is 75Ω 0V 0.8V 39nH connected to pin 25 0V 5.0V 0V IF-AGC monitor point (test) Adjustment for SD on level Open Incase of changing SD on level, put Resistor between this pin and GND. 3.0V Capacitor of 0.047uF is connected between this pin and GND. Active low output Active low output 3.0V (0.1V) 3.0V (0.1V) 2.2V Remarks Connect to pin2 through Matching coil or Ferrite antenna. Connect to pin1 through Matching coil or Ferrite antenna. Exteranal inductor (recommendation value) is connected between this pin and GND. Connected to GND Capacitor of 1μF is connected between this pin and GND. When RDS used, LC72725 is applicable Capacitor of 1μF is connected between this pin and GND. Connected to GND According to the VCC_application, Reference Output_level setting is cangeable by Register Bit. Register 1Eh bit 1 (LEVSHIF) =1: Register 1Eh bit 1 (LEVSHIF) =0: When using VCC < 6V, Connect to Pin15 directly 0V 4.3V 2.5V 0V 2.6V (3.7V) DC voltage 2.2V - No.A1990-4/23 LV23411V Pin internal circuit description Pin No. 1 Pin name AM-ANT Pin voltage (V) 2.2 Description AM antenna input pin. The AM antenna coil is connected between pins 40 and this pin. R = 100Ω Internal equivalent circuit 1 R R 2 2 AM-REF 2.2 Reference voltage pin for AM. VAM-REF = 2.2V 15 2.2V Regulator 2 3 AM-CAP - Tuning pinl for AM. (AM Capacitor Bank) CAP-BANK 3 4 5 GND1 VREF1 0 4.3 GND pin for Analogue AM_FE part. Analogue part (tuner) reference bias terminal. VREF1 = 4.3V 15 4.3V Regulator 5 6 MPX IN_OUT 2.5 FM demodulation output /input for MPX. R = 100Ω 6 R 7 AM RF-AGC - Pin for AM_RF AGC. R1 = 2MΩ R2 = 5kΩ R3 = 250Ω R4 = 1kΩ R2 7 R3 R1 R4 8 9 10 GND2 L-OUT R-OUT 0 2.6 (3.7V when LEVSHIF = 1) GND pin for Analogue tuner part. L-ch (R-ch) output pin. R = 100Ω ROUT = 150Ω 15 10 R 9 Continued on next page. No.A1990-5/23 LV23411V Continued from preceding page. Pin No. 11 Pin name VCC-Low Pin voltage (V) shorted. Description when using with VCC < 6.0V, 11Pin-15 Pin is Internal equivalent circuit 15 5V Regulator 11 4.3V Regulator 12 AM LCF 2.2 Terminal for AM Low-cut Filter. R1 = 250Ω R2 = 100kΩ R3 = 100kΩ R4 = 50kΩ R5 = 50kΩ R4 12 R1 R2 R3 R5 13 SD-OUT 3.0 (less than 0.1) SD indicator output pin. Active Low output. R = 100kΩ 22 R 13 SD SW 14 ST-OUT 3.0 (less than 0.1) FM stereo indicator output pin Active Low output R = 100kΩ 22 R 14 ST SW 15 VCC VCC Analogue part power supply pin. When using 8.5 to 9.5V, set to Register 1Eh Bit 1 (LEVSHIF) = 1 When using with VCC < 6.5V, set to Register 1Eh Bit 1 (LEVSHIF) = 0 And 11Pin-15Pin must be shorted “ 16 CLK_IN 2.1 (OSC mode) For internal reference clock. 32.768kHz crystal connected to GND. It is Also applicable to input directly clock signals ( square wave GND_reference) R = 100Ω 16 R Crystal oscillator 17 IF AGC CAP - This pin is for test. Open R1 = 1.5kΩ, R2 = 1kΩ, R3 = 500Ω R1 R2 R3 17 18 SD-ADJ - Open normally. Adjust pin for SD sensitivity with to kΩ resistor connected to GND COMP 18 R Continued on next page. No.A1990-6/23 LV23411V Continued from preceding page. Pin No. 19 20 NC SCL Pin name Pin voltage (V) Digital interface CLK line. R = 1kΩ Description Internal equivalent circuit 20 R SCL 21 SDA Digital interface DATA line. (Interactive data communication line.) Require pull_up resistor 3.3k to 10k between this pin and Vref2 (VDD). R = 250Ω data 21 R data 22 VREF2 3 Reference voltage output pin for Logic part. Vref2 = 3V 15 3V Regulator 22 23 24 26 GND3 L1 L2 0 5 GND pin for digital part (Control part). OSC coil of 39nH to be connected between this pin and pin 25. 24 26 CAP BANK CAP BANK 25 VREF3 5 Reference voltage pin for local oscillation circuit. 15 5V Regulator 25 27 28 GND4 FLL-CAP 0 - GND pin for local oscillation circuit. LPF pi n for controlled FLL internally. R = 80kΩ 28 29 GND5 0 GND pin for local oscillation circuit. Continued on next page. No.A1990-7/23 LV23411V Continued from preceding page. Pin No. 30 Pin name FM-ANT Pin voltage (V) 0.8 R = 1.5kΩ Rin = 75Ω Description FM antenna input pin FM. Internal equivalent circuit 30 R 29 Used parts Component L1 L2 L3 T1 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 R1 R2 R3 BPF X1 LO1 Parameter Local Osc Coil Local Osc Coil AM Loop antenna AM RF matching Ripple Filter AM RF AGC Capacitor Coupling Capacitor Coupling Capacitor Supply Bypass Capacitor Supply Bypass Capacitor AM Low-cut Filter Supply Bypass Capacitor Osc Filter Ripple Filter Pulled-up Resistor Pulled-up Resistor SD Adjust Resistor FM ANT BPF Crystal AM Ferrite antenna Value 39nH 39nH 18.1μH 250μH 1μF 1μF 1μF 1μF 0.1μF 22μF 0.1μF 22μF 0.1μF 0.1μF 4.7kΩ 4.7kΩ to kΩ 32.768kHz 260μH 100ppm TBD GFMB7 DT-26 SOSHIN KDS Tolerance 5% 5% 5% Type LL2012-FHL39NJ LL2012-FHL39NJ 4910-CSL18R1JN1 A90326057 #7003RNS-A1109YZS Supplier TOKO TOKO SAGAMI COILS TOKO No.A1990-8/23 LV23411V Format of Bus Transfers Bus transfers are primarily based on the I2C primitives • Start condition • Repeated start condition • Stop condition • Byte write • Byte read Start, restart, and stop conditions are specified as shown in Table 1 below. Start Repeated start Stop SCL SCL SCL SDA SDA SDA Fig. 1 the I2C start, repeated start and stop conditions. For details, like timing, etc., refer to specifications of I2C. 8-bit write 8-bit data is sent from the master microcomputer to LV23411. Data bit consists of MSB first and LSB last. Data transmission is latched at the rising edge of SCL in synchronization with the SCL clock generated at the master IC. Do not change data while SCL remains HIGH. LV23411 outputs the ACK bit between eighth and ninth falling edges of SCL SCL D7 D6 D5 D4 D3 D2 D1 D0 Ack SDA Fig. 2 Signal pattern of the I2C byte write Read is of the same form as write, only except that the data direction is opposite. Eight data bits are sent from LV23411 to the master while Ack is sent from the master to LV23411. SCL D7 D6 D5 D4 D3 D2 D1 D0 Ack SDA Fig. 3 Signal pattern of the I2C byte read The serial clock SCL is supplied from the master side. It is essential that data bit is output from LV23411 in synchronization with the falling edge while the master side performs latching at the rising edge. No.A1990-9/23 LV23411V LV23411 latches ACK at the rising edge. The sequence to write data D into the register A of LV23411 is shown below. • Start condition • write the device address (C0h) • write the register address, A • write the target data, D • stop condition start SCL DA7 DA6...1 Ack write device address SDA write register address write data byte stop A7 A6...1 Ack D7 D6...0 Ack Fig. 4 Register write through I2C When one or more data has been provided for writing, only the first data is allowed to be written. Read sequence • start condition • write the device address (C0h) • write the register address, A • repeated start condition (or stop + start in a single master network) • write the device address + 1 (C1h) • read the register contents D, transmit NACK (no more data to be read) • stop condition start SCL DA7 write device address write register address rep. SDA start DA6...1 Ack A7 A6...0 Ack write device address + 1 read data byte with NACK stop DA7 DA6...1 Ack D7 D6...0 Fig. 5 Register read through I2C Interrupt Pin INT LV23411 has the dedicated interrupt output pin. For the active level to the host, either LOW or HIGH can be selected. The INT output pin is kept floating while the PWRAD bit is cleared during initialization. Therefore, to avoid influence on the CPU side during initialization, it is recommended to secure the non-active state by means of the pull-up or pull-down resistor. This enables direct INT output connection to non-masking interruption of the host CPU. No.A1990-10/23 LV23411V Digital interface specification (interface specification : reference) (1). Characteristics of SDA and SCL bus line relative to the I2C bus interface START Condition Tf SCL Repeated START Tr TLOW THIGH Tf SDA Tr THD;STA THD;DAT TSU;DAT TSU;STA Standard-mode Parameter SCL clock frequency Fall time of both SDA and SCL Rise time of both SDA and SCL High time of SCL Low time of SCL Hold time of STAT condition Hold time of Data Set-up time of STAT condition Set-up time of STOP condition Set-up time of Data Bus free time between a STOP and START condition Capacitivie load for each bus line *Cb = Total capacitance of one bus line Cb 400 Symbol FSCL Tf Tr THIGH TLOW THD ; STA THD ; DAT TSU ; STA TSU ; STO TSU ; DAT TBUF 4.0 4.7 4.0 0 4.7 4.0 250 4.7 3.45 min 0 max 100 300 1000 High_Speed-mode min 0 20+0.1Cb 20+0.1Cb 0.6 1.3 0.6 0 0.6 0.6 100 1.3 400 0.9 max 400 300 300 unit kHz ns ns μs μs μs μs μs μs ns μs pF No.A1990-11/23 LV23411V Description of the Register of LV23411V Register 00h - CHIP_ID - Chip identify register (Read-Only) 7 ID[7:0] Bit 7-0 : 6 5 4 3 2 1 0 ID[7:0] : 8-bit Chip ID LV243411 : 1Bh Note : To abort the command, write any value in this register. Register 01h - CHIP_REV - Chip Revision identify register (Read-Only) 7 6 5 4 Revision[7:0] Bit 7-0 : ID[7:0] : 8-bit Chip Revision ES1 : 00h Note : To abort the command, write any value in this register. 3 2 1 0 Register 02h - RADIO_STAT - Radio station status (Read-Only) 7 IM_STAT Bit 7 : 6 5 4 3 2 IM_FS[1:0] MO_ST FS[2:0] IM_STAT : State of Image-station avoidance 0 = Normal (Possible to write) 1 = The Image-station avoidance is being processed (Impossible to write) Note : This bit works only at Register14h_bit7 (IM_EVAS) is set to “1”. The writing processing to LV23411 is prohibited when this bit is “1”. 1 0 TUNED Bit 6-5 : IM_FS : Image-signal Fieldstrength 0 : No image-signal 1 : There are weak Image-signal that level is less -10dB or more weaker than desire’s 2 : The level of the image –signal is around 0 - 10dB compared with desire’s 3 : The level of the image-signal is +10dB or more stronger than that of desire’s MO_ST : Mono/Stereo indicator 0 = Forced monaural 1 = Normal (Receiving in stereo mode) FS[2:0] : Fieldstrength 0 : FS < 10 dBμV 1 : FS = 10 - 20 dBμV 2 : FS = 20 - 30 dBμV ……… 7 : FS > 70 dBμV TUNED : Radio tuning flag. 0 = No tuned 1 = Tuned Note : When the tuning command succeeds, this bit is set. This bit is cleared under 3 conditions as below. 1. PW_RAD = 0 2. Tuning Frequency 3. When FLL becomes outside the correction range Bit 4 : Bit 3-1 : Bit 0 : No.A1990-12/23 LV23411V Register 04h - TNPL - Tune position low (Read-Only) 7 6 5 4 3 TUNEPOS[7:0] Bit 7-0 : TUNEPOS[7:0] : Current RF Frequency (Low 8 bit) 2 1 0 Register 05h - TNPH_STAT - Tune position high/status (Read-Only) 7 6 5 4 3 ERROR[1:0] TUNEPOS[12:8] Bit 7-6 : ERROR[1:0] : Error code ERROR[1:0] Remark 0 OK, Command end (No Error) 1 DAC Limit Error 2 Command forced End 3 Command busy Bit 5:0 : TUNEPOS[13:8] : Current RF Frequency (High 5 bit) 2 1 0 Register 06h - COUNT_L - Counter low (Read-Only) 7 6 5 4 COUNT[7:0] Bit 7-0 : COUNT[7:0] : Counter value (Low 8 bit) 3 2 1 0 Register 07h - COUNT_H - Counter High (Read-Only) 7 6 5 4 COUNT[15:8] Bit 7-0 : COUNT[15:8] : Counter value (High 8 bit) 3 2 1 0 Register 08h - IF_OSC - DAC for IF OSC (Read/Write) 7 IFOSC[7:0] Bit 7-0 : 6 5 4 3 2 1 0 IFOSC[7:0] : IF Oscillator DAC Register 09h - IFBW-DAC for IF - Filter Band width (Read/Write) 7 IFBW[7:0] Bit 7-0 : 6 5 4 3 2 1 0 IFBW[7:0] : IF-Filter Band width DAC Register 0Bh - STEREO_OSC - DAC for Stereo Decoder OSC (Read/Write) 7 6 5 4 SDOSC[7:0] Bit 7-0 : SDOSC[7:0] : Stereo Decoder Oscillator DAC 3 2 1 0 Register 0Ch - RF_OSC - DAC for RF OSC (Read/Write) 7 6 5 4 RFCAP[7:0] Bit 7-0 : RFOSC[7:0] : RF Oscillator DAC 3 2 1 0 Register 0Dh - RFCAP - RF Cap bank (Read/Write) 7 6 5 4 RFCAP[7:0] Bit 7-0 : RFCAP[7:0] : RF Oscillator Capacitor-Bank 3 2 1 0 No.A1990-13/23 LV23411V Register 0Eh - AMCAP1 - AM - ANT Cap bank1 (Read/Write) 7 6 5 4 AMCAP[7:0] Bit 7-0 : AMCAP[7:0] : AM Antenna Capacitor-Bank Note : The AM antenna capacitor bank is composed of 12 bits. High 4 bit is arranged at “AMCTRL” register. 3 2 1 0 Register 0Fh - AMCTRL - AM Station Control (Read/Write) 7 AMDIV[2:0] Bit 7-5 : Bit 7 : Bit 6 : Bit 5 : 6 5 4 AM_CAL 3 ACAP11 2 ACAP10 1 ACAP9 0 ACAP8 AMDIV[2:0] : AM Clock Divider AM_CD2 : AM Clock Divider bit 2. AM_CD1 : AM Clock Divider bit 1. AM_CD0 : AM Clock Divider bit 0. Note : The AM_CD[2:0] is used to decrease frequency from FM - band to AM - band. Please set AM_CD to “0” at FM mode. AM_CD[2:0] 0,1 2 3 4 5 6 7 Bit 4 : Bit 3-0 : Bit 3 : Bit 2 : Bit 1 : Bit 0 : NA (Fixed to “0”) AMCAP[11:8] : AM Antenna Capacitor-Bank AMCAP_bit 11 AMCAP_bit 10 AMCAP_bit 9 AMCAP_bit 8 Divide-Rate Divider OFF 224 160 112 80 64 48 AM-RF frequency (In kHz) 0 (FM mode) 338 - 483 474 - 676 676 - 966 947 - 1353 1183 - 1692 1578 - 2256 Register 10h - DO_REF_CLK_CNF - DO output mode and reference clock configuration (Read/Write) 7 IPOL Bit 7-5 : Bit 4-3 : 6 5 DO_SEL[1:0] NA (Fixed to “0”) 4 3 EXT_CLK_CFG[1:0] 2 FS_S[2:0] 1 0 EXT_CLK_CFG[1:0] : External Clock Setting EXT_CLK_CFG[1:0] 00 01 10 11 Reference clock Off Oscillator clock source (External Clock source) 32768Hz crystal oscillator No use Bit 2-0 : FS_S[2:0] : SD (Station Detector) operation level setting No.A1990-14/23 LV23411V Register 11h - IF_SEL - IF frequency selection (Read/Write) 7 FLL_MOD Bit 7 : 6 5 4 AMIF[2:0] FLL_MOD: FLL operation mode 0 : Smoothing Filter = OFF 1 : Smoothing Filter = ON AMIF[2:0] : IF frequency setting at AM mode AMIF[2:0] 3 4 53kHz 64kHz 3 FMIF[3:0] 2 1 0 Bit 6-4 : 0 20kHz Bit 3-0 : 1 31kHz 2 42kHz 5 75kHz 6 86kHz 7 97kHz FMIF[3:0] : IF frequency setting at FM mode (kHz) RF_SEL 0 0 0 0 1 1 2 3 4 5 6 SE_AM FMIF[3:0] 7 8 9 10 11 12 13 14 15 112.5 125 137.5 150 162.5 175 187.5 212.5 225 237.5 250 262.5 275 287.5 312.5 325 112.5 127.5 142.5 157.5 157.5 172.5 187.5 202.5 217.5 232.5 247.5 262.5 277.5 292.5 307.5 322.5 Register 12h - REF_CLK_MOD - Slope correction (Read/Write) 7 6 5 4 REFMOD[7:0] Bit 7-0 : REFMOD[7:0] : Reference clock collection 3 2 1 0 No.A1990-15/23 LV23411V Register 13h - SM_CTRL - Statemachine control (Read/Write) 7 FLL_ON Bit 7 : 6 5 CLKS_SE[2:0] FLL_ON : FLL control 0 = FLL OFF 1 = FLL ON 4 3 nSD_PM 2 nIF_PM 1 CM_SE[1:0] 0 Bit 6-4 : CLKS_SE : Clock source selection 0 = No select 1 = Stereo Decoder Oscillator is selected 2 = IF Oscillator is selected 3 = AM Antenna Oscillator is selected 4 = FM RF Oscillator is selected 5 = AM RF Oscillator is selected 6 - 7 = No select Note : Bit[6-4] set oscillator source. Select arbitrary clock oscillator at tuning or calibrations or measure. Bit 3 : nSD_PM : Stereo Decoder PLL mute 0 = SD PLL Off (Calibration) 1 = SD PLL On (Normal operation) nIF_PM : IF PLL mute 0 = IF PLL Off (Calibration) 1 = IF PLL On (Normal operation) CM_SE : Command mode selection 0 = No command 1 = Measure mode 2 = Calibration mode 3 = Radio tuning (RF frequency tuning) mode Bit 2 : Bit 1-0 : Note : This bit used to select command mode. Select the arbitrary command to be executed. The command is executed by setting TARGET_VAL_L/H. Command execution time : SD calibration = 540ms IF calibration = 134ms RF (FM) tuning = 105ms RF (AM) tuning = 158ms Note: Please wait the time provided for the above-mentioned before all processing including reading the register after having executed the command. No.A1990-16/23 LV23411V Register 14h - REF_CLK_PRS - Reference clock pre-scaler (Read/Write) 7 IM_EVAS Bit 7 : 6 5 4 3 Reserved WAIT_SEL AM_FINE REFPRE[3:0] IM_EVAS : Image signal avoidance function ON/OFF 0 = OFF 1 = ON (Recommend) Reserved : Fixed to “0” WAIT_SEL : Selection mute release standby time after tuning 0 = 8ms wait 1 = 4ms wait AM_FINE : Selection AM_ANT adjustment standby time 0 = No wait when DAC value is changed 1 = 2ms wait when DAC value is changed REFPRE[3:0] : Reference Clock pre- scaler 0=1:1 1=1:2 2=1:4 … 15 = 1 : 32768 2 1 0 Bit 6 : Bit 5 : Bit 4 : Bit 3-0 : Register 15h - REF_CLK_DIV - Reference clock divider (Read/Write) 7 6 5 4 REFDIV[7:0] Bit 7-0 : REFDIV[7:0] : Reference Clock Divider 0 : Divide rate = 1 1 : Divide rate = 2 … 255 : Divide rate = 256 3 2 1 0 Register 16h - TARGET_VAL_L - Target Value Low Register (Read/Write) 7 6 5 4 TARGET[7:0] Bit 7-0 : TARGET[7:0] : Target frequency low 8 bit : Tuning frequency or Calibration frequency : low byte 3 2 1 0 Register 17h - TARGET_VAL_H - Target Value High Register (Read/Write) 7 6 5 4 3 TARGET[15:8] Bit 7-0 : TARGET[15:8] : Target frequency high 8 bit : Tuning frequency or Calibration frequency : high byte 2 1 0 With radio power ON, lower eight bits of the target frequency are set. Then, set higher eight bits of the target frequency to this register. The command is executed. TUNEPOS and TARGET : - AM mode : 1kHz span - FM mode : 10kHz span No.A1990-17/23 LV23411V Register 18h - RADIO_CTRL1 - Radio control 1 (Read/Write) 7 IQC_CTR Bit 7 : 6 5 4 3 2 IFPOL OSC_LEV[1:0] DEEM VOL[1:0] IQC_CTR : I/Q phase change 0 = Normal mode (Upper heterodyne) 1 = I/Q phase change : for image signal avoidance (Lower heterodyne) Note : Usually, no-need to change IF pole change by State Machine 0 = The IF frequency is added to local frequency (Normal) 1 = The IF frequency is subtracted from local frequency Note : Usually, no-need to change OSC_LEV[1:0] : RF-OSC oscillation level setting 0 = minimum level 3 = maximum level Note : 3dB steps, Level = 2 is recommended DEEM : De-emphasis setting 0 = 50μs : Korea China, Europe, Japan 1 = 75μs : USA VOL[1:0] : Volume setting 0 = minimum (VOL0) …… 3 = maximum (VOL3) EN_AMHC : AM High-cut Filter ON/OFF 0 = AM HCF OFF 1 = AM HCF ON 1 0 EN_AMHC Bit 6 : Bit 5-4 : Bit 3 : Bit 2-1 : Bit 0 : Register 19h - RADIO_CTRL2 - Radio control 2 (Read/Write) 7 Reserved Bit 7 : Bit 6 : Bit 5 : 6 5 Reserved EN_AMM Reserved : Fixed to “0” Reserved : Fixed to “1” EN_AMM : AM Mute ON/OFF 0 = AM mute OFF 1 = AM mute ON Reserved : Fixed to “0” IF_AGC_LEV : IF-AGC Level Control 0 = AGC slow mode 1 = AGC first mode RF_AGC_LEV[1:0] : RF-AGC Level Control 0 = AGC slow mode 1 = AGC normal mode 3 = AGC first mode EN_RFAGC : RF-AGC ON/OFF 0 = AGC OFF 1 = AGC ON (Normal) 4 Reserved 3 IF_AGC_LEV 2 1 RF_AGC_LEV[1:0] 0 EN_RFAGC Bit 4 : Bit 3 : Bit 2-1 : Bit 0 : No.A1990-18/23 LV23411V Register 1Ah - RADIO_CTRL3 - Radio control 3 (Read/Write) 7 DEEM_100 Bit 7 : 6 5 4 NA IF_AGC_CAP DEEM_100 : Additional De-emphasis (100μs) 0 = 0μs (Default setting) 1 = 100μs (DEEM = 1 : 75μS) NA IF_AGC_CAP 0 = OFF (Normal) 1 = ON AM_WIDE_AGC_OFF[1:0] : AM WIDE AGC OFF Level Control 0 = First mode 3 = Slow mode AM_WIDE_AGC_ON[1:0] : AM WIDE AGC ON Level Control 0 = WIDE AGC OFF 1 = First mode 3 = Slow mode 3 2 AM_WIDE_AGC_OFF 1 0 AM_WIDE_AGC_ON Bit 6 : Bit 4 : Bit 3-2 : Bit 1-0 : Register 1Ch - STEREO_CTRL1 - Stereo control 1 (Read/Write) 7 CRC[1:0] Bit 7-6 : 5 4 SS_SP2 Reserved CRC[1:0] : Capture Range Control 0 = Narrow mode 3 = Wide mode 6 3 Reserved 2 PICAN_EN 1 FOSTEREO 0 ST_M Bit 5 : SS_SP2 : Stereo=ON sensitivity speed2 (First mode) 0 : First mode = OFF 1 : First mode = ON (Recommend) Reserved : Fixed to “0” Reserved : Fixed to “0 PICAN_EN : PILOT signal Cancellation ON/OF 0 = OFF 1 = ON (Recommend) FOSTEREO : Forced Stereo 0 = OFF (Normal) 1 = ON ST_M : Mono/Stereo setting 0 = Stereo on (Normal) 1 = Stereo off (Forced mono) Bit 4 : Bit 3 : Bit 2 : Bit 1 : Bit 0 : No.A1990-19/23 LV23411V Register 1Dh - STEREO_CTRL2 - Stereo control 2 (Read/Write) 7 NA Bit 7-5 : Bit 4 : 6 NA FOAMAGC 0 : Forced - AGC = OFF 1 : Forced - AGC = ON Reserved: Fixed to “0” OVER_MOD : Over-modulation detector ON/OFF 0 = OFF 1 = ON CPAJ[1:0] : Channel separation adjacent 0 = Minimum Sub-signal level 7 = Maximum Sub-signal level 5 4 FOAMAGC 3 Reserved 2 OVER_MOD 1 CPAJ[2:0] 0 Bit 3 : Bit 2 : Bit 1-0 : Register 1Eh - RADIO_CTRL4 - Radio control 4 (Read/Write) 7 6 5 4 3 SOFTST[2:0] SOFTMU[2:0] Bit 7-5 : SOFTST[2:0] : Soft Stereo Function (Stereo-Blend) 0 : Soft Stereo = OFF 7 : Soft Stereo = Lev7 (Max) Bit 4-2 : SOFTMU[2:0] : Soft Audio mute Function 0 : Soft mute = OFF 7 : Soft mute = Lev7 (Max) LEVSHIF : Audio Line-out DC level shift 0 = Normal DC level (VCC = 5.0V) 1 = DC level is shifted (VCC =9.0V) FO_SOFTST : Forced Soft Stereo Function 0 : ON (Normal) 1 : OFF 2 1 LEVSHIF 0 FO_SOFTT Bit 1 : Bit 0 : No.A1990-20/23 LV23411V Register 1Fh - RADIO_CTRL5 - Radio control 5 (Read/Write) 7 RF_SEL Bit 7 : 6 5 4 IFRIM nAGC_SPD SE_FM/AM RF_SEL : RF tuning range select 0 = Normal ( Japan/USA/Europe) 1 = OILT (65MHz to 74MHz) IFRIM : IF OSC limit setting 0 : Max = 350kHz (FM mode) 1 : Max = 150kHz (AM mode) nAGC_SPD : IF AGC speed setting 0 = High speed (FM mode) 1 = Normal (AM mode) SE_FM/AM : AM/FM mode select 0 = FM mode 1 = AM mode AMP_CTR : Audio Amp ON/OFF 0 = OFF 1 = ON MUTE : Audio Mute ON/OFF 0 = ON 1 = OFF 3 AMP_CTR 2 MUTE 1 AM_CAL 0 PW_RAD Bit 6 : Bit 5 : Bit 4 : Bit 3 : Bit 2 : Bit 1 : AM_CAL : AM Calibration (Antenna tuning mode) 0 = AM Receiving mode (Normal) 1 = AM Calibration mode (AM antenna tuning mode) Note : Set this bit to “1”, if ANT calibration frequency is measured. PW_RAD: Radio Power 0 = Power OFF (power save mode) 1 = Power ON Bit 0 : *1 : After the VCC voltage is impressed, PW_RAD is automatically set to "0" in 50ms. *2 : When the VCC voltage is dropped once, content of registers other than PW_RAD becomes irregular. No.A1990-21/23 LV23411V Test Circuit I2C_Bus C10 0.1μF 50Ω 50Ω 50Ω BPF L2 39nH L1 39nH C9 22μF R2 4.7kΩ R3 open X1 32.768Hz 30 29 28 27 26 25 24 23 22 21 R1 4.7kΩ 20 19 18 17 16 MPX IN_OUT Vref3(4.3V) IF AGC CAP ST OUT 14 ST FM ANT FLL CAP SDA Vref2(3V) Vref1(4.3V) LV23411V VCC_Low AM_LCF AM AGC SD OUT R OUT L OUT GND2 AM CAP AM ANT AM ref GND1 50Ω Dummy ANT T1 1 2 3 4 5 6 7 8 9 10 11 12 13 15 C1 0.1μF C2 1μF C3 1μF C4 C5 1μF 1μF C6 0.047μF VCC=5V:short VCC=9V:open SD C7 C8 0.1μF 22μF MPX IN_OUT GND Lout Rout VCC=5V(9V) PS No.A1990-22/23 VCC CLK IN GND5 L1 GND4 GND3 SCL NC NC L2 LV23411V Application Circuit Example I2C_Bus C10 0.1μF BPF L2 39nH L1 39nH C9 22μF R2 4.7kΩ R3 open X1 32.768Hz 17 IF AGC CAP ST OUT 30 FM ANT 29 GND5 28 FLL CAP 27 GND4 26 L2 25 MPX IN_OUT Vref3(4.3V) 24 L1 23 GND3 22 Vref2(3V) 21 SDA R1 4.7kΩ 20 19 SCL NC 18 SD ADJ 16 CLK IN Vref1(4.3V) LV23411V VCC_Low AM_LCF AM AGC SD OUT R OUT L OUT GND2 AM CAP AM ANT AM ref GND1 T1 L3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 For AM Loop antenna C1 0.1μF C2 1μF C3 1μF C4 C5 1μF 1μF C6 0.047μF VCC=5V:short VCC=9V:open SD C7 C8 0.1μF 22μF AM CAP AM ref AM ANT GND LO1 For AM Ferrite antenna MPX IN_OUT GND ST VCC=5V(9V) Lout Rout SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein. 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No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written consent of SANYO Semiconductor Co.,Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO Semiconductor Co.,Ltd. product that you intend to use. Upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third party. SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's intellctual property rights which has resulted from the use of the technical information and products mentioned above. This catalog provides information as of October, 2011. Specifications and information herein are subject to change without notice. PS No.A1990-23/23 VCC