LV4912GP

Ordering number : ENA1173A Bi-CMOS LSI LV4912GP Overview Crass-D Audio Power Amplifier BTL 2W×1ch The LV4912GP is analog input type digital power amplifier with 2W × 1 channel. By using an original feed back technology, it improves sound quality through it is class-D power amplifier and the LC filter in the output stage can be deleted as application. Features • Enabling output LC filter-less. • Class-D amplifier system of the output BTL type. • Improve the sound quality by the use of original feedback technology. • Realized high efficiency class-D amplifier. • Reduce the pop sound at ON/OFF state by the use of soft mute function. • Full complement of built-in protection circuits : over current protection, thermal protection, and low power supply voltage protection circuits. • Internal oscillation frequency : 280kHz Functions • Output power • THD + N • Noise • Package : 2W(VD = 5V, RL = 4Ω, THD + N = 10%) : 0.4% (VD = 5V, RL = 4Ω, fin = 1kHz, PO = 1W, Filter : AES17) : 70µVrms (Filter : DIN AUDIO) VCT24 (3.5 × 3.5) Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment (home appliances, AV equipment, communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee thereof. If you should intend to use our products for applications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our customer shall be solely responsible for the use. Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer' s products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer' s products or equipment. 70208 MS / 51408 MS PC 20080331-S00006 No.A1173-1/11 LV4912GP Specifications Maximum Ratings at Ta = 25°C Parameter Maximum supply voltage Allowable power dissipation Operating temperature Storage temperature Symbol VD Pd max Topr Tstg Conditions Externally applied voltage Mounted on a board * Ratings 6 1 -20 to +75 -40 to +150 Unit V W °C °C ∗ When mounted on the specified printed circuit board : 40mm×50mm×1.6mm, glass epoxy Recommended Operation Conditions at Ta = 25°C Parameter Supply voltage range Load impedance renge Symbol VD RL Conditions min Externally applied voltage Speaker load 2.7 4 Ratings typ 5 max 5.5 V Ω Unit Electrical Characteristics at Ta = 25°C, VD = 5V, RL = 4Ω, L = 22µH, C = 0.33µF Parameter Operating current Standby current Mute current Quiescent current Main amplifier Voltage gain Total harmonic distortion Output power Ripple rejection ratio Noise Digital input High-level output voltage Low-level output voltage Protection circuit Power supply voltage drop protection circuit upper limit value Power supply voltage drop protection circuit lower limit value Note : The values of these characteristics were measured in the SANYO test environment. The actual values in an end system will vary depending on the printed circuit board pattern, the external components actually used, and other factors. UV_LOWER VD pin voltage monitor 2.2 V UV_UPPER VD pin voltage monitor 2.3 V VIH VIL STBY pin, MUTE pin STBY pin, MUTE pin 3 0.3 V V VG THD+N PO SVRR VNO fin = 1kHz, VO = 0dBm PO = 1W, fin = 1kHz, AES17 THD+N = 10%, fin = 1kHz, AES17 fr = 100Hz, Vr = -15dBm, Rg = 0, DIN AUDIO Rg = 0, DIN AUDIO 1.6 50 21.5 23.5 0.4 2 60 70 210 25.5 0.7 dB % W dB µVrms Ist Imute ICCO STBY = L, MUTE = L, LC less, RL = OPEN STBY = H, MUTE = L, LC less, RL = OPEN STBY = H, MUTE = H, LC less, RL = OPEN 1 4.5 6 8 7.5 10 µA mA mA Symbol Conditions min Ratings typ max Unit Package Dimensions unit : mm (typ) 3322A 1.2 Pd max -- Ta Specified board Specified board : 40 × 50 × 1.6mm3 glass epoxy TOP VIEW 3.5 SIDE VIEW BOTTOM VIEW (0.13) Allowable power dissipation, Pd max – W 1 (0.125) (C0.17) 3.5 0.8 0.6 0.6 0.4 24 21 0.5 SIDE VIEW 0.8 0.4 (0.5) 0.2 Independent IC 0.11 0.25 (0.035) 0 – 20 0 20 40 60 75 80 100 SANYO : VCT24(3.5X3.5) Ambient temperature, Ta – °C No.A1173-2/11 LV4912GP LV4912GP customer bread board rev.1.0 Size : 40mm × 50mm × 1.6mm Pattern Top Layer Bottom Layer No.A1173-3/11 LV4912GP Block Diagram and Application Circuit Example (RL = 4Ω) PRE_VD C3 1µF PRE_GND PWR_VD PWR_GND 22µH OUT+ L1 C2 + C1 100µF 1µF VD OUTPUTSTAGE 1µF IN+ C4 IN C5 1µF RECEIVER CONTROL DELAY OUTPUTSTAGE C8 0.33µF C9 0.33µF C10 1µF RL 22µH OUTL2 0-5V 0-5V STBY MUTE MUTECAP BIASCAP C6 1 µF C7 1µF SEQUENCE VBIAS Under Voltage Over Current Thermal Protection Protection Protection VCC SUPPLY IREF LV4912GP Application (RL = 4Ω) Part List Parts Name CVD CVD CIN CMUTE CBIASCAP LO CO Part No. C1 C2, C3 C4, C5 C6 C7 L1, L2 C8, C9, C10 Power supply capacitor for VD High-frequency cut capacitor for VD Input capacitor Capacitor for soft mute Input coupling capacitor for Internal power supply (VBIAS) Output L. P. F. coil Output L. P. F. capacitor Description Function Pin Assignments PWR_GND OUT+ OUT- NC NC 20 24 NC PRE_VD PRE_GND VIN+ VINNC 1 2 3 4 5 6 7 23 22 21 NC 19 18 17 16 15 14 13 NC PWR_VD TEST2 TEST1 STBY MUTE 12 8 9 10 11 BIASCAP MUTECAP NC NC NC NC Top view No.A1173-4/11 LV4912GP Pin Equivalent Circuit Pin No. 1 2 3 4 Pin Name NC PRE_VD PRE_GND VIN+ I I/O No connection Power supply pin Pre ground Input plus Description Equivalent Circuit VD 4 300Ω 30kΩ VBIAS GND 5 VIN- I Input minus VD 5 300Ω 30kΩ VBIAS GND 6 7 8 9 10 NC NC NC NC BIASCAP O No connection No connection No connection No connection Internal power supply decoupling capacitor connection VD 10 200kΩ 100kΩ 90kΩ GND 11 12 NC MUTECAP O No connection Mute capacitor connection VCC VD 12 200kΩ GND 13 MUTE I Mute control pin VD 100kΩ 13 200kΩ VCC GND Continued on next page. No.A1173-5/11 LV4912GP Continued from preceding page. Pin No. 14 Pin Name STBY I/O I Description Standby control pin Equivalent Circuit VD 100kΩ 14 200kΩ GND 15 16 17 18 19 20 21 TEST1 TEST2 PWR_VD NC NC NC OUTO Test pin Test pin Power supply pin No connection No connection No connection Output pin, minus VD 21 GND 22 23 PWR_GND OUT+ O Power ground Output pin, plus VD 23 GND 24 NC No connection No.A1173-6/11 LV4912GP Description functions 1. System Standby Each bias can be turned on/off by switching the STBY pin (pin 14) into high or low. The bias is turned off when the STBY pin is low. Conversely, the bias is turned on when the STBY pin is high. STBY pin (pin 14) High Low Bias condition ON OFF 2. Mute Function The mute of the output and reduction of power-on popping noise are mainly performed by the use of this function. By switching between high and low on the MUTE pin (pin 13), the output can be muted. The MUTE pin enters the mute mode (PWM output stops) when the MUTE pin is low. Also the MUTE pin enters the operation mode (normal operations) when the MUTE pin is high. MUTE pin (pin 13) High Low Conditions Operation mode Mute mode We recommend the following sequence for reduction of the popping noise when power is on/off. Also, we recommend the following ON Time and OFF Time when P.4 the application circuit is used. (1) Power On sequence The ON Time should secure more than 150msec for reduction of the popping noise. STBY Internal power supply MUTE MUTECAP Output pin ON Time No.A1173-7/11 LV4912GP (2) Power Down sequence The OFF Time should secure more than 100msec for reduction of the popping noise. STBY Internal power supply MUTE MUTECAP Output pin OFF Time Capacitors for Power supply and pin arrangement 1. Capacitors for power supply The capacitors C2 and C3 for power supply connected between IC pins must be inserted using the shortest lines possible. 17 PWR_VD C2 1µF 22 PWR_GND 2 PRE_VD C3 1µF 3 PRE_GND 2. Pin arrangement of the test pins (pins 15 and 16) The test pins (pins 15 and 16) are used as pins for testing before shipment. These pins are not used normally. Therefore, these pins must be left open if the pin arrangement is not performed. Please make sure to connect these pins to GNDs if the pin arrangement is performed. No.A1173-8/11 LV4912GP General Characteristics Ist – VD 0.18 0.16 7 Imute – VD RL = 4Ω STBT = L, MUTE = L RL = 4Ω STBT = L, MUTE = L Mute current, Imute – mA 3 3.5 4 4.5 5 5.5 6 6 Standby current, Ist – µA 0.14 0.12 0.1 0.08 0.06 0.04 0.02 0 2.5 5 4 3 2 1 0 2.5 3 3.5 4 4.5 5 5.5 PCA02904 6 Supply voltage, VD – V 16 14 Supply voltage, VD – V 10 7 5 3 2 RL = 4Ω STBT = H, MUTE = H ICCO – VD PO – VIN VD = 5V AES17 Quiescent current, ICCO – mA 10 8 6 4 2 0 2.5 Output power, PO – W 12 1 7 5 3 2 0.1 7 5 3 2 RL = 4Ω RL = 8Ω 3 3.5 4 4.5 5 5.5 6 0.01 7 5 3 2 0.001 10 2 3 5 7 100 2 3 5 7 1000 Supply voltage, VD – V 3.5 PO – VD VD = 5V RL = 4Ω AES17 Output power, PO – W Input voltage, VIN – mVp 2.5 PO – VD 3 VD = 5V RL = 8Ω AES17 2 Output power, PO – W 2.5 2 1.5 THD = 10% 1.5 THD = 10% 1 THD = 1% 1 THD = 1% 0.5 0.5 0 2 3 4 5 6 7 0 2 3 4 5 6 7 Supply voltage, VD – V 10 7 5 3 2 1 7 5 3 2 0.1 7 5 3 2 0.01 0.001 2 3 5 70.01 23 5 7 0.1 23 571 23 5 7 10 Supply voltage, VD – V 10 7 5 3 2 0.1 7 5 3 2 0.1 7 5 3 2 0.01 0.001 2 3 5 70.01 23 5 7 0.1 23 571 23 5 7 10 THD+N – PO Total harmonic distortion, THD+N – % THD+N – PO VD = 5V RL = 8Ω AES17 Total harmonic distortion, THD+N – % VD = 5V RL = 4Ω AES17 f = 6.67kHz f = 6.67kHz f = 1kHz f = 1kHz f = 100Hz f = 100Hz Output power, PO – W Output power, PO – W No.A1173-9/11 LV4912GP Total harmonic distortion, THD+N – % 10 7 5 3 2 1 7 5 3 2 0.1 7 5 3 2 0.01 7 5 3 2 0.001 10 THD+N – f VD = 5V RL = 4Ω PO = 1W AES17 10 Response – f VD = 5V RL = 4Ω PO = 1W AES17 5 Response – dB 23 5 7 100 23 5 7 1k 23 5 7 10k 23 5 7 100k 0 –5 – 10 – 15 – 20 10 23 5 7 100 23 5 7 1k 23 5 7 10k 23 5 7 100k Frequency, f – Hz 30 20 10 0 Frequency, f – Hz VD = 5V RL = 4Ω PO = 1W AES17 70 Phase – f Ripple rejection ratio, SVRR – dB SVRR – BIASCAP 60 50 Phase – deg – 10 – 20 – 30 – 40 – 50 – 60 10 23 5 7 100 23 5 7 1k 23 5 7 10k 23 57 100k 40 30 20 10 0 0.1 VD = 5V RL = 4Ω Vr = -15dBm DIN AUDIO 23 571 23 Frequency, f – Hz 100 Bias capacitance, Bias Cap – µF 5 7 10 23 5 7 100 23 57 1000 Efficiency – PO VD = 5V AES17 RL = 8Ω RL = 4Ω 1.2 Pd – PO VD = 5V AES17 Power dissipation, Pd – W 80 1 Efficiency – % 0.8 60 0.6 RL = 4Ω 40 0.4 20 0.2 RL = 8Ω 0 0 0.5 1 1.5 2 0 0 0.5 1 1.5 2 Temperature Characteristics 6 Output power, PO – W Imute – Ta Output power, PO – W 20 18 ICCO – Ta Quiescent current, ICCO – mA 5 Mute current, Imute – mA 16 14 12 10 8 6 4 2 4 3 2 1 0 – 50 VD = 5V RL = 4Ω Rg = 0 STBY = H MUTE = L – 25 0 25 50 75 100 0 – 50 VD = 5V RL = 4Ω Rg = 0 STBY = H MUTE = H – 25 0 25 50 75 100 Allowable temperature, Ta – °C Allowable temperature, Ta – °C No.A1173-10/11 LV4912GP 0.8 THD+N – Ta VD = 5V RL = 4Ω PO = 1W fin = 1kHz AES17 3.0 PO – Ta Total harmonic distortion, THD+N – % 0.7 0.6 0.5 0.4 0.3 0.2 0.1 2.5 RL = 4Ω fin = 1kHz THD+N = 10% AES17 VD = 5V Output power, PO – W 2.0 1.5 1.0 VD = 3.6V VD = 3V 0.5 0 – 50 – 25 0 25 50 75 100 0 – 50 – 25 0 25 50 75 100 Allowable temperature, Ta – °C 25 Allowable temperature, Ta – °C 90 80 VG – Ta Vno – Ta 24 Voltage gain, VG – dB 70 Noise, Vno – µVrms VD = 5V RL = 4Ω VIN = 0dBm DIN AUDIO – 25 0 25 50 75 100 60 50 40 30 20 10 23 22 21 20 – 50 0 – 50 VD = 5V RL = 4Ω Rg = 0 – 25 0 25 50 75 100 Allowable temperature, Ta – °C Allowable temperature, Ta – °C SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein. SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO Semiconductor Co.,Ltd. products described or contained herein are controlled under any of applicable local export control laws and regulations, such products may require the export license from the authorities concerned in accordance with the above law. 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SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's intellctual property rights which has resulted from the use of the technical information and products mentioned above. This catalog provides information as of July, 2008. Specifications and information herein are subject to change without notice. PS No.A1173-11/11