LV4924VH

Ordering number: ENA1997 LV4924VH Overview Bi-CMOS IC Class-D Audio power Amplifier Power cell BTL 10W×2ch The LV4924VH is a 2-channel full-bridge driver for digital power amplifiers. It requires a PWM modulator IC in the previous stage. This IC is a power cell that takes in PWM signals as an input and is used to form a digital amplifier system for TVs, amusement equipment, and other such systems. Features • BTL output, class D amplifier system • High-efficiency class D amplifier • Muting function reduces impulse noise at power on / off • Protection circuits incorporated for over-current, thermal, supply voltage drop, output offset detector • Built-in bootstrap diodes • • • • Output 15W (VD=16V, RL=8Ω, fIN=1kHz, AES17, THD+N=10%) Output 10W (VD=13V, RL=8Ω, fIN=1kHz, AES17, THD+N=10%) Efficiency : 89% (VD=13V, RL=8Ω, fIN=1kHz, PO=10W) THD+N : 0.1% (VD=13V, RL=8Ω, fIN=1kHz, PO=1W, Filter: AES17) Specification Maximum Ratings / Absolute Maximum Ratings /Ta=25°C Parameter Maximum supply voltage Maximum PWM pin voltage Maximum pull-up pin voltage Allowable power dissipation Maximum junction temperature Operating temperature Storage temperature Symbol VD VIN Vpup max Pd max Tj max Topr Tstg Conditions Externally applied voltage PWM_A1,PWM_A2,PWM_B1,PWM_B2 NPN Open collector pin Exposed Die-pad Soldered *1 Ratings 22 6 20 4.6 150 -25 to 75 -50 to 150 Unit V V V W °C °C °C *1 Customer bread board rev.1.0: 90.0mm × 70.0 mm × 1.6 mm (two-layer) Material: glass epoxy Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment. The products mentioned herein shall not be intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee thereof. If you should intend to use our products for new introduction or other application different from current conditions on the usage of automotive device, communication device, office equipment, industrial equipment etc. , please consult with us about usage condition (temperature, operation time etc.) prior to the intended use. If there is no consultation or inquiry before the intended use, our customer shall be solely responsible for the use. Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer ' s products or equipment. N1611 SY 20111031-S00002 No.A1997-1/15 LV4924VH Recommended Operating Range at Ta = 25°C Parameter Recommended supply voltage range Recommended PWM pin voltage Recommended pull-up supply voltage Recommended load resistance RL Speaker load 4 8 Ω VIN Vpup PWM_A1,PWM_A2,PWM_B1,PWM_B2 NPN Open collector pin 0 3.3 5 18 V V Symbol VD Conditions Externally applied voltage Ratings min 9 typ 13 max 20 Unit V Electrical Characteristics Ta=25°C, VD=13V, RL=8Ω, L=22μH (TOKO: A7040HN-220M), C=0.33μF (Matsuo: 553M6302-334K) Parameter Quiescent current Current at MUTE Standby current H input voltage L input voltage H input current L input current Output pin leakage current Output pin current Power Tr ON resistance Turn ON delay time Turn OFF delay time Rise-up time *1 Symbol ICCO Imute Ist VIH VI L I IH IIL IOFF IOL Rds ON td ON td OFF tr Conditions STBY=H, MUTE=H, fIN=384kHz, Duty=50% STBY=H, MUTE=L, VIN=GND STBY=L, MUTE=L, VIN=GND PWM_A, PWM_B, STBY, MUTE PWM_A, PWM_B, STBY, MUTE VIN=5V VIN=GND NPN Open collector output OFF-stage 5.0V pull-up NPN Open collector output ON-stage, VOL=0.4V Id=1A fIN=384kHz, Duty=50% fIN=384kHz, Duty=50% fIN=384kHz, Duty=50% Ratings min 30 2 2.3 0 -20 0.5 220 30 30 5 5 50 50 20 20 1 typ 38 4 max 45 6 10 5.5 1.0 60 Unit mA mA μA V V μA μA μA mA mΩ ns ns ns ns Fall time tf fIN=384kHz, Duty=50% *1 : The maximum power transistor ON resistance(RDSON) is 270mΩ(design guarantee value). circuit board pattern, the components used, and other factors. Note : The value of these characteristics were measured in SANYO test environment. The actual value in an end system will vary depending on the printed Electrical Characteristics (Reference value: The table below shows the reference value when FPGA equivalent to the Sanyo reference model is used.) Parameter Output 1 Output 2 Symbol PO1 PO2 Conditions THD+N=10%, fIN=1kHz, AES17 VD=16V, THD+N=10%, fIN=1kHz, AES17 Ratings min typ 10 15 max Unit W W Total harmonic distortion THD+N PO=1W, fIN =1kHz, AES17 0.1 % Note : The value of these characteristics were measured in SANYO test environment. The actual value in an end system will vary depending on the printed circuit board pattern, the components used, and other factors. Audio data IIS MCLK BCLK LRCLK SDATA PWM BD-mode MCLK BCLK FPGA LRCLK SDATA LV4924VH No.A1997-2/15 LV4924VH Package Dimensions unit : mm (typ) 3417 TOP VIEW 15.0 36 (4.7) BOTTOM VIEW 5.6 7.6 12 1.625 0.65 0.22 0.2 (0.68) 0.05 2.17 (1.5) SIDE VIEW 1.7 MAX 0.5 SANYO : HSSOP36(275mil) Pin Assignment (3.5) BOOT_CH1_P BOOT_CH1_N BOOT_CH2_N BOOT_CH2_P OUT_CH2_P OUT_CH1_N OUT_CH1_N OUT_CH2_N OUT_CH2_N OUT_CH1_P OUT_CH1_P VDDA1 OUT_CH2_P VDDA2 PVD1 PVD1 36 35 34 33 32 31 30 29 28 GND 27 26 25 24 23 19 20 PVD2 21 LV4924VH 1 STBY 2 MUTE 3 SOS 4 NC1 5 NC2 6 NC3 7 NC4 8 PWM_A1 9 PWM_B1 GND 10 PWM_B2 11 PWM_A2 12 NC5 13 NC6 14 NC7 15 NC8 16 NC9 17 NC10 Top view NC11 No.A1997-3/15 PVD2 22 18 LV4924VH Reference data for thermal design Overall view of substrate Mounted on a specified board (Customer bread board rev.1.0): 90.0mm × 70.0 mm × 1.6 mm (two-layer) Material: glass epoxy Pd max-Ta 6 Pd max -- Ta Specified board : 90.0 × 70.0 × 1.6mm3 glass epoxy Exposed Die-Pad Soldered Exposed Die-Pad Not Soldered 2.7 Allowable power dissipation, Pd max -- W 5 4.6 4 3.2 3 2 1.9 1 0 --25 0 25 50 75 100 Ambient temperature, Ta -- C 1. Data of the Exposed Die-Pad (heat spreader) substrate as mounted represents the value in the state where the exposed Die-Pad surface is wet for 90% or more. 2. For the set design, derating design should be made while ensuring allowance. Stresses to become an object of derating are the voltage, current, junction temperature, power loss and mechanical stresses including vibration, impact and tension. Accordingly, these stresses must be as low or small as possible in the design. Approximate targets for general derating are as follows: (1) Maximum value 80% or less for the voltage rating. (2) Maximum value 80% or less for the current rating. (3) Maximum value 80% or less for the temperature rating. 3. After set design, be sure to verify the design with the product. Also check the soldered state of the Exposed Die-Pad, etc. and verify the reliability of the soldered joint. If any void or deterioration is observed in these sections, thermal conduction to the substrate is deteriorated, resulting in thermal damage of IC. No.A1997-4/15 LV4924VH Block Diagram GND Pin Equivalent Circuit Pin No. 1 Pin name STBY I/O I Standby mode control Description Equivalent Circuit PVD 1 GND 2 MUTE I Muting control GND PVD VDDA 2 GND Continued on next page. No.A1997-5/15 LV4924VH Continued from preceding page. Pin No. 3 Pin name SOS I/O I Description Internal protection circuit detection output (OR output of the thermal detection, over-current, voltage drop protection, offset detection circuit) of an NPN open collector output type Equivalent Circuit PVD 3 GND 4 5 6 7 8 9 10 11 NC1 NC2 NC3 NC4 PWM_A1 PWM_B1 PWM_B2 PWM_A2 I I I I Non connection Non connection Non connection Non connection PWM input (plus input) of OUT_CH1_P PWM input (negative input) of OUT_CH1_N PWM input (negative input) of OUT_CH2_N PWM input (plus input) of OUT_CH2_P PVD VDDA GND FIN 12 13 14 15 16 17 18 19, 20 21, 22 26, 27 28, 29 33, 34 GND NC5 NC6 NC7 NC8 NC9 NC10 NC11 PVD2 OUT_CH2_P OUT_CH2_N OUT_CH1_N OUT_CH1_P O O O O ground Non connection Non connection Non connection Non connection Non connection Non connection Non connection Power pin Output pin, Channel 2 plus Output pin, Channel 2 minus Output pin, Channel 1 minus Output pin, Channel 1 plus PVD GND 23 24 25 30 31 32 35, 36 BOOT_CH2_P VDDA2 BOOT_CH2_N BOOT_CH1_N VDDA1 BOOT_CH1_P PVD1 I/O O I/O I/O O I/O - Bootstrap I / O pin, channel 2 plus Internal power supply decoupling capacitor connection Bootstrap I / O pin, channel 2 minus Bootstrap I / O pin, channel 1 minus Internal power supply decoupling capacitor connection Bootstrap I / O pin, channel 1 plus Power pin No.A1997-6/15 LV4924VH Description of functions System Standby The built-in 5V regulator is turned ON / OFF by changing over "H" and "L" of "STBY". The regulator is turned OFF with "STBY" at "L" and ON with "STBY" at "H". This signal also causes initialization of the internal logic initialization with "L" and the normal mode with "H". MUTE Function The MUTE function is mainly for muting of the output and for reduction of pop noise at power ON. Muting the output The output PWM can be turned ON / OFF by changing over "H" and "L" of "MUTE". The PWM output is stopped (putting all of PWM outputs at high impedance) with "MUTE" at "L" and enters the normal operation mode with "MUTE" at "H". Sequence at power ON To reduce the pop noise, turn ON power supply while controlling in the following timing (PWM=BD mode). In particular, all of inputs of PWM must be held at "L" at canceling of MUTE function. * Please observe the following items for the destruction prevention of the output transistor. (1) Under all conditions must control the period at the "H" level about the PWM input so as not to become more than 200μs when period of the "H" level MUTE and STBY signals both. No.A1997-7/15 LV4924VH Sequence at power OFF To reduce the pop noise, turn OFF power supply while controlling in the following timing (PWM=BD mode). Protection Circuit LV4924VH incorporates the over-current protection circuit, thermal protection circuit, supply voltage drop protection circuit and output offset detection protection circuit. Activation of any one of these circuits causes the SOS output pin to become active and thus "L". Over-current protection circuit This circuit is a protection circuit* to protect the output transistor from the over-current and compatible with any mode of lightning, ground fault, and load short-circuit. Protection is done when the detection current value (about 6A) set inside IC is reached, forcing the output transistor to remain OFF for about 20μs. After forced OFF, the transistor returns automatically to the normal operation and performs protection again if the over-current continues to flow. Output Current Control Operation Self-recovery & Normal Operation Internal Control Signal * The over-current protection circuit functions only to avoid the abnormal state, such as output short-circuit, etc., temporarily, and does not guarantee to offer the protection to prevent damage to IC. No.A1997-8/15 LV4924VH Thermal protection circuit This circuit detects the temperature (150°C or more) inside LSI for protection. While this protection circuit is active, the output Tr is turned OFF on both high- and low-sides, putting the output in the high-impedance state. This operation is also provided with the hysteresis. Supply voltage drop protection circuit To avoid unstable operation at low voltages, this circuit monitors the PVD pin voltage and turns ON the amplifier when this voltage exceeds the Attack voltage (VD = 7V typ.). In addition, to avoid unstable operation when the PVD pin voltage has dropped because of certain reasons, the Recover voltage (VD = 6V typ.) is set. Both Attack and Recover voltages have the hysteresis (about 1V) to prevent continuous ON / OFF operation of the supply voltage drop protection circuit. PVD Pin Voltage Recovery Voltage Internal Control Signal Output offset detection protection circuit This circuit is a protection circuit intended to alleviate burn of the loudspeakers when DC outputs to the BTL output for a certain period or more. The circuit detects the case in which each BTL input of each channel continues to disagree (for about 300ms), turns OFF the output Tr on both high- and low-sides, and puts the output in the high-impedance state. No.A1997-9/15 LV4924VH Application Circuit GND * SOS of pin 3 is the open collector output. Therefore, to monitor this output with CPU, it is necessary to pull up (resistor: R1) at power supply of CPU, etc. When the output is not to be used (not to be monitored), it is not necessary to pull-up the resistor. GND No.A1997-10/15 LV4924VH Characteristics Data: L=22μH (TOKO: A7040HN-220M), C=0.33μF (Matsuo: 553M6302-334K) 0.3 Ist -- VD 0.3 Ipd -- Ta V D =13V, RL=8 IN=Low, STBYB=Low MUTEB=Low Standby current, Ist - A 0.2 Standby current, Ist - A 16 18 20 0.2 0.1 0.1 0 0 2 4 6 8 10 12 14 22 24 0 -40 -20 0 20 40 60 80 100 120 Supply voltage, VD - V 8 7 Ambient temperature, Ta - C 8 7 IMUTE -- VD IMUTE -- Ta V D =13V, RL=8 IN=0, STBYB=High MUTEB=Low RL=8 , IN=Low STBYB=High, MUTEB=Low Muting current, Imute - mA Muting current, Imute - mA 6 5 4 3 2 1 0 6 5 4 3 2 1 0 -40 4 6 8 10 12 14 16 18 20 22 -20 0 20 40 60 80 100 120 Supply voltage, VD - V 70 Icco -- VD Ambient temperature, Ta - C 70 Icco -- Ta 60 Quiescent current, Icco - mA RL=8 IN=Duty50%[0 to 3.3V] STBYB=High, MUTEB=High Quiescent current, Icco - mA 60 50 VD=13V, RL=8 IN=Duty50%[0 to 3.3V] STBYB=High, MUTEB=High 50 40 30 40 30 20 10 0 20 10 0 -40 4 6 8 10 12 14 16 18 20 22 -20 0 20 40 60 80 100 120 Supply voltage, VD - V 6 VDD1,2 -- VD Ambient temperature, Ta - C 6 VDD1,2 -- Ta RL=8 5 5 VDDA1,2[V] VDDA1,2[V] 4 4 3 3 2 2 1 1 0 4 6 8 10 12 14 16 18 20 22 0 -40 VD=13V RL=8 -20 0 20 40 60 80 100 120 Supply voltage, VD - V Ambient temperature, Ta - C No.A1997-11/15 LV4924VH 60 td ON -- VD 60 td ON -- Ta VD=13V RL=8 Turn ON delay time, td ON - nsec 50 50 Turn ON delay time, td ON - nsec 40 40 30 30 20 20 10 10 0 8 10 12 14 16 18 20 22 0 -40 -20 0 20 40 60 80 100 120 Supply voltage, VD - V 60 td OFF -- VD Ambient temperature, Ta - C 60 td OFF -- Ta Turn OFF delay time, td OFF - nsec 40 Turn OFF delay time, td OFF - nsec 50 50 VD=13V RL=8 40 30 30 20 20 10 10 0 8 10 12 14 16 18 20 22 0 -40 -20 0 20 40 60 80 100 120 Supply voltage, VD - V 30 tr -- VD Ambient temperature, Ta - C 30 tr -- Ta VD=13V RL=8 Rise-up time, tr - nsec Rise-up time, tr - nsec 10 12 14 16 18 20 22 20 20 10 10 0 8 0 -40 -20 0 20 40 60 80 100 120 Supply voltage, VD - V 30 tf -- VD Ambient temperature, Ta - C 30 CH sep. -- Ta VD=13V RL=8 Full time, tr - nsec 10 Full time, tr - nsec 10 12 14 16 18 20 22 20 20 10 0 8 0 -40 -20 0 20 40 60 80 100 120 Supply voltage, VD - V Ambient temperature, Ta - C No.A1997-12/15 LV4924VH 100 Efficiency -- Power 4 Pd - Power 80 3 Efficiency - % Pd - W 60 2 40 1 20 0 0 2 4 6 8 10 0 0 2 4 6 8 10 Power - W/ch 100 Efficiency -- Power 5 Pd - Power Power - W/ch 80 4 Efficiency - % 40 Pd - W 60 3 2 20 1 0 0 3 6 9 12 15 0 0 3 6 9 12 15 32 28 Power@THD+N+1% -- VD fIN=1kHz THD+N=1% 2CH-Drive AES17 RL=4 Power - W/ch 32 28 Power@THD+N+1% -- Ta VD=13V fIN=1kHz THD+N=1% 2CH-Drive AES17 Power - W/ch RL=6 Power@THD+N=1% - W 24 20 16 12 8 4 0 Power@THD+N=1% - W 24 20 16 12 8 4 RL=8 RL=4 RL=6 RL=8 8 10 12 14 16 18 20 22 0 -40 -20 0 20 40 60 80 100 120 44 40 36 Power@THD+N+10% -- VD fIN=1kHz THD+N=10% 2CH-Drive AES17 Supply voltage, VD - V Ambient temperature, Ta - C 44 40 Power@THD+N+10% -- Ta VD=13V fIN=1kHz THD+N=10% 2CH-Drive AES17 Power@THD+N=10% - W Power@THD+N=10% - W 32 28 24 20 16 12 8 4 0 8 10 12 14 16 RL=6 RL=4 RL=8 36 32 28 24 20 16 12 8 4 RL=4 RL=6 RL=8 18 20 22 0 -40 -20 0 20 40 60 80 100 120 Supply voltage, VD - V Ambient temperature, Ta - C No.A1997-13/15 LV4924VH 100 THD+N -- Frequency Total harmonic distortion, THD+N -- % VD=13V RL=8 PO=1W 2CH-Drive AES17 100 THD+N -- Ta VD=13V RL=8 fIN=1kHz PO=1W 2CH-Drive AES17 Total harmonic distortion, THD+N -- % 10 10 1 1 CH1 0.1 CH1 0.1 CH2 CH2 0.01 10 100 1000 10000 100000 0.01 -40 -20 0 20 40 60 80 100 120 Frequency - Hz 100 Ambient temperature, Ta - C 100 THD+N -- Frequency Total harmonic distortion, THD+N -- % VD=16V RL=8 PO=1W 2CH-Drive AES17 THD+N -- Ta VD=16V RL=8 fIN=1kHz PO=1W 2CH-Drive AES17 Total harmonic distortion, THD+N -- % 10 10 1 1 CH1 0.1 CH1 0.1 CH2 CH2 0.01 10 100 1000 10000 100000 0.01 -40 -20 0 20 40 60 80 100 120 Frequency - Hz 100 THD+N -- Power Total harmonic distortion, THD+N -- % VD=13V RL=8 2CH-Drive AES17 Ambient temperature, Ta - C 100 THD+N -- Power Total harmonic distortion, THD+N -- % VD=16V RL=8 2CH-Drive AES17 10 10 1 1 fIN=100Hz fIN=1kHz 0.1 fIN=100Hz fIN=1kHz 0.1 fIN=6.67kHz 0.01 0.0001 fIN=6.67kHz 0.01 0.0001 0.001 0.01 0.1 1 10 100 0.001 0.01 0.1 1 10 100 Power - W Power - W No.A1997-14/15 LV4924VH SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein. SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO Semiconductor Co.,Ltd. products described or contained herein are controlled under any of applicable local export control laws and regulations, such products may require the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written consent of SANYO Semiconductor Co.,Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO Semiconductor Co.,Ltd. product that you intend to use. Upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third party. SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's intellctual property rights which has resulted from the use of the technical information and products mentioned above. This catalog provides information as of November, 2011. Specifications and information herein are subject to change without notice. PS No.A1997-15/15