LV5052V

Ordering number : ENA1394 Bi-CMOS IC LV5052V Overview Built-in 2-channels DC/DC Converter Controller The LV5052V is a high efficiency DC/DC converter controller with 2-channels IC adopting a synchronous rectifying system. Incorporating numerous functions on a single chip with easy external setting, it can be used for a wide variety of applications. This device is optimal for use in internal power supply systems which are used in electronic devices, LCD-TVs, DVD recorders, etc. Functions • Step-down DC/DC converter controller with 2-channel • Built-in input UVLO circuit, Over current detection function, soft-start/soft-stop function and Start-up delay circuit • Built-in output voltage monitor function (Under voltage protection with power good and timer latch) • 180 degree interleaving operation during 1-phase to 2-phase • Synchronized operation is possible (Master-slave operation is possible when using plural devices) Specifications Absolute Maximum Ratings at Ta = 25°C Parameter Supply voltage Output peak current Allowable power dissipation Operating temperature Storage temperature VIN IOUT Pd max Topr Tstg Mounted on a specified board *1 Symbol Conditions Ratings 18 ±1.0 1.0 -20 to 85 -55 to +150 Unit V A W °C °C *1: Specified board: 114.3mm × 76.1mm ×1.6mm, glass epoxy board. Continued on next page. Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment (home appliances, AV equipment, communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee thereof. If you should intend to use our products for applications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our customer shall be solely responsible for the use. Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer' s products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer' s products or equipment. 12809 MS 20081209-S00004 No.A1394-1/9 LV5052V Continued from preceding page. Parameter Allowable terminal voltage *2 1 2 3 4 5 HDRV1,2, CBOOT1,2 Between HDRV1,2, CBOOT1,2 and SW1,2 VIN, ILIM1,2, RSNS1,2, SW1,2, PGOOD1,2 VLIN5, VDD, LDRV1,2 COMP1,2, FB1,2, SS1,2, UV_DELAY,TD1,2, CT, CLKO 25 6.5 18 6.5 VLIN5+0.3 V V V V V Symbol Conditions Ratings Unit *2: The Allowable Terminal Voltage, the SGND+PGND pin becomes a standard except for No.2 of the allowable terminal voltage about No.2 of the allowable terminal voltage, the SW pin becomes a standard. Recommended Operating Condition at Ta = 25°C Parameter Supply voltage Symbol VIN Conditions Ratings 9.4 to 16 Unit V Electrical Characteristics at Ta = 25°C, VIN=12V, Unless especially specified. Parameter System Reference voltage for comparing Supply current 1 Supply current 2 5V supply voltage Over-current sense comparator offset Over-current sense reference current source Soft start source current Soft start sink current Soft start clamp voltage UV_DELAY source current UV_DELAY sink current UV_DELAY threshold voltage UV_DELAY operating voltage VUVP detection hysteresis Over-voltage detection Output discharge transistor ON resistance Output part CBOOT leakage current HDRVx LDRVx source current HDRVx LDRVx sink current HDRVx lower ON resistance LDRVx lower ON resistance Synchronous ON prevention dead time 1 Synchronous ON prevention dead time 2 Oscillator Oscillation frequency Oscillation frequency range Maximum ON duty Minimum ON time Upper-side voltage saw- tooth wave Lower-side voltage saw-tooth wave ON time difference between CH1 to CH2 fosc foscop DON max TON min VsawH VsawL ∆Tdead CT=130pF CT=130pF fOSC=300kHz fOSC=300kHz CT=130pF 280 250 82 100 2.75 1 5 3.2 1.2 330 380 1100 kHz kHz % ns V V % ICBOOT ISCDRV ISKDRV RHDRV RLDRV Tdead1 Tdead2 IOUT = 500mA IOUT = 500mA LDRV OFF→HDRV ON HDRV OFF→LDRV ON VCBOOT = VSW + 6.5V 1.0 1.0 1.5 1.5 50 120 2.5 2.5 10 µA A A Ω Ω ns ns ISSSC ISSSK VSST0 ISCUVD ISKUVD VUVD VUVP ∆VUVP VOVP VSWON 100% at VFBx = VREF 113 5 100% at VFBx = VREF UV_DELAY = 2V UV_DELAY = 2V TD = 5V TD = 0V -1.8 0.2 1.2 -4.3 0.2 1.5 77 -3.5 1.0 1.6 -8.6 1.0 2.4 82 4 118 10 123 20 3.5 87 2.0 -17.2 -7.0 µA mA V µA mA V % % % Ω VREF ICC1 ICC2 VLIN5 VCLOS ICL VIN = 10 to 14V TD1,2 = 5V (Except for the Ciss charge) TD1,2 = 0V IVIN5 = 0 to 10mA 0.838 4 0.8 5.10 -5 75 85 0.840 6 1.4 5.30 0.848 8 2.0 5.50 +5 95 V mA mA V mV µA Symbol Conditions min Ratings typ max Unit Continued on next page. No.A1394-2/9 LV5052V Continued from preceding page. Parameter Error Amplifier Error amplifier input current COMP pin source current COMP pin sink current Error amplifier gm Current detection amplifier gain Logic output Power Good low level source current Power Good high level leakage current TP pin threshold voltage TP pin high impedance voltage TD pin charge source current TD pin discharge sink current CLKO high level voltage CLKO low level voltage Protection function VIN UVLO Release voltage UVLO Hysteresis VUVLO ∆VUVLO 3.5 4.1 0.4 4.3 mA µA IpwrgdL IpwrgdH VONTD VTDH ITDSC ITDSK VCLKOH VCLKOL ICLKO = 1mA ICLKO = 1mA VPGOOD = 0.4V VPGOOD = 12V When the voltage of the TD pin rises When VIN and VLIN5 pins are set to open 1.5 4.5 -1.8 0.2 0.7V5LIN 0.3V5LIN 2.6 5.2 -3.5 1.0 0.5 1.0 10 3.5 5.5 -7.0 mA µA V V µA mA V V IFB ICOMPSC ICOMPSK gm GISNS 18 500 5 -200 -100 -100 100 700 6.4 900 7.8 200 -18 nA µA µA umho Symbol Conditions min Ratings typ max Unit No.A1394-3/9 LV5052V Package Dimensions unit : mm (typ) 3191B 1200 Pd max - Ta Specified board: 114.3×76.1×1.6mm3 glass epoxy board. 9.75 30 16 Allowable power dissipation, Pd max -- mW 1000 950 800 5.6 7.6 600 494 400 1 0.65 (0.33) 0.22 15 0.15 0.5 200 (1.3) 1.5max 0 -20 0 20 40 60 80 85 100 Ambient temperature, Ta -- °C 0.1 SANYO : SSOP30(275mil) Pin Assignment PGND SGND PGOOD2 CBOOT2 COMP2 HDRV2 RSNS2 LDRV2 CLKO 16 15 Top view ILIM2 SW2 SS2 TD2 FB2 30 29 28 27 26 25 24 23 22 21 20 19 18 17 LV5052V 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PGOOD1 CBOOT1 SW1 ILIM1 CT UV_DELAY COMP1 FB1 TD1 VLIN5 VDD HDRV1 RSNS1 LDRV1 SS1 VIN No.A1394-4/9 LV5052V Block Diagram VIN POR 9.0V /8.0V Current bias VLIN5 Internal Bias 4.5V /4.0V ILIM Comp Typ 85µA 5V REG (always ON) Input Power Supply BG BG reference IREF Voltage and current generator VIN Vref VLIN5 5.3V Vref 0.84V COMP1 CH1 output ILIM1 SENSE Amp Error Amp 0.82Vref 1.18Vref 3.5µA SD UV1 OV1 Vref 1.6V SS1EN D Corrective ramp PWM comp PWM logic SKIP control VIN RSNS1 FB1 Shifter & latch RQ SQ CBOOT1 HDRV1 SW1 CH1 output SS1 SD Shoot through protection sequencer VDD LDRV1 0 deg 3.5µA Active discharge Rdson = 15Ω CONT1 2.6V ILIM Comp Typ 85µA TD1 POR COMP2 CH2 output ILIM2 SENSE Amp Error Amp 0.82Vref 1.18Vref 3.5µA SD UV2 OV2 Vref 1.6V SS2EN D Corrective ramp PWM comp PWM logic SKIP control VIN RSNS2 FB2 Shifter & latch RQ SQ CBOOT2 HDRV2 SW2 CH2 output SS2 SD Shoot through protection sequencer 180 deg 3.5µA Active discharge Rdson = 15Ω CONT2 2.6V CONT1 CONT2 POR OV1 9µA UV1 UV2 OV2 LDRV2 PGND TD2 POR 1µs delay 0V RQ SQ 0 180 deg deg OSC 300kHz SS1EN D SS2EN D 2.6V UV timeout PGOOD1 PGOOD2 UV_DELAY CT CLKO 5V 0V SGND Sync. pulse out No.A1394-5/9 LV5052V Pin Functions Pin No. 1 2 Pin name VDD LDRV Description Power supply pin for the gate drive of an external lower-side MOS-FET. This pin is connected to the VLIN5 pin through a filter. The gate drive pin of an external lower-side MOS-FET of channel 1. This pin has the signal input part for prevention of short-through of both the upper and lower MOS-FETs. When the voltage of this pin becomes less than 1V, the HDRV pin is turned on. 3 4 HDRV1 SW1 The gate drive pin for an external upper side MOS-FET of channel 1. This pin is connected with the switching node of channel 1. A source of an external upper side MOSFET and a drain of an external lower side MOS-FET are connected with this pin. This pin becomes the return current path of the HDRV pin. This pin is connected with a transistor drain of the discharge MOS-FET for SOFT STOP in the IC (typical 30Ω). Also, this pin has the signal output part for the short through prevention of both the upper and lower MOS-FETs. When this terminal voltage becomes 1V or less for PGND, the LDRV pin is turned on. 5 CBOOT1 The bootstrap capacity connection pin of channel 1. The gate drive power of upper MOSFET is provided by this pin. This pin is connected to the VDD pin through a diode and is connected to the SW pin through the bootstrap capacity. 6 VLIN5 The output pin of an internal regulator of 5V. the current is provided by the VIN pin. Also, power supply of the control circuit in the IC is provided by this pin. Connect an output capacitor of 4.7µF between this pin and SGND. A regulator of 5V operates, even if the IC is in the standby state. This pin is monitored by an UVLO function and the IC starts by the voltage of 4.5V or more (the IC is off by the voltage of 4.0V or less.) 7 COMP1 The phase compensation pin of channel 1. The output of an internal transformer conductance amplifier is connected. Connect an external phase compensation circuit between this pin and SGND. 8 FB1 Feed back input pin of channel 1. The minus terminal (-) of the trans conductance amplifier is connected. The voltage generated when the output voltage was divided by a resistor is input into this pin. The converter operates so that this pin becomes an internal reference voltage (VREF=0.8V). Also, this pin is monitored by the comparators UVP and OVP. When the voltage of this pin becomes less than 82% of the set voltage, the PGOOD pin is low level. A timer of the UV_DELAY function operates. Also, when the voltage of this pin becomes more than 117% of the set voltage, the IC latches off. 9 RSNS1 Channel 1 side input pin of the over current detection comparator / the current detection amplifier. To detect resistance, this pin is connected to the under side of a resistor for the current detection between the VIN pin and the DRAIN of the upper MOS-FET. Also, to use the ON resistance of MOS-FET for the current detection, connect this pin to the SOURCE of the upper MOS-FET. To prevent the common impedance of main current to the detection-voltage, this pin is connected by independent wiring. 10 ILIM The pin to set the trip point for over current detection of channel 1. Since the SINK current source of 85µA (ILIM) is connected in the IC, the over-current detection voltage (ILIM × RLIM) is generated by connecting a resistor RLIM between this pin and the VIN pin. The over-current is detected by comparing the voltage between the VIN pin and the ILIM pin to the current detection resistance RSNS or both end voltage of the upper MOSFET. 11 TD Start-up delay pin of channel 1. The time until the IC starts after releasing POR is set by connecting a capacitor between this pin and SGND. After releasing POR, an external capacitor is charged up by the constant current source of 3.5µA in the IC. When this terminal voltage becomes 2.6V or more, The IC starts. Also, when this terminal voltage becomes 2.6V or less, The IC becomes the standby state. If external capacitor is not connected, the IC instantly starts after releasing POR. 12 SS1 The pin to connect a capacitor for soft start of channel 1. After releasing POR, when the voltage of the TD pin becomes 2.6V or more, the SS1 pin is charged by an internal constant current source of 3.5µA. Since this pin is connected to the positive (+) input of the transformer conductance amplifier, the ramp-up wave form of the SS pin becomes the ramp-up wave form of the output. During POR operations and after the UV_DELAY time-out, the SS1 pin is discharged 13 PGOOD The power good pin of channel 1. The open drain MOS-FET of the withstand of 28V is connected in the IC. When the output voltage of channel 1 is less than -13% for the setup voltage, the low level is output. This pin has hysteresis of about (VREF × 4.0%). 14 UV_DELAY Common UVP DELAY pin to channel 1 and channel 2. By connecting a capacitor between this pin and SGND, the time until the IC latches off after detecting the UVP state can be set. Also, after channel 1 or channel 2 terminated the soft-start function, when the output voltage becomes 82% or less for the setup voltage, an external capacitor is charged by the constant current source of 8.6µA in the IC. When this terminal voltage becomes 2.6V or more, the IC is latched off. If an external capacitor is not connected, the IC is instantly latched off after detecting the UVP state. Also, when this pin is shorted to GND, the UV_DELAY function is not operated. Continued on next page. No.A1394-6/9 LV5052V Continued from preceding page. Pin No. 15 Pin name VIN CLKO Power supply pin of the IC. This pin is observed by the UVLO function and IC starts by 9.0V or more. (After starts, stop by 8.0V or less. ) 16 The clock output pin. The clock that synchronized to the oscillation waveform of the CT pin is output. To synchronize two or more LV5052Vs, the CLKO pin of the device that becomes a master is connected to the CT pin of the device that becomes a slave. When two or more the devices are synchronized and the start-up timing is changed by using the TD pin between each device, the earliest start-up device is determined as the master. 17 CT The pin to connect an external capacitor for the oscillator. Connect a capacitor between this pin and SGND. When a capacitor of 130pF is connected between this pin and GND, the oscillation frequency can be set up by 330kHz. Also, this pin is applied by an external clock signal. The PWM operation is performed by the frequency of applied clock signal. When an external clock signal is applied, the rectangular wave of 0V in low level and from 0V / 3.3V to 5V in high level is applied. The rectangular wave source needs the fan-out of 1mA or more. 18 19 20 21 22 23 24 25 PGOOD2 SS2 TD2 ILIM2 RSNS2 FB2 COMP2 SGND The power good pin of channel 2. The pin to connect a capacitor for soft start of channel 2. Start-up delay pin of channel 2. The pin to set the trip point for over current detection of channel 2. Channel 2 side input pin of the over current detection comparator / the current detection amplifier. Feed back input pin of channel 2. The phase compensation pin of channel 2. The system ground of the IC. The reference voltage is generated based on this pin. This pin is connected to the power supply system ground. 26 27 28 29 30 CBOOT2 SW2 HDRV2 LDRV2 PGND The bootstrap capacity connection pin of channel 2. This pin is connected with the switching node of channel 2. The gate drive pin for an external upper side MOS-FET of channel 2. The gate drive pin of an external lower-side MOS-FET of channel 2. Power ground pin. This pin becomes the return current path of the LDRV pin. Description No.A1394-7/9 LV5052V Start-up Sequence Each signal control timing at power supply ON is as below. 9V typ VIN=12V UVLO release * 4.5V typ VLIN5=5V VIN VLIN5 2.4V typ TD=5V TD SS=1.6V 0.8V VOUT=Vout × 100% SS VOUT Vout × 82% PGOOD * Starts charging the TD at the trigger point of either VIN > 9V(typ) or VLIN5 > 4.5V(typ), whichever is later. Protection Operate Sequence (1) Latch-off release by UVLO The signal control timing diagram for resetting the latch-off condition using UVLO is shown below. VIN=12V VIN 9V typ 8V typ Restart VLIN5=5V VLIN5 TD discharge start TD=5V 2.4V typ SS=1.6V TD SS Vout × 118% Vout × 82% OVP 0.8V VOUT=Vout × 100% Vout × 82% VOUT PGOOD (2) Latch off release by TD The signal control timing diagram for resetting the latch-off condition using UVLO is shown below. VIN=12V VIN VLIN5=5V VLIN5 TD discharge start TD=5V 2.4V typ SS=1.6V TD SS Vout × 118% Vout × 82% OVP 0.8V VOUT=Vout × 100% Vout × 82% VOUT PGOOD No.A1394-8/9 LV5052V Synchronized operation A recommended circuit for synchronizing the LV5052V is shown below. Master VIN (typ 12V) VIN CLKO 10kΩ Slave VIN CT CT 130pF 10kΩ VIN CT SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein. SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all semiconductor products fail or malfunction with some probability. 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SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's intellctual property rights which has resulted from the use of the technical information and products mentioned above. This catalog provides information as of January, 2009. Specifications and information herein are subject to change without notice. PS No.A1394-9/9