LV5230LG_10

Ordering number : ENA1359A LV5230LG Overview Bi-CMOS IC 7ch×17ch LED Driver The LV5230LG is a dot-matrix LED driver IC for cell phones. Features • 7×17 dot-matrix LED driver (5×15 dot-matrix supported) • Each dot can be set for display over the serial bus. Functions • LED driver Column (anode) driving P-channel driver × 17 channels Row (cathode ) driving N-channel driver × 7 channels LED current per dot : 25mA maximum Two flames of 7×17 (5×15) patterns can be set. 7 grayscale level adjustment on a dot basis (PWM duty factor switching) Reverse display Horizontal scroll (1 frame/2 frames) Continuous/single scroll selectable Vertical scroll (1 frame/2 frames) Continuous/single scroll selectable Automatic flashing can be specified per each dot Interupt output at the end of scroll Ring tone synchronization function • LED driving open drain output × 2 Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment (home appliances, AV equipment, communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee thereof. If you should intend to use our products for applications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our customer shall be solely responsible for the use. Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer' s products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer' s products or equipment. O0610 SY/10709 MS PC 20081114-S00001 No.A1359-1/27 LV5230LG Specifications Maximum Ratings at Ta = 25°C Parameter Maximum supply voltage Symbol VCC max1 VCC max2 Allowable power dissipation Operating temperature Storage temperature Pd max Topr Tstg SVCC, VDD LEDVDD Mounted on a board * Conditions Ratings 5.5 6 1.2 -30 to +85 -40 to +125 Unit V V W °C °C ∗ Designated board : 40mm×50mm×0.8mm, glass epoxy 4-layter board (2S2P) Operating Conditions at Ta = 25°C Parameter Supply voltage 1 Supply voltage 2 Supply voltage 3 Symbol VBAT VDD VLEDVDD SVCC VDD LEDVDD Conditions Ratings 3 to 4.5 1.65 to 3 2.7 to 5.5 Unit V V V * Power application sequence : 1. VBAT 2. VDD VBAT > VDD, No restriction on VLEDVDD. * Same level of voltage LEDVCC must be applied to the 4 pins as VLEDVDD voltage. Electrical Characteristics, Analog Block Ta = 25°C, VBAT = 3.7V, VDD = 2.6V, LEDVDD = 3.7V, unless otherwise specified Parameter Symbol Conditions min Consumption current (SVCC+VDD+LEDVDD) Consumption current 1 Consumption current 2 Consumption current 3A Consumption current 3B LEDSW On resistance 1 On resistance 2 LED current 1 LED current 2 Leakage current 1 Leakage current 2 Leakage current 3 OSC Oscillator frequency Oscillator frequency RT Maximum. LED drive current setting LI1 RT external resistance : 27kΩ LED maximum drive current = 607.5/RT resistance Continued on next page. 20 22.5 25 mA F1 F1 When RT external resistance is 27kΩ, CT external capacitance is 120pF When RT external resistance is 160kΩ, CT external capacitance is 10pF 900 1000 1100 kHz 900 1000 1100 kHz Ron1 Ron2 ILED1 ILED2 IL1 IL2 IL3 ROW1 to 7 : IL = 425mA LEDO1, LED02 : IL = 20mA COL1 to COL17 : VO = LEDVDD-0.5V RT external resistance value : 27kΩ COL1 to COL17 : VO = LEDVDD-0.5V RT external resistance value : 160kΩ ROW1 to ROW : VO = 5V COL1 to COL17 : VO = 0V, LEDVDD = 5V LEDO1, LED02 : VO = 5V 2.8 3.8 4.8 1 1 1 mA μA μA μA 20 1 2 22.5 2 4 25 Ω Ω mA ICC1 ICC2 ICC3A ICC3B RESET : L RESET : H, serial default When STBY mode is released, RT external resistance value is 27kΩ When STBY mode is released, RT external resistance value is 160kΩ 1 2 mA 0 0.3 1.9 5 5 3 μA μA mA Ratings typ max Unit No.A1359-2/27 LV5230LG Continued from preceding page. Parameter Control Circuit Block H level 1 L level 1 H level 2 L level 2 H input current 3 L input current 3 H input current 4 L input current 4 H output level 1 L output level 1 VINH1 VINL1 VINH2 VINL2 IHIN3 ILIN3 IHIN4 ILIN4 VH1 VL1 Input H level, SDA, SCL Input L level, SDA, SCL Input H level, RESET, SCTL Input L level, RESET, SCTL Inflow-outflow current, when VBAT voltage is applied to RESET pin. Inflow-outflow current, when 0V is applied to RESET pin. Inflow-outflow current, when VBAT voltage is applied to SCTL pin. Inflow-outflow current, when 0V is applied to SCTL pin. INTO pin, H level, IO = 1mA INTO pin, L level, IO = 1mA VDD-0.3 0 VDD 0.3 V V -1 0 1 μA 15 47 75 μA -1 0 1 μA VDD×0.8 0 1.5 0 -1 0 0.3 1 VDD×0.2 V V V V μA Symbol Conditions min Ratings typ max Unit Package Dimensions unit : mm (typ) 3359 1.4 Pd max – Ta Specified board : 50 × 40 × 0.8mm3 4-layer glass epoxy (2S2P) board 0.55 5.0 0.45 0.45 Allowable power dissipation, Pd max – W 0.55 567 1.2 1.0 5.0 0.8 34 0.65 0.6 0.48 0.4 G F ED 0.35 0.0 NOM 0.8 CB A 0.65 1 2 0.2 0 – 30 – 20 0 20 40 60 80 100 Ambient temperature, Ta – °C SANYO : FLGA49J(5.0X5.0) Pin Assignment G 1 NC F COL16 E CT D C B A TEST 1 Top view SGND LEDGND ROW2 1 SDA ROW1 ROW3 2 LEDVDD COL17 SVCC RT 2 3 COL15 COL14 COL13 SCL VDD LEDGND ROW4 2 ROW5 LEDGND 3 3 4 LEDVDD COL12 COL11 RESET INTO 4 5 COL10 COL9 COL4 COL2 GPI ROW6 LEDGND 4 5 6 LEDVDD COL8 COL5 COL3 LEDO2 LEDO1 ROW7 6 7 NC G COL7 F COL6 LEDVDD COL1 LEDGND 5 E D C B NC A 7 No.A1359-3/27 NC NC NC SGND SVCC CT COUNTER shift register Block Diagram ROW1 ROW2 ROW3 ROW4 ROW5 ROW6 ROW7 OSC LEDGND1 LEDGND2 RT RESET IREF LEDGND3 LEDGND4 COL1 COL2 COL3 COL4 COL5 COL6 COL7 COL8 COL9 COL10 COL11 COL12 COL13 COL14 COL15 COL16 COL17 LEDVDD PWM LEDGND5 TEST LEDO1 LEDO2 VBAT LV5230LG GPI (SCTL) I2C bus control INTO SDA SCL VDD I/F level shift No.A1359-4/27 LV5230LG Dot Matrix LED 7 × 17 COL10 COL12 COL13 COL14 COL15 COL16 COL17 No.A1359-5/27 ROW1 ROW2 ROW3 ROW4 ROW5 ROW6 ROW7 2ms ROW1 ROW2 ROW3 ROW4 ROW5 ROW6 ROW7 Dynamic Display Dot Matrix LED 5 × 15 COL10 COL12 COL13 COL14 COL15 COL11 COL1 COL2 COL3 COL4 COL5 COL6 COL7 COL8 COL9 ROW1 ROW2 ROW3 ROW4 ROW5 2ms ROW1 ROW2 ROW3 ROW4 ROW5 Dynamic Display COL11 COL1 COL2 COL3 COL4 COL5 COL6 COL7 COL8 COL9 LV5230LG Pin Functions Pin No. A1 Pin name TEST Test signal input pin. Be sure to connect the pin to GND. Pin Description Equivalent Circuit SVCC A1 pin A2 RT Reference current setting resistor connection pin. By connecting the external resistor between this pin and GND, the reference current is generated. The pin voltage is about 0.61V. Change of this current value enables change of the oscillation frequency and LED driver current value (COL1 to COL17 only). SVCC A2 pin A3 A6 B1 B2 B4 B5 C2 ROW4 ROW7 ROW2 ROW3 ROW5 ROW6 ROW1 N-channel driver output pins 1 to 7 for row (cathode) drive. Must be connected to GND when not to be used. A3, A6, B1, B2, B4, B5, C2 pin A4 A5 A7 G1 G7 B3 B6 C6 LEDGND3 LEDGND4 NC ROW SW GND. ROW SW GND. No connection. LEDGND2 LEDO1 LEDO2 ROW SW GND. Open drain output pins for LED drive. Must be connected to GND when not to be used. B6, C6 pin B7 C1 C3 C4 LEDGND5 LEDGND1 VDD INTO GND pin dedicated for LEDO1 and LEDO2. ROW SW GND. Power supply for serial I/F. Interrupt signal output pin. VDD SVCC C4 pin Continued on next page. No.A1359-6/27 LV5230LG Continued from preceding page. Pin No. C5 Pin name GPI Pin Description Ringing tone synchronization signal input pin. Must be connected to GND when not to be used. Equivalent Circuit SVBAT C5 pin C7 D5 D6 E3 E4 E5 E6 E7 F1 F2 F3 F4 F5 F6 F7 G3 G5 D7 G2 G4 G6 D1 D2 COL1 COL2 COL3 COL13 COL11 COL4 COL5 COL6 COL16 COL17 COL14 COL12 COL9 COL8 COL7 COL15 COL10 LEDVDD P-channel driver output pins 1 to 17 for column (anode) drive. Must be connected to GND when not to be used. LEDVDD C7, D5, D6, E3, E4, E5, E6, E7, F1, F2, F3, F4, F5, F6, F7, G3, G5 pin Dot matrix LED drive voltage supply pins. SGND SDA Analog circuit GND pin. Serial data signal input pin. VDD D2 pin D3 SCL Serial clock signal input pin. VDD D3 pin Continued on next page. No.A1359-7/27 LV5230LG Continued from preceding page. Pin No. D4 Pin name RESET Reset signal input pin. Reset state when low. Pin Description Equivalent Circuit SVCC D4 pin E1 CT Oscillator frequency setting capacitor connection pin. The oscillation frequency can be adjusted by changing the value of capacitor at CT pin. SVCC E1 pin E2 SVCC Analog circuit power supply. No.A1359-8/27 LV5230LG Serial Bus Communication Specifications I2C serial transfer timing conditions twH SCL twL th2 SDA th1 ts2 ts1 ts3 th1 tbuf Start condition ton tof Resend start condition Stop condition Input waveform condition Standard mode Parameter SCL clock frequency Data set up time symbol fscl ts1 ts2 ts3 Data hold time th1 th2 Pulse width twL twH Input waveform conditions ton tof Bus free time tbuf SCL clock frequency SCL setup time relative to the fall of SDA SDA setup time relative to the rise of SCL SCL setup time relative to the rise of SDA SCL data hold time relative to the fall of SDA SDA hold time relative to the fall of SCL SCL pulse width for the L period SCL pulse width for the H period SCL and SDA (input) rise time SCL and SDA (input) fall time Time between STOP and START conditions 4.7 Conditions min 0 4.7 250 4.0 4.0 0 4.7 4.0 1000 300 typ max 100 unit kHz μs ns μs μs μs μs μs ns ns μs High-speed mode Parameter SCL clock frequency Data setup time Symbol fscl ts1 ts2 ts3 Data hold time th1 th2 Pulse width twL twH Input waveform conditions ton tof Bus free time tbuf SCL clock frequency SCL setup time relative to the fall of SDA SDA setup time relative to the rise of SCL SCL setup time relative to the rise of SDA SCL data hold time relative to the fall of SDA SDA hold time relative to the fall of SCL SCL pulse width for the L period SCL pulse width for the H period SCL and SDA (input) rise time SCL and SDA (input) fall time Time between STOP and START conditions 1.3 Conditions min 0 0.6 100 0.6 0.6 0 1.3 0.6 300 300 typ max 400 unit kHz μs ns μs μs μs μs μs ns ns μs No.A1359-9/27 LV5230LG I2C bus transmission method Start and stop conditions In the I2C bus, SDA must basically be kept in the constant state while SCL is “H” as shown below during data transfer. SCL SDA ts2 th2 When data transfer is not made, both SCL and SDA are in the “H” state. When SCL = SDA = “H”, change of SDA from “H” to “L” enables the start conditions to start access. When SCL is “H”, change of SDA from “L” to “H” enables the stop conditions to stop access. Start condition Stop condition SCL SDA th1 ts3 No.A1359-10/27 LV5230LG Data transfer and acknowledgement response After establishment of start conditions, data transfer is made by one byte (8 bits). Data transfer enables continuous transfer of any number of bytes. Each time the 8-bit data is transferred, the ACK signal is sent from the receive side to the send side. The ACK signal is issued when SDA on the send side is released and SDA on the receive side is set “L” immediately after fall of the clock pulse at the SCL eighth bit of data transfer to “L”. When the next 1-byte transfer is left in the receive state after transmission of the ACK signal from the receive side, the receive side releases SDA at fall of the SCL ninth clock. In the I2C bus, there is no CE signal. Instead, 7-bit slave address is assigned to each device and the first byte of transfer is assigned to the command (R/W) representing the 7-bit slave address and subsequent transfer direction. The 7-bit address is transferred sequentially from MSB and if the eighth bit is “L”, the second byte is WRITE mode and if “H”, the second byte is READ mode. In the READ mode, the ACK signal issued immediately before sending the stop condition must be 1. In LV5230, the slave address is specified as (1110111). Write mode Start M S B Slave address L S B W A C K M S B Register address L S B A C K M S B Data L S B A C K Stop SCL SDA 111 011 1 000 000 10 000 100 01 Read mode Start M S B Slave address L S B W A C K M S B Data L S B A C K M S B Data L S B A C K Stop SCL SDA 111 011 1 1 STATUS 0 STATUS 1 No.A1359-11/27 LV5230LG Serial modes setting address : 00h CTRL1 00h CTRL1 Register name R/W Default D7 STBY W 0 D6 D5 MXMODE W 0 D4 MSWEN W 0 D3 D2 DFCLR W 0 D1 FADECLR W 0 D0 SCRLCLR W 0 D0 : SCRLCLR Scroll interrupt signal clear 0 : Scroll interrupt signal stays active. 1 : Scroll interrupt signal cleared. * Automatically updated to 0 after being set to 1. D1 : FADECLR Fade interrupt signal clear 0 : Fade interrupt signal stays active. 1 : Fade interrupt signal cleared. * Automatically updated to 0 after being set to 1. D2 : DFCLR Pallete fade interrupt signal clear 0 : Pallete fade interrupt signal stays active. 1 : Pallete fade interrupt signal cleared. * Automatically updated to 0 after being set to 1. D4 : MSWEN Ringing tone synchronization enable 0 : Ringing tone synchronization enabled. * GPI = L : All LEDs turned off, GPI = H : Normal operation 1 : Ringing tone synchronization disabled. D5 : MXMODE LED matrix mode switchingr 0 : 7 × 17 LED matrix 1 : 5 × 15 LED matrix D7: STBY Standby mode 0 : Standby 1 : Operation No.A1359-12/27 LV5230LG address : 01h CTRL2 01h CTRL2 Register name R/W Default D7 LEDOFF W 0 D6 D5 LED2 W 0 D4 LED1 W 0 D3 D2 ROTHEN W 0 D1 ROTVEN W 0 D0 PAGE W 0 D0 : PAGE Display page 0 : Frame 1 displayed 1 : Frame 2 displayed D1 : ROTVEN Vertical rotation 0 : Normal display 1 : Vertically rotated display D2 : ROTHEN Horizontal rotation 0 : Normal display 1 : Horizontally rotated display D4 : LED1 LED1 enable 0 : LED1 turned off 1 : LED1 turned on D5 : LED2 LED2 enable 0 : LED2 turned off 1 : LED2 turned on D7 : LEDOFF Screen display ON/OFF 0 : Normal operation 1 : All matrix LEDs turned off No.A1359-13/27 LV5230LG address : 02h DOTMODE 02h DOTMODE Register name R/W Default D7 DOTEN W 0 D6 DOTMODE W 0 D5 D4 D3 DOTSP [3] W 0 D2 DOTSP [2] W 0 D1 DOTSP [1] W 0 D0 DOTSP [0] W 0 D3-D0 : DOTSP Flashing/brightness inversion speed D3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 D2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 D1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 ON : 0.05s ON : 0.10s ON : 0.15s ON : 0.20s ON : 0.25s ON : 0.30s ON : 0.35s ON : 0.40s ON : 0.45s ON : 0.50s ON : 0.55s ON : 0.60s ON : 0.65s ON : 0.70s ON : 0.75s ON : 0.80s OFF : 0.05s OFF : 0.10s OFF : 0.15s OFF : 0.20s OFF : 0.25s OFF : 0.30s OFF : 0.35s OFF : 0.40s OFF : 0.45s OFF : 0.50s OFF : 0.55s OFF : 0.60s OFF : 0.65s OFF : 0.70s OFF : 0.75s OFF : 0.80s D6 : DOTMODE Flashing/brightness inversion display switching 0 : Flashing 1 : Brightness inversion D7 : DOTEN Flashing/brightness inversion display enable 0 : Disable 1 : Enable No.A1359-14/27 LV5230LG address : 03h AUTOPAGE 03h AUTOPAGE Register name R/W Default D7 PGEN W 0 D6 D5 D4 D3 PGSP [3] W 0 D2 PGSP [2] W 0 D1 PGSP [1] W 0 D0 PGSP [0] W 0 D3 top D0 : PGSP Page switching speed D3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 D2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 D1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Page1 : 0.05s Page1 : 0.10s Page1 : 0.15s Page1 : 0.20s Page1 : 0.25s Page1 : 0.30s Page1 : 0.35s Page1 : 0.40s Page1 : 0.45s Page1 : 0.50s Page1 : 0.55s Page1 : 0.60s Page1 : 0.65s Page1 : 0.70s Page1 : 0.75s Page1 : 0.80s Page2 : 0.05s Page2 : 0.10s Page2 : 0.15s Page2 : 0.20s Page2 : 0.25s Page2 : 0.30s Page2 : 0.35s Page2 : 0.40s Page2 : 0.45s Page2 : 0.50s Page2 : 0.55s Page2 : 0.60s Page2 : 0.65s Page2 : 0.70s Page2 : 0.75s Page2 : 0.80s D7 : PGEN Automatic page switching enable 0 : Disable 1 : Enable No.A1359-15/27 LV5230LG address : 04h SCCON1 04h SCCON1 Register name R/W Default D7 SCEN W 0 D6 SCDIR [1] W 0 D5 SCDIR [0] W 0 D4 SCMODE W 0 D3 SCSP [3] W 0 D2 SCSP [2] W 0 D1 SCSP [1] W 0 D0 SCSP [0] W 0 D3 to D0 : SCSP Scroll speed per dot D3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 D2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 D1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 50ms 100ms 150ms 200ms 250ms 300ms 350ms 400ms 450ms 500ms 550ms 600ms 650ms 700ms 750ms 800ms D4 : SCMODE Page mode when scrolling 0 : Scrolls and displays the current page repeatedly. 1 : Scrolls and displays the current and other pages alternately. D6 to D5 : SCDIR Scroll direction D6 0 0 1 1 D5 0 1 0 1 Right Left Up Down D7 : SCEN Scroll enable 0 : Disable 1 : Enable No.A1359-16/27 LV5230LG address : 05h SCCON2 05h SCCON2 Register name R/W Default D7 SCGO W 0 D6 D5 SCCNT [5] W 0 D4 SCCNT [4] W 0 D3 SCCNT [3] W 0 D2 SCCNT [2] W 0 D1 SCCNT [1] W 0 D0 SCCNT [0] W 0 D0 to D5 : SCCNT Scroll increment 17 × 7 mode When SCCON1.SCDIR = 0 or 1 : 1 to 34 When SCCON1.SCDIR = 2 or 3 : 1 to 14 15 × 5 mode When SCCON1.SCDIR = 0 or 1 : 1 to 30 When SCCON1.SCDIR = 2 or 3 : 1 to 10 * Scrolls one page when SCCNT = 0. D7 : SCGO Scroll start 0 : Standby 1 : Scroll start * The scrolled state is maintained until SCCON1 and SCEN are set low. No.A1359-17/27 LV5230LG address : 06h FADECON 06h FADECON Register name R/W Default D7 FADEEN W 0 D6 FADEGO W 0 D5 FADEIO W 0 D4 FADEMOD W 0 D3 FDSP [3] W 0 D2 FDSP [2] W 0 D1 FDSP [1] W 0 D0 FDSP [0] W 0 D3 to D0 : FDSP Fade speed per 1 grayscale level (It takes (following set value × 64) seconds to complete fading) D3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 D2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 D1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 2ms 4ms 6ms 8ms 10ms 12ms 14ms 16ms 18ms 20ms 22ms 24ms 26ms 28ms 30ms 32ms D4 : FADEMOD Single/continuous switching 0 : Single fade-in/fade-out operation 1 : Fade-in/fade-out operation repeated D5 : FADEIO Fade-in/fade-out switching 0 : Fade in 1 : Fade out D6 : FADEGO Fade-in/fade-out start 0 : Standby 1 : Fade-in/fade-out operation start D7 : FADEEN Fade-in/fade-out enable 0 : Disable 1 : Enable * The interrupt flag is set high after a fade operation has completed. Manual clearing is required. * All LEDs are turned off if FADEEN is set to 1 when FADEO is set to 0. If GO is set to 1 in that state, fade-in operation starts and LEDs are turned on. No.A1359-18/27 LV5230LG address : 07h ROWSW 07h ROWSW Register name R/W Default D7 ROWSWEN W 0 D6 ROWSW7 W 0 D5 ROWSW6 W 0 D4 ROWSW5 W 0 D3 ROWSW4 W 0 D2 ROWSW3 W 0 D1 ROWSW2 W 0 D0 ROWSW1 W 0 D0 : ROWSW1 Row 1 display ON/OFF 0 : ON 1 : OFF D1 : ROWSW2 Row 2 display ON/OFF 0 : ON 1 : OFF D2 : ROWSW3 Row 3 display ON/OFF 0 : ON 1 : OFF D3 : ROWSW4 Row 4 display ON/OFF 0 : ON 1 : OFF D4 : ROWSW5 Row 5 display ON/OFF 0 : ON 1 : OFF D5 : ROWSW6 Row 6 display ON/OFF 0 : ON 1 : OFF D6 : ROWSW7 Row 7 display ON/OFF 0 : ON 1 : OFF D7 : ROWSWEN Each row ON/OFF enable 0 : Disable 1 : Enable No.A1359-19/27 LV5230LG address : 08h COLSW1 08h COLSW1 Register name R/W Default D7 COLSWEN W 0 D6 D5 D4 D3 D2 D1 D0 COLSW17 W 0 D0 : COLSW17 Row 17 display ON/OFF 0 : ON 1 : OFF D7 : COLSWEN Column ON/OFF enable 0 : Disable 1 : Enable address : 09h COLSW2 09h COLSW2 Register name R/W Default D7 COLSW16 W 0 D6 COLSW15 W 0 D5 COLSW14 W 0 D4 COLSW13 W 0 D3 COLSW12 W 0 D2 COLSW11 W 0 D1 COLSW10 W 0 D0 COLSW9 W 0 D0 : COLSW9 Column 9 display ON/OFF 0 : ON 1 : OFF D1 : COLSW10 Column 10 display ON/OFF 0 : ON 1 : OFF D2 : COLSW11 Column 11 display ON/OFF 0 : ON 1 : OFF D3 : COLSW12 Column 12 display ON/OFF 0 : ON 1 : OFF D4 : COLSW13 Column 13 display ON/OFF 0 : ON 1 : OFF D5 : COLSW14 Column 14 display ON/OFF 0 : ON 1 : OFF D6 : COLSW15 Column 15 display ON/OFF 0 : ON 1 : OFF D7 : COLSW16 Column 16 display ON/OFF 0 : ON 1 : OFF No.A1359-20/27 LV5230LG address : 0Ah COLSW3 0Ah COLSW3 Register name R/W Default D7 COLSW8 W 0 D6 COLSW7 W 0 D5 COLSW6 W 0 D4 COLSW5 W 0 D3 COLSW4 W 0 D2 COLSW3 W 0 D1 COLSW2 W 0 D0 COLSW1 W 0 D0 : COLSW1 Column 1 display ON/OFF 0 : ON 1 : OFF D1 : COLSW2 Column 2 display ON/OFF 0 : ON 1 : OFF D2 : COLSW3 Column 3 display ON/OFF 0 : ON 1 : OFF D3 : COLSW4 Column 4 display ON/OFF 0 : ON 1 : OFF D4 : COLSW5 Column 5 display ON/OFF 0 : ON 1 : OFF D5 : COLSW6 Column 6 display ON/OFF 0 : ON 1 : OFF D6 : COLSW7 Column 7 display ON/OFF 0 : ON 1 : OFF D7 : COLSW8 Column 8 display ON/OFF 0 : ON 1 : OFF No.A1359-21/27 LV5230LG address : 0Bh DFCON1 0Bh DFCON1 Register name R/W Default D7 DFEN W 0 D6 DFGO W 0 D5 D4 D3 DFDIR W 0 D2 DFNUM [2] W 0 D1 DFNUM [1] W 0 D0 DFNUM [0] W 0 D2 to D0 : DFNUM Number of palette to be faded to 0 : Invalid 1 to 7 : Correspond to PWMDUTY1 to PWMDUTY7. D3 : DFDIR Fading direction 0 : Fade in 1 : Fade out D6 : DFGO Fade start 0 : Standby 1 : Start D7 : DFEN Fade enable 0 : Disable 1 : Enable * The interrupt flag is set high after a fade operation has completed. Manual clearing is required. address : 0Ch DFCON2 0Ch DFCON2 Register name R/W Default D7 D6 D5 D4 D3 DFSP [3] W 0 D2 DFSP [2] W 0 D1 DFSP [1] W 0 D0 DFSP [0] W 0 D3 to D0 : DFSP Fading speed per grayscale D3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 D2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 D1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 2ms 4ms 6ms 8ms 10ms 12ms 14ms 16ms 18ms 20ms 22ms 24ms 26ms 28ms 30ms 32ms No.A1359-22/27 LV5230LG address : 0Dh MAXDUTY 0Dh MAXDUTY Register name R/W Default D7 D6 D5 MXDTY [5] W 0 D4 MXDTY [4] W 0 D3 MXDTY [3] W 0 D2 MXDTY [2] W 0 D1 MXDTY [1] W 0 D0 MXDTY [0] W 0 D5 to D0 : MXDTY Maximum DUTY value n : 0 to 63 Maximum DUTY value (n/64) × 100[%] * 100[%] when n = 63. address : 10h PWMDUTY1 10h PWMDUTY1 Register name R/W Default D7 D6 D5 DUTY1 [5] W 0 D4 DUTY1 [4] W 0 D3 DUTY1 [3] W 0 D2 DUTY1 [2] W 0 D1 DUTY1 [1] W 0 D0 DUTY1 [0] W 0 D5 to D0 : DUTY1 DUTY value for brightness 1 setting n : 0 to 63 DUTY value ((n + 1)/64) × 100 [%] * 0 [%] when n = 0. address : 11h PWMDUTY2 11h PWMDUTY2 Register name R/W Default D7 D6 D5 DUTY2 [5] W 0 D4 DUTY2 [4] W 0 D3 DUTY2 [3] W 0 D2 DUTY2 [2] W 0 D1 DUTY2 [1] W 0 D0 DUTY2 [0] W 0 D5 to D0 : DUTY2 DUTY value for brightness 2 setting n : 0 to 63 DUTY value ((n + 1)/64) × 100 [%] * 0 [%] when n = 0. address : 12h PWMDUTY3 12h PWMDUTY3 Register name R/W Default D7 D6 D5 DUTY3 [5] W 0 D4 DUTY3 [4] W 0 D3 DUTY3 [3] W 0 D2 DUTY3 [2] W 0 D1 DUTY3 [1] W 0 D0 DUTY3 [0] W 0 D5 to D0 : DUTY3 DUTY value for brightness 3 setting n : 0 to 63 DUTY value ((n + 1)/64) × 100 [%] * 0 [%] when n = 0. address : 13h PWMDUTY4 13h PWMDUTY4 Register name R/W Default D7 D6 D5 DUTY4 [5] W 0 D4 DUTY4 [4] W 0 D3 DUTY4 [3] W 0 D2 DUTY4 [2] W 0 D1 DUTY4 [1] W 0 D0 DUTY4 [0] W 0 D5 to D0 : DUTY4 DUTY value for brightness 4 setting n : 0 to 63 DUTY value ((n + 1)/64) × 100 [%] * 0 [%] when n = 0. No.A1359-23/27 LV5230LG address : 14h PWMDUTY5 14h PWMDUTY5 Register name R/W Default D7 D6 D5 DUTY5 [5] W 0 D4 DUTY5 [4] W 0 D3 DUTY5 [3] W 0 D2 DUTY5 [2] W 0 D1 DUTY5 [1] W 0 D0 DUTY5 [0] W 0 D5 to D0 : DUTY5 DUTY factor value for brightness 5 setting n : 0 to 63 DUTY value ((n + 1)/64) × 100 [%] * 0 [%] when n = 0. address : 15h PWMDUTY6 15h PWMDUTY6 Register name R/W Default D7 D6 D5 DUTY6 [5] W 0 D4 DUTY6 [4] W 0 D3 DUTY6 [3] W 0 D2 DUTY6 [2] W 0 D1 DUTY6 [1] W 0 D0 DUTY6 [0] W 0 D5 to D0 : DUTY6 DUTY factor value for brightness 6 setting n : 0 to 63 DUTY value ((n + 1)/64) × 100 [%] * 0 [%] when n = 0. address : 16h PWMDUTY7 16h PWMDUTY7 Register name R/W Default D7 D6 D5 DUTY7 [5] W 0 D4 DUTY7 [4] W 0 D3 DUTY7 [3] W 0 D2 DUTY7 [2] W 0 D1 DUTY7 [1] W 0 D0 DUTY7 [0] W 0 D5 to D0 : DUTY7 DUTY factor value for brightness 7 setting n : 0 to 63 DUTY value ((n + 1)/64) × 100 [%] * 0 [%] when n = 0. No.A1359-24/27 LV5230LG address : 20h to 9Dh FRAMEDATA 20h to 9Dh FRAMEDATA Register name R/W Default D7 BRn W 0 D6 LMn [2] W 0 D5 LMn [1] W 0 D4 LMn [0] W 0 D3 BRm W 0 D2 LMm [2] W 0 D1 LMm [1] W 0 D0 LMm [0] W 0 D2 to D0 : LM11m Frame 1 : vertical 1st : horizontal (n + 1) th LED brightness D2 0 0 0 0 1 1 1 1 D1 0 0 1 1 0 0 1 1 D0 0 1 0 1 0 1 0 1 Off On at brightness set by PWMDUTY1 register On at brightness set by PWMDUTY2 register On at brightness set by PWMDUTY3 register On at brightness set by PWMDUTY4 register On at brightness set by PWMDUTY5 register On at brightness set by PWMDUTY6 register On at brightness set by PWMDUTY7 register D3 : BR11m Frame 1 : vertical 1: horizontal (n + 1) th LED flashing/brightness inversion enable 0 : Flashing/brightness inversion disabled 1 : Flashing/brightness inversion enabled D6 to D4 : LM11n Frame 1 : vertical 1 : horizontal (n) th LED brightness D2 0 0 0 0 1 1 1 1 D1 0 0 1 1 0 0 1 1 D0 0 1 0 1 0 1 0 1 Off On at brightness set by PWMDUTY1 register On at brightness set by PWMDUTY2 register On at brightness set by PWMDUTY3 register On at brightness set by PWMDUTY4 register On at brightness set by PWMDUTY5 register On at brightness set by PWMDUTY6 register On at brightness set by PWMDUTY7 register D7 : BR11n Frame 1 : vertical 1 : horizontal (n) th LED flashing/brightness inversion enable 0 : Flashing/brightness inversion disabled 1 : Flashing/brightness inversion enabled * These are used for each LED data. One register is loaded with two LEDs data. See the table on the following page for the storage address of each dot. No.A1359-25/27 LV5230LG Frame Data Register Tables xxH : higher-order 4 bits of register xx xxL : lower-order 4 bits of register xx 17 × 7 mode Frame 1 1 1 2 3 4 5 6 7 20H 29H 32H 3BH 44H 4DH 56H 2 20L 29L 32L 3BL 44L 4DL 56L 3 21H 2AH 33H 3CH 45H 4EH 57H 4 21L 2AL 33L 3CL 45L 4EL 57L 5 22H 2BH 34H 3DH 46H 4FH 58H 6 22L 2BL 34L 3DL 46L 4FL 58L 7 23H 2CH 35H 3EH 47H 50H 59H 8 23L 2CL 35L 3EL 47L 50L 59L 9 24H 2DH 36H 3FH 48H 51H 5AH 10 24L 2DL 36L 3FL 48L 51L 5AL 11 25H 2EH 37H 40H 49H 52H 5BH 12 25L 2EL 37L 40L 49L 52L 5BL 13 26H 2FH 38H 41H 4AH 53H 5CH 14 26L 2FL 38L 41L 4AL 53L 5CL 15 27H 30H 39H 42H 4BH 54H 5DH 16 27L 30L 39L 42L 4BL 54L 5DL 17 28H 31H 3AH 43H 4CH 55H 5EH Frame 2 1 1 2 3 4 5 6 7 5FH 68H 71H 7AH 83H 8CH 95H 2 5FL 68L 71L 7AL 83L 8CL 95L 3 60H 69H 72H 7BH 84H 8DH 96H 4 60L 69L 72L 7BL 84L 8DL 96L 5 61H 6AH 73H 7CH 85H 8EH 97H 6 61L 6AL 73L 7CL 85L 8EL 97L 7 62H 6BH 74H 7DH 86H 8FH 98H 8 62L 6BL 74L 7DL 86L 8FL 98L 9 63H 6CH 75H 7EH 87H 90H 99H 10 63L 6CL 75L 7EL 87L 90L 99L 11 64H 6DH 76H 7FH 88H 91H 9AH 12 64L 6DL 76L 7FL 88L 91L 9AL 13 65H 6EH 77H 80H 89H 92H 9BH 14 65L 6EL 77L 80L 89L 92L 9BL 15 66H 6FH 78H 81H 8AH 93H 9CH 16 66L 6FL 78L 81L 8AL 93L 9CL 17 67H 70H 79H 82H 8BH 94H 9DH 15 × 5 mode Frame 1 1 1 2 3 4 5 20H 29H 32H 3BH 44H 2 20L 29L 32L 3BL 44L 3 21H 2AH 33H 3CH 45H 4 21L 2AL 33L 3CL 45L 5 22H 2BH 34H 3DH 46H 6 22L 2BL 34L 3DL 46L 7 23H 2CH 35H 3EH 47H 8 23L 2CL 35L 3EL 47L 9 24H 2DH 36H 3FH 48H 10 24L 2DL 36L 3FL 48L 11 25H 2EH 37H 40H 49H 12 25L 2EL 37L 40L 49L 13 26H 2FH 38H 41H 4AH 14 26L 2FL 38L 41L 4AL 15 27H 30H 39H 42H 4BH Frame 2 1 1 2 3 4 5 4DH 56H 5FH 68H 71H 2 4DL 56L 5FL 68L 71L 3 4EH 57H 60H 69H 72H 4 4EL 57L 60L 69L 72L 5 4FH 58H 61H 6AH 73H 6 4FL 58L 61L 6AL 73L 7 50H 59H 62H 6BH 74H 8 50L 59L 62L 6BL 74L 9 51H 5AH 63H 6CH 75H 10 51L 5AL 63L 6CL 75L 11 52H 5BH 64H 6DH 76H 12 52L 5BL 64L 6DL 76L 13 53H 5CH 65H 6EH 77H 14 53L 5CL 65L 6EL 77L 15 54H 5DH 66H 6FH 78H No.A1359-26/27 LV5230LG address : FFh STATUS FFh STATUS Register name R/W Default X X X X X D7 D6 D5 D4 D3 D2 DFIF R D1 FEDIF R D0 SCRIF R D0 : SCRIF End of scroll interrupt occurrence flag 0 : No end of scroll interrupt has occurred. 1 : An end of scroll interrupt has occurred. * The flag needs to be cleared manually (CTRL1.SCRLCLR). D1 : FEDIF End of fade interrupt occurrence flag 0 : No end of fade interrupt has occurred. 1 : An end of fade interrupt has occurred. * The flag needs to be cleared manually (CTRL1.FADECLR). D2 : DFIF End of palette fade interrupt occurrence flag 0 : No end of palette fade interrupt has occurred. 1 : An end of palette fade interrupt has occurred. * The flag needs to be cleared manually (CTRL1.DFCLR). The OR of SCRIF, FEDIF and DFIF appear at the interrupt pin. * The addresses used here are all dummy and not used in actual communications. SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein. SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO Semiconductor Co.,Ltd. products described or contained herein are controlled under any of applicable local export control laws and regulations, such products may require the export license from the authorities concerned in accordance with the above law. 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SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's intellctual property rights which has resulted from the use of the technical information and products mentioned above. This catalog provides information as of October, 2010. Specifications and information herein are subject to change without notice. PS No.A1359-27/27