LV5232VH

Ordering number : ENA1628B Bi-CMOS IC LV5232VH Overview 16ch LED Driver The LV5232VH is a semiconductor integrated circuit that incorporates a serial input and serial or parallel output 16-stage shift register that features a CMOS structure based on Bi-CMOS process technology. The LV5232VH also contains an n-channel CMOS construction high-withstand-voltage, large-current drive 16-stage parallel output driver. The protection circuit of the output malfunction is built into. Features • Serial input and serial or parallel output • Enable input for output control • Serial output enables cascade connection • Low supply current (30μA typ. during standby ICC≤40μA) • Serial input/output levels compatible with typical CMOS devices • High-withstand-voltage LED driver with open drain output High withstand voltage (VDS < 42V) High-current drive (IO max = 100mA) • Operating temperature range Ta = -25 to 75°C • Output malfunction protection circuit Reset input pin VCC decrease voltage confirmation Specifications Maximum Ratings at Ta = 25°C Parameter Maximum supply voltage Output voltage Output current Allowable power dissipation Operating temperature Storage temperature Symbol VCC max VO max IO max Pd max Topr Tstg Ta ≤ 25°C * SVCC LEDO1 to LEDO16 off Conditions Ratings 6 42 100 1100 -25 to +75 -40 to +125 Unit V V mA mW °C °C * Specified board : 114.3mm × 76.1mm × 1.6mm, glass epoxy board. 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To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer' s products or equipment. 42011 SY 20110413-S00006/O0610 SY/D0209 SY No.A1628-1/9 LV5232VH Operating Conditions at Ta = 25°C Parameter Recommended supply voltage Operating supply voltage range Output applied voltage Output current Symbol VCC VCC op VO IO Duty = 45% to 55% SVCC SVCC Conditions Ratings 5.0 3.0 to 5.5 42 100 Unit V V V mA Electrical Characteristics at Ta = 25°C, VCC = 5.0V Parameter Quiescent current drain LEDO output on resistance OFF leak current Driver output malfunction prevention voltage Control circuit block H level 1 L level 1 H level 2 L level 2 VINH1 VINL1 VOUTH1 VOUTL1 Input H level Input L level SOUT IO = -1mA SOUT IO = 1mA VCC × 0.8 0 VCC -0.3 0 0.3 VCC × 0.2 V V V V Symbol ICC1 Ron Ileak Vt Conditions min LEDO driver off (standby) IO = 30mA VO = 42V 2.58 Ratings typ 30 5 0 2.70 10 2.82 max 40 μA Ω μA V Unit Package Dimensions unit : mm (typ) 3222A 15.0 28 15 5.6 7.6 1 0.8 (0.7) 2.0 0.3 14 0.2 SANYO : HSOP28(275mil) 1.5 Pd max -- Ta Specified board : 114.3 × 76.1 × 1.6mm3 glass epoxy Allowable power dissipation, Pd max -- W 1.0 0.1 2.7 (1.5) 1.7max 0.55 0.5 0 --25 0 25 50 75 0.5 100 Ambient temperature, Ta -- °C No.A1628-2/8 LV5232VH Pin Assignment 28 27 26 25 24 23 22 21 20 19 18 17 16 15 LEDO13 LEDO14 PGND4 LEDO10 LEDO12 Heat sink &GND Heat sink &GND LEDO11 LEDO15 LEDO16 LATCH LEDO9 PGND3 SDATAIN 13 PGND2 PGND1 LEDO7 LEDO6 SVCC 1 2 3 LEDO8 LEDO5 LEDO4 SOUT 4 5 6 7 8 9 10 11 12 14 Top view Pin Descriptions Pin No. 1 2 3 4 5 6 7 Heat sink 8 9 10 11 12 13 14 15 16 17 18 19 20 21 Heat sink 22 23 24 25 26 27 LEDO12 LEDO11 PGND3 PGND10 PGND9 LATCH O O I O O LEDO12 Latch output (LEDO12 of shift register) LEDO11 Latch output (LEDO11 of shift register) GND LEDO10 Latch output (LEDO10 of shift register) LEDO9 Latch output (LEDO9 of shift register) Latch input When the latch input is held low, the LED0 output status is retained. When a high-level is input, the LED0 outputs change when the status of the shift register changes. 28 XEN I Enable inputs (LEDO1 to LEDO16) When a high-level is input, all the LED0 outputs are turned off. When a low-level is input, the shift register data is output to LED0. LEDO4 LEDO3 PGND1 LEDO2 LEDO1 SDATAIN XRESET SGND SCK LEDO16 LEDO15 PGND4 LEDO14 LEDO13 O O I O O O O I I O O LEDO4 Latch output (LEDO4 of shift register) LEDO3 Latch output (LEDO3 of shift register) GND LEDO2 Latch output (LEDO2 of shift register) LEDO1 Latch output (LEDO1 of shift register) Serial Input Reset input (shift register and latch) GND Clock input (for shift register) LEDO16 Latch output (LEDO16 of shift register) LEDO15 Latch output (LEDO15 of shift register) GND LEDO14 Latch output (LEDO14 of shift register) LEDO13 Latch output (LEDO13 of shift register) Pin name SVCC SOUT LEDO8 LEDO7 PGND2 LEDO6 LEDO5 O O O O O I/O Power supply shift register output (final-stage shift register) LEDO8 Latch output (LEDO8 of shift register) LEDO7 Latch output (LEDO7 of shift register) GND LEDO6 Latch output (LEDO6 of shift register) LEDO5 Latch output (LEDO5 of shift register) Description XRESET LEDO3 LEDO2 LEDO1 SGND XEN SCK No.A1628-3/8 LV5232VH Block Diagram SCK SDATAIN LATCH XEN SVCC XRESET DQ CQ R DQ CQ R SVCC_protection LEDO1 LEDO2 DQ CQ R DQ CQ R LEDO3 DQ CQ R DQ CQ R LEDO4 LEDO13 LEDO14 DQ CQ R DQ CQ R LEDO15 DQ CQ R DQ CQ R LEDO16 DQ CQ R DQ CQ R DQ CQ R SOUT PGND1 PGND3 SGND PGND2 PGND4 Function The LV5232VH consists of 1) an 16-stage D-type flip-flop and 2) an 16-stage D-type flip-flop connected to the output of 1). When data is supplied to the serial data input (SDATAIN) and the clock pulse is supplied to the clock input (SCK), the serial data input signal is input to the internal shift register and the data already in the shift register shifted sequentially when the clock changes from low to high. The serial output (SOUT) is used to connect multiple LV5232VH to expand the number of bits and is connected to the SDATAIN of the next stage. (Cascade connection supported.) For parallel output, when the output control enable input (XEN) is low, the latch input (LATCH) changes from low to high and the clock pulse input changes from low to high, the serial data input signal is output to LED01, and the output is shifted sequentially. For parallel outputs (LED2 to LED16), the signals whose polarities inverted from those of the serial data input (SDATAIN) are output. When the EN input is high, outputs LED01 through LED01 all turn off. When the reset input is low, outputs LED01 through LED16 and SOUT outputs all turn off. The power must be turned on after checking that the reset input is low. To prevent the malfunction, the output load protection circuit is built into. The output of LEDO1 to LEDO16 is compulsorily turned off when becoming below the voltage with a constant there is VCC. No.A1628-4/8 LV5232VH Pin Functions Pin No. 13 16 Pin Name SDATAIN SCK Pin function Pull-down input Equivalent Circuit SVCC SGND 14 27 28 XRESET LATCH XEN Pull-up input SVCC SGND 2 SOUT SOUT output SVCC SOUT SGND 3 4 6 7 8 9 11 12 17 18 20 21 22 23 25 26 LEDO8 LEDO7 LEDO6 LEDO5 LEDO4 LEDO3 LEDO2 LEDO1 LEDO16 LEDO15 LEDO14 LEDO13 LEDO12 LEDO11 LEDO10 LEDO9 LEDO outputs LEDO1 to LEDO16 SVCC SGND PGND No.A1628-5/8 LV5232VH Timing conditions Parameter Clock frequency Clock pulse width Latch pulse width Data set up time Data hold time Clock latch time Input conditions 1 Input conditions 2 symbol fs1 twck twla ts1 th1 tla1 ton toff SCK and SDATAIN rise time SCL and SDATAIN fall time SCK Duty = 50% SCK LATCH SDATAIN setup time relative to the rise of SCK SDATAIN data hold time relative to the rise of SCK 50 50 25 25 100 100 100 Conditions min typ max 10 unit MHz ns ns ns ns ns ns ns twck SCK ts1 2.5V th1 ton SDATAIN 2.5V 2.5V twla tla1 LATCH 2.5V 2.5V toff 2.5V 10% 90% 90% 10% SOUT output timings Parameter SOUT delay time 1 SOUT delay time 2 symbol tdso1 tdso2 Conditions The time from a SCK falling edge to SOUT rising edge The time from a SCK falling edge to SOUT falling edge min typ max 50 50 unit MHz ns SCK 2.5V 2.5V tdso1 tdso2 2.5V SOUT 2.5V No.A1628-6/8 LV5232VH LEDO output timings Parameter LEDO delay time 1 symbol tdled1 Conditions The time from an XEN rising edge to LEDO rising edge CL = 30pF, IO = 100mA, VO = 42V LEDO delay time 2 tdled2 The time from an XEN falling edge to LEDO falling edge CL = 30pF, IO = 100mA, VO = 42V LEDO rise time trled LEDO rise time CL = 30pF, IO = 100mA, VO = 42V LEDO fall time tfled LEDO fall time CL = 30pF, IO = 100mA, VO = 42V LEDO delay time 3 tdled3 The time from a LATCH rising edge to LEDO falling edge CL = 30pF, IO = 100mA, VO = 42V 200 ns 200 ns 200 ns 100 ns min typ 100 max unit ns XEN 2.5V 2.5V tdled1 tdled2 90% LEDO 10% trled 90% 10% tfled tdled3 90% 2.5V LATCH Application Circuit Example max:42V 5V SVCC SDATAIN LEDO SVCC SDATAIN SCK LATCH XEN XRESET LEDO SOUT LEDO SOUT LEDO To SDATAIN sub CPU SCK LATCH XEN XRESET SGND PGND SGND PGND No.A1628-7/8 LV5232VH Allowable output current characteristics 300 IO -- LEDO Ta = 25° C 300 IO -- LEDO Ta = 25° C 250 250 50°C Output current, IO -- mA 200 50°C 75°C Output current, IO -- mA 200 75°C 150 150 100 100 50 50 0 0 duty cycle 100% 1 2 3 4 5 6 7 8 0 0 duty cycle 80% 1 2 3 4 5 6 7 8 Number of output ports, LEDO 300 Number of output ports, LEDO IO -- LEDO Ta = 25°C 50°C 75°C 250 Output current, IO -- mA 200 150 100 50 0 0 duty cycle 50% 1 2 3 4 5 6 7 8 Number of output ports, LEDO SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein. 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SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's intellctual property rights which has resulted from the use of the technical information and products mentioned above. This catalog provides information as of April, 2011. Specifications and information herein are subject to change without notice. PS No.A1628-8/8