LV5233H

Ordering number : EN*A1693A Bi-CMOS IC LV5233H Overview 24ch LED Driver The LV5233H is a semiconductor integrated circuit that incorporates a serial input and serial or parallel output 24-stage shift register that features a CMOS structure based on Bi-CMOS process technology. The LV5233H also contains an n-channel CMOS construction high-withstand-voltage, large-current drive 24-stage parallel output driver. The protection circuit of the output malfunction is built into. Features • Serial input and serial or parallel output • Enable input for output control • Serial output enables cascade connection • Low supply current (0.45mA typ. during standby ICC≤0.6mA) • Serial input/output levels compatible with typical CMOS devices • High-withstand-voltage LED driver with open drain output High withstand voltage (VDS < 42V) High-current drive (IO max = 100mA) • Operating temperature range Ta = -25 to 75°C • Output malfunction protection circuit Reset input pin Thermal protection circuit VCC decrease voltage confirmation Specifications Maximum Ratings at Ta = 25°C Parameter Maximum supply voltage Output voltage Output current Allowable power dissipation Operating temperature Storage temperature Symbol VCC max VO max IO max Pd max Topr Tstg Ta ≤ 25°C * SVCC LEDO1 to LEDO24 off Conditions Ratings 6 42 100 1750 -25 to +75 -40 to +125 Unit V V mA mW °C °C * Specified board : 114.3mm × 76.1mm × 1.6mm, glass epoxy board. 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O0610 SY/33110 SY No.A1693-1/8 LV5233H Operating Conditions at Ta = 25°C Parameter Recommended supply voltage Operating supply voltage range Output applied voltage Output current Symbol VCC VCC op VO IO Duty = 45% to 55% SVCC SVCC Conditions Ratings 5.0 3.0 to 5.5 42 100 Unit V V V mA Electrical Characteristics at Ta = 25°C, VCC = 5.0V Parameter Quiescent current drain LEDO output on resistance OFF leak current Driver output malfunction prevention voltage Control circuit block H level 1 L level 1 H level 2 L level 2 VINH1 VINL1 VOUTH1 VOUTL1 Input H level Input L level SOUT IO = -1mA SOUT IO = 1mA VCC × 0.8 0 VCC -0.3 0 0.3 VCC × 0.2 V V V V Symbol ICC1 Ron Ileak Vt Conditions min LEDO driver off (standby) IO = 30mA VO = 42V 2.58 Ratings typ 0.45 3 0 2.70 10 2.82 max 0.6 mA Ω μA V Unit Package Dimensions unit : mm (typ) 3235A 2.0 Pd max -- Ta Specified board : 114.3 × 76.1 × 1.6mm3 glass epoxy 36 Allowable power dissipation, Pd max -- W 0.65 17.8 (6.2) 2.7 1.5 (4.9) 10.5 7.9 1.0 0.87 1 (0.5) (2.25) 0.8 2.0 0.3 0.25 0.5 2.45max 0 --25 0 25 50 75 100 Ambient temperature, Ta -- C 0.1 SANYO : HSOP36(375mil) Pin Assignment 36 XEN 35 LATCH 34 LEDO13 33 LEDO14 32 LEDO15 31 PGND3 30 LEDO16 29 LEDO17 28 Heat sink &GND LEDO18 27 LEDO19 26 LEDO20 25 LEDO21 24 PGND4 23 LEDO22 22 LEDO23 21 LEDO24 20 SCK SDATAIN 19 SGND XRESET LEDO12 PGND2 Heat sink &GND LEDO11 LEDO10 LEDO2 PGND1 LEDO8 LEDO7 LEDO9 LEDO6 LEDO5 SVCC LEDO4 SOUT LEDO3 LEDO1 Top view 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 No.A1693-2/8 LV5233H Pin Descriptions Pin No. 1 2 3 4 5 6 7 8 9 Heat sink 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 Heat sink 28 29 30 31 32 33 34 35 LEDO18 LEDO17 LEDO16 PGND3 LEDO15 LEDO14 LEDO13 LATCH O O O I O O O LEDO18 Latch output (LEDO18 of shift register) LEDO17 Latch output (LEDO17 of shift register) LEDO16 Latch output (LEDO16 of shift register) GND LEDO15 Latch output (LEDO15 of shift register) LEDO14 Latch output (LEDO14 of shift register) LEDO13 Latch output (LEDO13 of shift register) Latch input When the latch input is held low, the LED0 output status is retained. When a high-level is input, the LED0 outputs change when the status of the shift register changes. 36 XEN I Enable inputs (LEDO1 to LEDO24) When a high-level is input, all the LED0 outputs are turned off. When a low-level is input, the shift register data is output to LED0. LEDO6 LEDO5 LEDO4 PGND1 LEDO3 LEDO2 LEDO1 SDATAIN XRESET SGND SCK LEDO24 LEDO23 LEDO22 PGND4 LEDO21 LEDO20 LEDO19 O O O I O O O O O O I I O O O LEDO6 Latch output (LEDO6 of shift register) LEDO5 Latch output (LEDO5 of shift register) LEDO4 Latch output (LEDO4 of shift register) GND LEDO3 Latch output (LEDO3 of shift register) LEDO2 Latch output (LEDO2 of shift register) LEDO1 Latch output (LEDO1 of shift register) Serial Input Reset input (shift register and latch) GND Clock input (for shift register) LEDO24 Latch output (LEDO24 of shift register) LEDO23 Latch output (LEDO23 of shift register) LEDO22 Latch output (LEDO22 of shift register) GND LEDO21 Latch output (LEDO21 of shift register) LEDO20 Latch output (LEDO20 of shift register) LEDO19 Latch output (LEDO19 of shift register) Pin name SVCC SOUT LEDO12 LEDO11 LEDO10 PGND2 LEDO9 LEDO8 LEDO7 O O O O O O O I/O Power supply shift register output (final-stage shift register) LEDO12 Latch output (LEDO12 of shift register) LEDO11 Latch output (LEDO11 of shift register) LEDO10 Latch output (LEDO10 of shift register) GND LEDO9 Latch output (LEDO9 of shift register) LEDO8 Latch output (LEDO8 of shift register) LEDO7 Latch output (LEDO7 of shift register) Description No.A1693-3/8 LV5233H Block Diagram SCK SDATAIN LATCH XEN SVCC XRESET DQ CQ R DQ CQ R SVCC_protection LEDO1 LEDO2 DQ CQ R DQ CQ R LEDO3 DQ CQ R DQ CQ R LEDO4 LEDO21 LEDO22 DQ CQ R DQ CQ R LEDO23 DQ CQ R DQ CQ R LEDO24 DQ CQ R DQ CQ R DQ CQ R SOUT PGND1 PGND3 SGND PGND2 PGND4 Function The LV5233H consists of 1) an 24-stage D-type flip-flop and 2) an 24-stage D-type flip-flop connected to the output of 1). When data is supplied to the serial data input (SDATAIN) and the clock pulse is supplied to the clock input (SCK), the serial data input signal is input to the internal shift register and the data already in the shift register shifted sequentially when the clock changes from low to high. The serial output (SOUT) is used to connect multiple LV5233H to expand the number of bits and is connected to the SDATAIN of the next stage. (Cascade connection supported.) For parallel output, when the output control enable input (XEN) is low, the latch input (LATCH) changes from low to high and the clock pulse input changes from low to high, the serial data input signal is output to LED01, and the output is shifted sequentially. For parallel outputs (LED2 to LED24), the signals whose polarities inverted from those of the serial data input (SDATAIN) are output. When the EN input is high, outputs LED01 through LED01 all turn off. When the reset input is low, outputs LED01 through LED24 and SOUT outputs all turn off. The power must be turned on after checking that the reset input is low. To prevent the malfunction, the output load protection circuit is built into. The output of LEDO1 to LEDO24 is compulsorily turned off when becoming below the voltage with a constant there is VCC. Moreover, a thermal circuit is built into, and the output of LEDO1 to LEDO24 is turned off compulsorily when becoming it at the temperature that exceeds the temperature of the junction in IC. No.A1693-4/8 LV5233H Pin Functions Pin No. 17 20 Pin Name SDATAIN SCK Pin function Pull-down input Equivalent Circuit SVCC SGND 18 35 36 XRESET LATCH XEN Pull-up input SVCC SGND 2 SOUT SOUT output SVCC SOUT SGND 3 4 5 7 8 9 10 11 12 14 15 16 21 22 23 25 26 27 28 29 30 32 33 34 LEDO12 LEDO11 LEDO10 LEDO9 LEDO8 LEDO7 LEDO6 LEDO5 LEDO4 LEDO3 LEDO2 LEDO1 LEDO24 LEDO23 LEDO22 LEDO21 LEDO20 LEDO19 LEDO18 LEDO17 LEDO16 LEDO15 LEDO14 LEDO13 LEDO outputs LEDO1 to LEDO24 SVCC SGND PGND No.A1693-5/8 LV5233H Timing conditions Parameter Clock frequency Clock pulse width Latch pulse width Data set up time Data hold time Clock latch time Input conditions 1 Input conditions 2 symbol fs1 twck twla ts1 th1 tla1 ton toff SCK and SDATAIN rise time SCL and SDATAIN fall time SCK Duty = 50% SCK LATCH SDATAIN setup time relative to the rise of SCK SDATAIN data hold time relative to the rise of SCK 50 50 25 25 100 100 100 Conditions min typ max 10 unit MHz ns ns ns ns ns ns ns twck SCK ts1 2.5V th1 ton SDATAIN 2.5V 2.5V twla tla1 LATCH 2.5V 2.5V toff 2.5V 10% 90% 90% 10% SOUT output timings Parameter SOUT delay time 1 SOUT delay time 2 symbol tdso1 tdso2 Conditions The time from a SCK falling edge to SOUT rising edge The time from a SCK falling edge to SOUT falling edge min typ max 50 50 unit ns ns SCK 2.5V 2.5V tdso1 tdso2 2.5V SOUT 2.5V No.A1693-6/8 LV5233H LEDO output timings Parameter LEDO delay time 1 symbol tdled1 Conditions The time from an XEN rising edge to LEDO rising edge CL = 30pF, IO = 100mA, VO = 42V LEDO delay time 2 tdled2 The time from an XEN falling edge to LEDO falling edge CL = 30pF, IO = 100mA, VO = 42V LEDO rise time trled LEDO rise time CL = 30pF, IO = 100mA, VO = 42V LEDO fall time tfled LEDO fall time CL = 30pF, IO = 100mA, VO = 42V LEDO delay time 3 tdled3 The time from a LATCH rising edge to LEDO falling edge CL = 30pF, IO = 100mA, VO = 42V 200 ns 200 ns 200 ns 100 ns min typ 100 max unit ns XEN 2.5V 2.5V tdled1 tdled2 90% LEDO 10% trled 90% 10% tfled tdled3 90% 2.5V LATCH Application Circuit Example max:42V 5V SVCC LEDO SVCC SDATAIN SCK LATCH XEN XRESET LEDO sub CPU SDATAIN SCK LATCH XEN XRESET LEDO SOUT LEDO SOUT SGND PGND SGND PGND No.A1693-7/8 LV5233H Allowable output current characteristics IO -- LEDO Ta = 25 C 50 C 100 75 C Output current, IO - mA 90 80 70 60 0 duty syscle 100% 2 4 6 8 10 12 14 16 Number of output ports, LEDO SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein. 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SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's intellctual property rights which has resulted from the use of the technical information and products mentioned above. This catalog provides information as of October, 2010. Specifications and information herein are subject to change without notice. PS No.A1693-8/8