Ordering number : ENA1512
LV5652T
Overview
Bi-CMOS LSI
3-channel Switching Regulator Controller
The LV5652T is a 3-channel switching regulator controller.
Features
• Low-voltage (3V) operation • Reference voltage precision : ±1% • Independent standby functions for each of three channels. • Is capable of driving MOS transistors. • switching regulator controller : 3-channel ch1 : Supports synchronous rectification ch2 : Supports inverting step-up operation ch3 : Supports step-up operation
Specifications
Maximum Ratings at Ta = 25°C
Parameter Maximum supply voltage 1 Maximum supply voltage 2 Maximum clock input voltage Allowable power dissipation Operating temperature Storage temperature Symbol VCC max VBIAS max VCLKIN max Pd max Topr Tstg VCC pin VBIAS pin CLKIN pin Mounted on a specified board* Conditions Ratings -0.3 to 16 -0.3 to 18 5.5 1 -30 to +85 -55 to +125 Unit V V V W °C °C
* Specified board: 114.3mm × 76.1mm × 1.6mm, glass epoxy board.
Recommended Operating Conditions at Ta = 25°C
Parameter Supply voltage 1 Supply voltage 2 Clock input voltage Timing resistor Timing capacitor Triangle wave frequency Symbol VCC VBIAS VCLKIN RT CT fOSC VCC pin VBIAS pin CLKIN pin Conditions Ratings 3 to 15 3 to 15 5 7 to 30 100 to 1000 0.1 to 1.3 Unit V V V kΩ pF MHz
Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment (home appliances, AV equipment, communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee thereof. If you should intend to use our products for applications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our customer shall be solely responsible for the use. Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer' s products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer' s products or equipment.
80509 SY 20080922-S00001 No.A1512-1/9
LV5652T
Electrical Characteristics at Ta = 25°C, VCC = VBIAS = 3.6V, SCP = 0V
Parameter Error amplifier 1 IN+ pin internal bias voltage Output low voltage Output high voltage Error amplifier 2 IN2-RE pin offset voltage Output low voltage Output high voltage Protection circuit Threshold voltage SCP pin current Short circuit detection signal pin Software start block Soft start current Soft start resistance Fixed duty Maximum on duty 1 Maximum on duty 2 Maximum on duty 3 Output block OUT pin high side on resistance OUT pin low side on resistance Triangle wave oscillator block Current setting pin voltage Output current Output current ratio Oscillation frequency Reference voltage block Reference voltage Line regulation Control circuit On state voltage OFF state voltage Pin input current Standby circuit On voltage OFF voltage Pin input current All circuits VCC current consumption Standby mode current consumption ICC IOFF IN1- to IN3- = 1V VSTBY = VCTL = 0V, IOFF = ICC + IBIAS 4 5 1 mA μA VON STBY VOFF STBY IIN STBY 2.0 0.6 60 V V μA VON CTL VOFF CTL IIN CTL 2.0 0.6 60 V V μA VREF VLN REF VCC = 3V to 15V 1.240 10 V mV VT RT IOH CT ∆IO CT fOSC CT pin, rise/fall RT = 10kΩ , CT = 270pF 2 390 RT = 10kΩ 0.57 190 2.5 510 3 620 V μA kHz ROUT SOUR ROUT SINK IO = 10mA IO = 10mA 28 18 50 35 Ω Ω ch1 ch2 ch3 Duty MAX 1 Duty MAX 2 Duty MAX 3 Out monitor , IN- = 0V Out monitor , IN- = 0V Out monitor , IN- = 0V 100 80 80 85 85 90 90 % % % ch1 to ch3 ch1 to ch3 ISF RSF CSOFT = 0V 3.2 160 4 200 4.8 240 μA kΩ VSCP ISCP VSCPOUT Open collector, ISCPOUT = 100μA 1.1 1.25 4 0.2 1.4 V μA V VOFF2 VLow FB2RE VHi FB2RE IN2-RE = 2.0V, IFB = 20μA IN2-RE = -10V, IFB1 = -500μA 2.0 -6 6 0.2 V V V ch1 to ch3 ch1 to ch3 VB VLow FB VHi FB Value added to the error amplifier offset at the error amplifier + side voltage IN- = 2.0V, IFB = 20μA IN- = 0V, IFB1 = -20μA 2.0 0.504 0.51 0.516 0.2 V V V Symbol Conditions Ratings min typ max Unit
No.A1512-2/9
LV5652T
Package Dimensions
unit : mm (typ) 3253B
9.75 36 19
Allowable power dissipation, Pd max --W
Pd max -- Ta
Specified board: 114.3×76.1×1.6mm3 glass epoxy board.
1.0
0.8
5.6
7.6
(0.5) (0.63)
1
0.18
18
0.5
0.6
0.15
0.4
1.2max
(1.0)
0.2
0.08
0 -30 -20
0
Ambient temperature, Ta -- °C
20
40
60
80
100
SANYO : TSSOP36(275mil)
Pin Assignment
VBIAS 1 OUT2 2 OUT3 3 SCPOUT 4 CLKIN 5 STBY3 6 STBY2 7 ( NC ) 8 36 ( NC ) 35 ( NC ) 34 GND_P(VS) 33 OUT1 32 OUT1N 31 CSOFT1 30 ( NC ) 29 CSOFT2
LV5652T
STBY1 9 SCP 10 CTL 11 IN3- 12 FB3 13 IN2+RE 14 IN2-RE 15 FB2RE 16 FB2 17 IN2- 18
28 CSOFT3 27 VCC 26 IN125 FB1 24 ( NC ) 23 ( NC ) 22 VREF 21 CT 20 RT 19 GND_S Top view
No.A1512-3/9
LV5652T
Block Diagram and Sample Application Circuit
VREF VREF
SCP SCP
SCP_OUT VCC
Signal system power supply
FB1A IN1FB1 CSOFT1 FB2A
Pre-output stage VBIAS power supply
+ + -
+
OUT1
FB1A
Step-down (DOWN)
OUT1N
Vo1 3.3V/100mA
IN2-RE IN2+RE FB2RE IN2FB2 CSOFT2
+ + + +
OUT2 FB2A
Inversion (INVERT)
Vo2 -4V/100mA
FB3A IN3FB3 CSOFT3
FB3A
Step-up (UP)
+ + -
+ -
OUT3
Vo3 6V/100mA
ON/OFF Setting GND_P(VS) GND_S
STBY1 STBY2 STBY3 STBY
(Stand by)
OSC
(Oscillation circuit)
CLKIN
CTL
CT
RT
The CLKIN pin must be connected to GND,when the external clock synchronization (CLKIN) is not used.
No.A1512-4/9
LV5652T
Pin Function
Block ch1 (Step-down) Pin No. 9 26 25 31 33 32 ch2 (Inversion) 7 14 15 16 18 17 29 2 ch3 (Step-up) 6 12 13 28 3 POWER 27 1 19 34 22 CONTROL 11 10 4 OSC 21 20 5 OTHER 8 23 24 30 35 36 Pin Name STBY1 IN1FB1 CSOFT1 OUT1 OUT1N STBY2 IN2+RE IN2-RE FB2RE IN2FB2 CSOFT2 OUT2 STBY3 IN3FB3 CSOFT3 OUT3 VCC VBIAS GND_S GND_P (VS) VREF CTL SCP SCPOUT CT RT CLKIN ( NC ) ( NC ) ( NC ) ( NC ) ( NC ) ( NC ) Standby input. H/ch1 ; ON, L/ch1 ; OFF. Error amplifier Inverting input. Error amplifier output. Soft start setting capacitor connection. Connect to GND through a capacitor. Output. External transistor P-channel gate connection. Output. External transistor N-channel gate connection. Standby input. H/ch2 ; ON, L/ch2 ; OFF. Inversion amplifier, +(noninverting) input. Inversion amplifier, -(Inverting) input. Inversion amplifier output. Error amplifier, - (Inverting) input. Error amplifier output. Soft start setting capacitor connection. Connect to GND through a capacitor. Output. External transistor P-channel gate connect. Standby input. H/ch3 ; ON, L/ch3 ; OFF. Error amplifier, - (Inverting) input. Error amplifier output. Soft start setting capacitor connection. Connect to GND through a capacitor. Output. External transistor N-channel gate connect. Power supply input (signal system). Power supply input (pre-output stage). Ground (signal system). Ground (pre-output stage). Reference voltage output. Output control. Connection pin for the delay time setting capacitor of short circuit detection circuit. SCP_OUT pin (SCP output). Triangle wave oscillation frequency setting capacitor connection. Triangle wave oscillation frequency setting resistor connection. External clock input. Not use. Not use. Not use. Not use. Not use. Not use. Functions
No.A1512-5/9
LV5652T
Equivalent Circuits
Pin No. 11 9 7 6 Pin Name CTL STBY1 STBY2 STBY3 Description CTL : Controls operation of all circuits. STBY* : Independently controls operation of the corresponding channel. Operation is high active. High : ON Low : OFF Equivalent Circuit
CTL/STBY*
GND_S
26 18 12 IN1IN2IN3Error amplifier inverting input. The regulator output is divided by a resistor and connected to IN*-
VREG (Internal constant voltage) IN*500Ω
5kΩ
5kΩ GND_S
25 17 13
FB1 FB2 FB3
Error amplifier output. These pins, in combination with IN*-, configure the error amplifier filters
VREG (Internal constant voltage) 20Ω FB* 500Ω
GND_S
14 15 IN2+RE IN2-RE Inversion step-up (Channel2) error amplifier input. These pins, in combination with FB2RE,configure the operational amplifier (independent)
VREG (Internal constant voltage) IN2-RE IN2+RE
GND_S
16 FB2RE Inversion step-up (Channel2) error amplifier output. This pin, in combination with IN2+RE and IN2-RE, configures the operational amplifier (independent)
VREG (Internal constant voltage)
FR2RE
GND_S
Continued on next page.
No.A1512-6/9
LV5652T
Continued from preceding page. Pin No. 31 29 28 Pin Name CSOFT1 CSOFT2 CSOFT3 Soft start. Connect to GND via a capacitor to set the soft start time. Description Equivalent Circuit
VREG (Internal constant voltage) 500Ω 10kΩ 200kΩ GND_S CSOFT*
33 2 3
OUT1 OUT2 OUT3
Output. Connect external PchFET.
VBIAS
OUT*
GND_P (VS)
32 OUT1N Output. Connect external NchFET.
VBIAS
VOUT1N
GND_P (VS)
20 RT Connect to GND through a resistor. This pin, together eith CT, sets the oscillation frequency.
VREG (Internal constant voltage)
RT
GND_S
21 CT Connect to GND through a capacitor. This pin, together eith RT, sets the oscillation frequency.
VREG (Internal constant voltage)
CT
GND_S
4 SCP_OUT Short circuit detection circuit output. When SCP exceeds the threshold voltage, the open collector goes OFF and this pin goes High.
VREG (Internal constant voltage) SCP_OUT
GND_S
Continued on next page.
No.A1512-7/9
LV5652T
Continued from preceding page. Pin No. 10 Pin Name SCP Description Connect to GND via a capacitor to set the short circuit detection circuit delay time. Equivalent Circuit
VREG (Internal constant voltage)
1.5kΩ SCP 13kΩ
GND_S
22 VREF Internal constant voltage circuit output. Connect a stabilizing capacitor.
VREG (Internal constant voltage) VREF
14.8kΩ
GND_S
5 CLKIN External clock input. Apply an external clock of the internal oscillation frequency or higher.
VREG (Internal constant voltage) CLKIN
GND_S
27 1 19 34 8 23 24 30 35 36 VCC VBIAS GND_S GND_P (VS1) ( NC ) ( NC ) ( NC ) ( NC ) ( NC ) ( NC ) Signal system power supply Power system power supply (Output stage) Signal system GND Output stage GND (pre-stage) Use prohibited. (Not connect pins.)
VCC
VBIAS GND_S GND_P (VS)
( NC )
No.A1512-8/9
LV5652T
Notes
(1) Soft start time setting method The soft start time is set with the capacitor connected between CSOFT* and GND_S. This IC has an independent soft start function for each channel, so a capacitor must be connected for each CSOFT to set the soft start time. (Description of soft start operation)
CSOFT* [V] CSOFT* voltage VB (=0.515 [V] (TYP))
(Outline of soft start pin)
VREG (Internal constant voltage) 4μA (ISF)
CSOFT* T [s] Soft start time (Tsoft [s]) CSOFT pin charging starts The output voltage reaches the set voltage (Output voltage constant) VB (0.515[V]) TSOFT = CSOFT × RSFIn ( VB ) RSF × ISF 200kΩ (RSF) GND_S
= 0.206 × 106 × CSOFT [s]
(2) Setting the oscillation frequency The internal oscillation frequency is set by the resistor connected to the RT pin and the capacitor connected to the CT pin. The waveform generated on CT is a triangular wave with the charging/discharging waveform determined by RT and CT. 1 fOSC = 1.32 Х CT Х RT [Hz] The actual internal oscillation frequency deviates from the calculated value due to overshoot, undershoot and other factors, so the frequency should be confirmed in an actual set. (3) External input CLK function (CLK_IN) Switching operation can be synchronized with external clock input (CLK_IN) by using the CLK_IN pin. • External clock (CLK_IN) frequency and input level When using external clock (CLK_IN) input, input a frequency equal to the internal oscillation frequency +20% or more to CLK_IN. In addition, the CLK_IN configuration is shown in the figure “CLK_IN (input) equivalent circuit (outline)” below. The 0.8V reference voltage and CLK_IN are compared to determine the edges, so input a signal of 0.8V or more (VCC voltage or less) as the external clock (CLK_IN). • External/internal clock switching Set the CTL pin Low before switching between the external clock and the internal clock. Switching clocks when running may give rise to output voltage fluctuations. • Maximum ON duty The maximum ON duty (Duty_MAX*) of channel 2 to channel 3 is the 85% (typ.) setting. When using the external clock (CLK_IN), the maximum ON duty (Duty_MAX*) becomes smaller, so care must be taken for the set output voltage. (CLK_IN (input) equivalent circuit (outline))
CLK_IN 0.8V
No.A1512-9/9
LV5652T
(4) SCP (short circuit protection) function • Description of operation When any one of FB1 to FB4 goes High due to the load being shorted or other reason, charging to the SCP pin starts. If output does not recover during the set time Tscp and SCP pin voltage exceeds the threshold voltage, the protective circuit (SCP) operates and all channel outputs are turned OFF. All outputs are latched off by the protection circuit (SCP). This latched state (output OFF) is canceled by setting the CTL pin Low or by turning the power supply OFF. When not using the protection function (SCP), the SCP pin must be shorted to GND_S with a line that is as short as possible. The SCP operation time is set by the capacitor connected to the SCP pin. (SCP charging operation) (SCP function)
⋅When STBY* is regarded as High
SCP [V] Charging with Iscp = 4 [μA] 1.25 [V] (TYP) CTL SCP
(the output is turned on by setting CTL Low to High). Capacitor charging starts with the load being shorted Threshold voltage 1.25V (TYP)
tscp Output short circuit
T [s] SCP operation
SCP_OUT
SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein. SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO Semiconductor Co.,Ltd. products described or contained herein are controlled under any of applicable local export control laws and regulations, such products may require the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written consent of SANYO Semiconductor Co.,Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO Semiconductor Co.,Ltd. product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. Upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third party. SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's intellctual property rights which has resulted from the use of the technical information and products mentioned above.
This catalog provides information as of August, 2009. Specifications and information herein are subject t o change without notice. PS No.A1512-10/10
